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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacket.v] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// sendPacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
 
 
module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
input   clk;
input   [7:0]fifoData;
input   fifoEmpty;
input   fullSpeedPolarity;
input   HCTxPortGnt;
input   HCTxPortRdy;
input   [3:0]PID;
input   rst;
input   sendPacketWEn;
input   [6:0]TxAddr;
input   [3:0]TxEndP;
output  fifoReadEn;
output  [10:0]frameNum;
output  [7:0]HCTxPortCntl;
output  [7:0]HCTxPortData;
output  HCTxPortReq;
output  HCTxPortWEn;
output  sendPacketRdy;
 
wire    clk;
wire    [7:0]fifoData;
wire    fifoEmpty;
reg     fifoReadEn, next_fifoReadEn;
reg     [10:0]frameNum, next_frameNum;
wire    fullSpeedPolarity;
reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
reg     [7:0]HCTxPortData, next_HCTxPortData;
wire    HCTxPortGnt;
wire    HCTxPortRdy;
reg     HCTxPortReq, next_HCTxPortReq;
reg     HCTxPortWEn, next_HCTxPortWEn;
wire    [3:0]PID;
wire    rst;
reg     sendPacketRdy, next_sendPacketRdy;
wire    sendPacketWEn;
wire    [6:0]TxAddr;
wire    [3:0]TxEndP;
 
// diagram signals declarations
reg  [7:0]PIDNotPID;
 
// BINARY ENCODED state machine: sndPkt
// State codes definitions:
`define START_SP 5'b00000
`define WAIT_ENABLE 5'b00001
`define SP_WAIT_GNT 5'b00010
`define SEND_PID_WAIT_RDY 5'b00011
`define SEND_PID_FIN 5'b00100
`define FIN_SP 5'b00101
`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
`define OUT_IN_SETUP_FIN 5'b01000
`define SEND_SOF_FIN1 5'b01001
`define SEND_SOF_WAIT_RDY3 5'b01010
`define SEND_SOF_WAIT_RDY4 5'b01011
`define DATA0_DATA1_READ_FIFO 5'b01100
`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
`define DATA0_DATA1_FIFO_EMPTY 5'b01110
`define DATA0_DATA1_FIN 5'b01111
`define DATA0_DATA1_TERM_BYTE 5'b10000
`define OUT_IN_SETUP_CLR_WEN1 5'b10001
`define SEND_SOF_CLR_WEN1 5'b10010
`define DATA0_DATA1_CLR_WEN 5'b10011
`define DATA0_DATA1_CLR_REN 5'b10100
`define LS_EOP_WAIT_RDY 5'b10101
`define LS_EOP_FIN 5'b10110
 
reg [4:0]CurrState_sndPkt, NextState_sndPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @(PID)
begin
PIDNotPID <=  { (PID ^ 4'hf), PID };
end
 
 
// Machine: sndPkt
 
// NextState logic (combinatorial)
always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
begin
  NextState_sndPkt <= CurrState_sndPkt;
  // Set default values for outputs and signals
  next_sendPacketRdy <= sendPacketRdy;
  next_fifoReadEn <= fifoReadEn;
  next_HCTxPortData <= HCTxPortData;
  next_HCTxPortCntl <= HCTxPortCntl;
  next_HCTxPortWEn <= HCTxPortWEn;
  next_HCTxPortReq <= HCTxPortReq;
  next_frameNum <= frameNum;
  case (CurrState_sndPkt)  // synopsys parallel_case full_case
    `START_SP:
    begin
      NextState_sndPkt <= `WAIT_ENABLE;
    end
    `WAIT_ENABLE:
    begin
      if (sendPacketWEn == 1'b1)
      begin
        NextState_sndPkt <= `SP_WAIT_GNT;
        next_sendPacketRdy <= 1'b0;
        next_HCTxPortReq <= 1'b1;
      end
    end
    `SP_WAIT_GNT:
    begin
      if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
      begin
        NextState_sndPkt <= `LS_EOP_WAIT_RDY;
      end
      else if (HCTxPortGnt == 1'b1)
      begin
        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
      end
    end
    `FIN_SP:
    begin
      NextState_sndPkt <= `WAIT_ENABLE;
      next_sendPacketRdy <= 1'b1;
      next_HCTxPortReq <= 1'b0;
    end
    `SEND_PID_WAIT_RDY:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `SEND_PID_FIN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= PIDNotPID;
        next_HCTxPortCntl <= `TX_PACKET_START;
      end
    end
    `SEND_PID_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      if (PID == `DATA0 || PID == `DATA1)
      begin
        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
      end
      else if (PID == `SOF)
      begin
        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
      end
      else if (PID == `OUT ||
        PID == `IN ||
        PID == `SETUP)
      begin
        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
      end
      else
      begin
        NextState_sndPkt <= `FIN_SP;
      end
    end
    `OUT_IN_SETUP_WAIT_RDY1:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
        next_HCTxPortCntl <= `TX_PACKET_STREAM;
      end
    end
    `OUT_IN_SETUP_WAIT_RDY2:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
        next_HCTxPortCntl <= `TX_PACKET_STREAM;
      end
    end
    `OUT_IN_SETUP_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `FIN_SP;
    end
    `OUT_IN_SETUP_CLR_WEN1:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
    end
    `SEND_SOF_FIN1:
    begin
      next_HCTxPortWEn <= 1'b0;
      next_frameNum <= frameNum + 1'b1;
      NextState_sndPkt <= `FIN_SP;
    end
    `SEND_SOF_WAIT_RDY3:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= frameNum[7:0];
        next_HCTxPortCntl <= `TX_PACKET_STREAM;
      end
    end
    `SEND_SOF_WAIT_RDY4:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `SEND_SOF_FIN1;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
        next_HCTxPortCntl <= `TX_PACKET_STREAM;
      end
    end
    `SEND_SOF_CLR_WEN1:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
    end
    `DATA0_DATA1_READ_FIFO:
    begin
      next_HCTxPortWEn <= 1'b1;
      next_HCTxPortData <= fifoData;
      next_HCTxPortCntl <= `TX_PACKET_STREAM;
      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
    end
    `DATA0_DATA1_WAIT_READ_FIFO:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
        next_fifoReadEn <= 1'b1;
      end
    end
    `DATA0_DATA1_FIFO_EMPTY:
    begin
      if (fifoEmpty == 1'b0)
      begin
        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
      end
      else
      begin
        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
      end
    end
    `DATA0_DATA1_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `FIN_SP;
    end
    `DATA0_DATA1_TERM_BYTE:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `DATA0_DATA1_FIN;
        //Last byte is not valid data,
        //but the 'TX_PACKET_STOP' flag is required
        //by the SIE state machine to detect end of data packet
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= 8'h00;
        next_HCTxPortCntl <= `TX_PACKET_STOP;
      end
    end
    `DATA0_DATA1_CLR_WEN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
    end
    `DATA0_DATA1_CLR_REN:
    begin
      next_fifoReadEn <= 1'b0;
      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
    end
    `LS_EOP_WAIT_RDY:
    begin
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `LS_EOP_FIN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= 8'h00;
        next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
      end
    end
    `LS_EOP_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `FIN_SP;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_sndPkt <= `START_SP;
  else
    CurrState_sndPkt <= NextState_sndPkt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    sendPacketRdy <= 1'b1;
    fifoReadEn <= 1'b0;
    HCTxPortData <= 8'h00;
    HCTxPortCntl <= 8'h00;
    HCTxPortWEn <= 1'b0;
    HCTxPortReq <= 1'b0;
    frameNum <= 11'h000;
  end
  else
  begin
    sendPacketRdy <= next_sendPacketRdy;
    fifoReadEn <= next_fifoReadEn;
    HCTxPortData <= next_HCTxPortData;
    HCTxPortCntl <= next_HCTxPortCntl;
    HCTxPortWEn <= next_HCTxPortWEn;
    HCTxPortReq <= next_HCTxPortReq;
    frameNum <= next_frameNum;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// sendPacket`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbConstants_h.v"
48
49
50
51	14	sfielding	`module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);`
52	5	sfielding	`input clk;`
53			`input [7:0]fifoData;`
54			`input fifoEmpty;`
55	14	sfielding	`input fullSpeedPolarity;`
56	5	sfielding	`input HCTxPortGnt;`
57			`input HCTxPortRdy;`
58			`input [3:0]PID;`
59			`input rst;`
60			`input sendPacketWEn;`
61			`input [6:0]TxAddr;`
62			`input [3:0]TxEndP;`
63			`output fifoReadEn;`
64			`output [10:0]frameNum;`
65			`output [7:0]HCTxPortCntl;`
66			`output [7:0]HCTxPortData;`
67			`output HCTxPortReq;`
68			`output HCTxPortWEn;`
69			`output sendPacketRdy;`
70
71			`wire clk;`
72			`wire [7:0]fifoData;`
73			`wire fifoEmpty;`
74			`reg fifoReadEn, next_fifoReadEn;`
75			`reg [10:0]frameNum, next_frameNum;`
76	14	sfielding	`wire fullSpeedPolarity;`
77	5	sfielding	`reg [7:0]HCTxPortCntl, next_HCTxPortCntl;`
78			`reg [7:0]HCTxPortData, next_HCTxPortData;`
79			`wire HCTxPortGnt;`
80			`wire HCTxPortRdy;`
81			`reg HCTxPortReq, next_HCTxPortReq;`
82			`reg HCTxPortWEn, next_HCTxPortWEn;`
83			`wire [3:0]PID;`
84			`wire rst;`
85			`reg sendPacketRdy, next_sendPacketRdy;`
86			`wire sendPacketWEn;`
87			`wire [6:0]TxAddr;`
88			`wire [3:0]TxEndP;`
89
90			`// diagram signals declarations`
91			`reg [7:0]PIDNotPID;`
92
93			`// BINARY ENCODED state machine: sndPkt`
94			`// State codes definitions:`
95			`define START_SP 5'b00000
96			`define WAIT_ENABLE 5'b00001
97			`define SP_WAIT_GNT 5'b00010
98			`define SEND_PID_WAIT_RDY 5'b00011
99			`define SEND_PID_FIN 5'b00100
100			`define FIN_SP 5'b00101
101			`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
102			`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
103			`define OUT_IN_SETUP_FIN 5'b01000
104			`define SEND_SOF_FIN1 5'b01001
105			`define SEND_SOF_WAIT_RDY3 5'b01010
106			`define SEND_SOF_WAIT_RDY4 5'b01011
107			`define DATA0_DATA1_READ_FIFO 5'b01100
108			`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
109			`define DATA0_DATA1_FIFO_EMPTY 5'b01110
110			`define DATA0_DATA1_FIN 5'b01111
111			`define DATA0_DATA1_TERM_BYTE 5'b10000
112			`define OUT_IN_SETUP_CLR_WEN1 5'b10001
113			`define SEND_SOF_CLR_WEN1 5'b10010
114			`define DATA0_DATA1_CLR_WEN 5'b10011
115			`define DATA0_DATA1_CLR_REN 5'b10100
116	14	sfielding	`define LS_EOP_WAIT_RDY 5'b10101
117			`define LS_EOP_FIN 5'b10110
118	5	sfielding
119			`reg [4:0]CurrState_sndPkt, NextState_sndPkt;`
120
121			`// Diagram actions (continuous assignments allowed only: assign ...)`
122			`always @(PID)`
123			`begin`
124			`PIDNotPID <= { (PID ^ 4'hf), PID };`
125			`end`
126
127
128			`// Machine: sndPkt`
129
130			`// NextState logic (combinatorial)`
131	14	sfielding	`always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)`
132	5	sfielding	`begin`
133			`NextState_sndPkt <= CurrState_sndPkt;`
134			`// Set default values for outputs and signals`
135			`next_sendPacketRdy <= sendPacketRdy;`
136			`next_fifoReadEn <= fifoReadEn;`
137			`next_HCTxPortData <= HCTxPortData;`
138			`next_HCTxPortCntl <= HCTxPortCntl;`
139			`next_HCTxPortWEn <= HCTxPortWEn;`
140			`next_HCTxPortReq <= HCTxPortReq;`
141			`next_frameNum <= frameNum;`
142			`case (CurrState_sndPkt) // synopsys parallel_case full_case`
143			`START_SP:
144			`begin`
145			NextState_sndPkt <= `WAIT_ENABLE;
146			`end`
147			`WAIT_ENABLE:
148			`begin`
149			`if (sendPacketWEn == 1'b1)`
150			`begin`
151			NextState_sndPkt <= `SP_WAIT_GNT;
152			`next_sendPacketRdy <= 1'b0;`
153			`next_HCTxPortReq <= 1'b1;`
154			`end`
155			`end`
156			`SP_WAIT_GNT:
157			`begin`
158	14	sfielding	if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
159	5	sfielding	`begin`
160	14	sfielding	NextState_sndPkt <= `LS_EOP_WAIT_RDY;
161			`end`
162			`else if (HCTxPortGnt == 1'b1)`
163			`begin`
164	5	sfielding	NextState_sndPkt <= `SEND_PID_WAIT_RDY;
165			`end`
166			`end`
167			`FIN_SP:
168			`begin`
169			NextState_sndPkt <= `WAIT_ENABLE;
170			`next_sendPacketRdy <= 1'b1;`
171			`next_HCTxPortReq <= 1'b0;`
172			`end`
173			`SEND_PID_WAIT_RDY:
174			`begin`
175			`if (HCTxPortRdy == 1'b1)`
176			`begin`
177			NextState_sndPkt <= `SEND_PID_FIN;
178			`next_HCTxPortWEn <= 1'b1;`
179			`next_HCTxPortData <= PIDNotPID;`
180			next_HCTxPortCntl <= `TX_PACKET_START;
181			`end`
182			`end`
183			`SEND_PID_FIN:
184			`begin`
185			`next_HCTxPortWEn <= 1'b0;`
186			if (PID == `DATA0 \|\| PID == `DATA1)
187			`begin`
188			NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
189			`end`
190			else if (PID == `SOF)
191			`begin`
192			NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
193			`end`
194			else if (PID == `OUT \|\|
195			PID == `IN \|\|
196			PID == `SETUP)
197			`begin`
198			NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
199			`end`
200			`else`
201			`begin`
202			NextState_sndPkt <= `FIN_SP;
203			`end`
204			`end`
205			`OUT_IN_SETUP_WAIT_RDY1:
206			`begin`
207			`if (HCTxPortRdy == 1'b1)`
208			`begin`
209			NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
210			`next_HCTxPortWEn <= 1'b1;`
211			`next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};`
212			next_HCTxPortCntl <= `TX_PACKET_STREAM;
213			`end`
214			`end`
215			`OUT_IN_SETUP_WAIT_RDY2:
216			`begin`
217			`if (HCTxPortRdy == 1'b1)`
218			`begin`
219			NextState_sndPkt <= `OUT_IN_SETUP_FIN;
220			`next_HCTxPortWEn <= 1'b1;`
221			`next_HCTxPortData <= {5'b00000, TxEndP[3:1]};`
222			next_HCTxPortCntl <= `TX_PACKET_STREAM;
223			`end`
224			`end`
225			`OUT_IN_SETUP_FIN:
226			`begin`
227			`next_HCTxPortWEn <= 1'b0;`
228			NextState_sndPkt <= `FIN_SP;
229			`end`
230			`OUT_IN_SETUP_CLR_WEN1:
231			`begin`
232			`next_HCTxPortWEn <= 1'b0;`
233			NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
234			`end`
235			`SEND_SOF_FIN1:
236			`begin`
237			`next_HCTxPortWEn <= 1'b0;`
238			`next_frameNum <= frameNum + 1'b1;`
239			NextState_sndPkt <= `FIN_SP;
240			`end`
241			`SEND_SOF_WAIT_RDY3:
242			`begin`
243			`if (HCTxPortRdy == 1'b1)`
244			`begin`
245			NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
246			`next_HCTxPortWEn <= 1'b1;`
247			`next_HCTxPortData <= frameNum[7:0];`
248			next_HCTxPortCntl <= `TX_PACKET_STREAM;
249			`end`
250			`end`
251			`SEND_SOF_WAIT_RDY4:
252			`begin`
253			`if (HCTxPortRdy == 1'b1)`
254			`begin`
255			NextState_sndPkt <= `SEND_SOF_FIN1;
256			`next_HCTxPortWEn <= 1'b1;`
257			`next_HCTxPortData <= {5'b00000, frameNum[10:8]};`
258			next_HCTxPortCntl <= `TX_PACKET_STREAM;
259			`end`
260			`end`
261			`SEND_SOF_CLR_WEN1:
262			`begin`
263			`next_HCTxPortWEn <= 1'b0;`
264			NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
265			`end`
266			`DATA0_DATA1_READ_FIFO:
267			`begin`
268			`next_HCTxPortWEn <= 1'b1;`
269			`next_HCTxPortData <= fifoData;`
270			next_HCTxPortCntl <= `TX_PACKET_STREAM;
271			NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
272			`end`
273			`DATA0_DATA1_WAIT_READ_FIFO:
274			`begin`
275			`if (HCTxPortRdy == 1'b1)`
276			`begin`
277			NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
278			`next_fifoReadEn <= 1'b1;`
279			`end`
280			`end`
281			`DATA0_DATA1_FIFO_EMPTY:
282			`begin`
283			`if (fifoEmpty == 1'b0)`
284			`begin`
285			NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
286			`end`
287			`else`
288			`begin`
289			NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
290			`end`
291			`end`
292			`DATA0_DATA1_FIN:
293			`begin`
294			`next_HCTxPortWEn <= 1'b0;`
295			NextState_sndPkt <= `FIN_SP;
296			`end`
297			`DATA0_DATA1_TERM_BYTE:
298			`begin`
299			`if (HCTxPortRdy == 1'b1)`
300			`begin`
301			NextState_sndPkt <= `DATA0_DATA1_FIN;
302			`//Last byte is not valid data,`
303			`//but the 'TX_PACKET_STOP' flag is required`
304			`//by the SIE state machine to detect end of data packet`
305			`next_HCTxPortWEn <= 1'b1;`
306			`next_HCTxPortData <= 8'h00;`
307			next_HCTxPortCntl <= `TX_PACKET_STOP;
308			`end`
309			`end`
310			`DATA0_DATA1_CLR_WEN:
311			`begin`
312			`next_HCTxPortWEn <= 1'b0;`
313			NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
314			`end`
315			`DATA0_DATA1_CLR_REN:
316			`begin`
317			`next_fifoReadEn <= 1'b0;`
318			NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
319			`end`
320	14	sfielding	`LS_EOP_WAIT_RDY:
321			`begin`
322			`if (HCTxPortRdy == 1'b1)`
323			`begin`
324			NextState_sndPkt <= `LS_EOP_FIN;
325			`next_HCTxPortWEn <= 1'b1;`
326			`next_HCTxPortData <= 8'h00;`
327			next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
328			`end`
329			`end`
330			`LS_EOP_FIN:
331			`begin`
332			`next_HCTxPortWEn <= 1'b0;`
333			NextState_sndPkt <= `FIN_SP;
334			`end`
335	5	sfielding	`endcase`
336			`end`
337
338			`// Current State Logic (sequential)`
339			`always @ (posedge clk)`
340			`begin`
341			`if (rst)`
342			CurrState_sndPkt <= `START_SP;
343			`else`
344			`CurrState_sndPkt <= NextState_sndPkt;`
345			`end`
346
347			`// Registered outputs logic`
348			`always @ (posedge clk)`
349			`begin`
350			`if (rst)`
351			`begin`
352			`sendPacketRdy <= 1'b1;`
353			`fifoReadEn <= 1'b0;`
354			`HCTxPortData <= 8'h00;`
355			`HCTxPortCntl <= 8'h00;`
356			`HCTxPortWEn <= 1'b0;`
357			`HCTxPortReq <= 1'b0;`
358			`frameNum <= 11'h000;`
359			`end`
360			`else`
361			`begin`
362			`sendPacketRdy <= next_sendPacketRdy;`
363			`fifoReadEn <= next_fifoReadEn;`
364			`HCTxPortData <= next_HCTxPortData;`
365			`HCTxPortCntl <= next_HCTxPortCntl;`
366			`HCTxPortWEn <= next_HCTxPortWEn;`
367			`HCTxPortReq <= next_HCTxPortReq;`
368			`frameNum <= next_frameNum;`
369			`end`
370			`end`
371
372	2	sfielding	`endmodule`

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