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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacket.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : 
// Company     : 
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacket.v
// Generated   : 09/25/04 06:36:27
// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacket.asf
// By          : FSM2VHDL ver. 4.0.5.2
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
 
 
module sendPacket (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, rst, sendPacketRdy, sendPacketWEn);
input   HCTxPortGnt;
input   HCTxPortRdy;
input   [3:0] PID;
input   [6:0] TxAddr;
input   clk;
input   [7:0] fifoData;
input   fifoEmpty;
input   rst;
input   sendPacketWEn;
output  [7:0] HCTxPortCntl;
output  [7:0] HCTxPortData;
output  HCTxPortReq;
output  HCTxPortWEn;
output  [3:0] TxEndP;
output  fifoReadEn;
output  [10:0] frameNum;
output  sendPacketRdy;
 
reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
reg     [7:0] HCTxPortData, next_HCTxPortData;
wire    HCTxPortGnt;
wire    HCTxPortRdy;
reg     HCTxPortReq, next_HCTxPortReq;
reg     HCTxPortWEn, next_HCTxPortWEn;
wire    [3:0] PID;
wire    [6:0] TxAddr;
reg     [3:0] TxEndP, next_TxEndP;
wire    clk;
wire    [7:0] fifoData;
wire    fifoEmpty;
reg     fifoReadEn, next_fifoReadEn;
reg     [10:0] frameNum, next_frameNum;
wire    rst;
reg     sendPacketRdy, next_sendPacketRdy;
wire    sendPacketWEn;
 
// diagram signals declarations
reg  [7:0]PIDNotPID;
 
// BINARY ENCODED state machine: sndPkt
// State codes definitions:
`define START_SP 5'b00000
`define WAIT_ENABLE 5'b00001
`define SP_WAIT_GNT 5'b00010
`define SEND_PID_WAIT_RDY 5'b00011
`define SEND_PID_FIN 5'b00100
`define FIN_SP 5'b00101
`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
`define OUT_IN_SETUP_FIN 5'b01000
`define SEND_SOF_FIN1 5'b01001
`define SEND_SOF_WAIT_RDY3 5'b01010
`define SEND_SOF_WAIT_RDY4 5'b01011
`define DATA0_DATA1_READ_FIFO 5'b01100
`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
`define DATA0_DATA1_FIFO_EMPTY 5'b01110
`define DATA0_DATA1_FIN 5'b01111
`define DATA0_DATA1_TERM_BYTE 5'b10000
`define OUT_IN_SETUP_CLR_WEN1 5'b10001
`define SEND_SOF_CLR_WEN1 5'b10010
`define DATA0_DATA1_CLR_WEN 5'b10011
`define DATA0_DATA1_CLR_REN 5'b10100
 
reg [4:0] CurrState_sndPkt;
reg [4:0] NextState_sndPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @(PID)
begin
    PIDNotPID <=  { (PID ^ 4'hf), PID };
end
 
 
//--------------------------------------------------------------------
// Machine: sndPkt
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PID or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)
begin : sndPkt_NextState
        NextState_sndPkt <= CurrState_sndPkt;
        // Set default values for outputs and signals
        next_sendPacketRdy <= sendPacketRdy;
        next_HCTxPortReq <= HCTxPortReq;
        next_HCTxPortWEn <= HCTxPortWEn;
        next_HCTxPortData <= HCTxPortData;
        next_HCTxPortCntl <= HCTxPortCntl;
        next_frameNum <= frameNum;
        next_fifoReadEn <= fifoReadEn;
        case (CurrState_sndPkt) // synopsys parallel_case full_case
                `START_SP:
                        NextState_sndPkt <= `WAIT_ENABLE;
                `WAIT_ENABLE:
                        if (sendPacketWEn == 1'b1)
                        begin
                                NextState_sndPkt <= `SP_WAIT_GNT;
                                next_sendPacketRdy <= 1'b0;
                                next_HCTxPortReq <= 1'b1;
                        end
                `SP_WAIT_GNT:
                        if (HCTxPortGnt == 1'b1)
                                NextState_sndPkt <= `SEND_PID_WAIT_RDY;
                `FIN_SP:
                begin
                        NextState_sndPkt <= `WAIT_ENABLE;
                        next_sendPacketRdy <= 1'b1;
                        next_HCTxPortReq <= 1'b0;
                end
                `SEND_PID_WAIT_RDY:
                        if (HCTxPortRdy == 1'b1)
                        begin
                                NextState_sndPkt <= `SEND_PID_FIN;
                                next_HCTxPortWEn <= 1'b1;
                                next_HCTxPortData <= PIDNotPID;
                                next_HCTxPortCntl <= `TX_PACKET_START;
                        end
                `SEND_PID_FIN:
                begin
                        next_HCTxPortWEn <= 1'b0;
                        if (PID == `DATA0 || PID == `DATA1)
                                NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
                        else if (PID == `SOF)
                                NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
                        else if (PID == `OUT ||
                                PID == `IN ||
                                PID == `SETUP)
                                NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
                        else
                                NextState_sndPkt <= `FIN_SP;
                end
                `OUT_IN_SETUP_WAIT_RDY1:
                        if (HCTxPortRdy == 1'b1)
                        begin
                                NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
                                next_HCTxPortWEn <= 1'b1;
                                next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
                                next_HCTxPortCntl <= `TX_PACKET_STREAM;
                        end
                `OUT_IN_SETUP_WAIT_RDY2:
                        if (HCTxPortRdy == 1'b1)
                        begin
                                NextState_sndPkt <= `OUT_IN_SETUP_FIN;
                                next_HCTxPortWEn <= 1'b1;
                                next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
                                next_HCTxPortCntl <= `TX_PACKET_STREAM;
                        end
                `OUT_IN_SETUP_FIN:
                begin
                        next_HCTxPortWEn <= 1'b0;
                        NextState_sndPkt <= `FIN_SP;
                end
                `OUT_IN_SETUP_CLR_WEN1:
                begin
                        next_HCTxPortWEn <= 1'b0;
                        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
                end
                `SEND_SOF_FIN1:
                begin
                        next_HCTxPortWEn <= 1'b0;
                        next_frameNum <= frameNum + 1'b1;
                        NextState_sndPkt <= `FIN_SP;
                end
                `SEND_SOF_WAIT_RDY3:
                        if (HCTxPortRdy == 1'b1)
                        begin
                                NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
                                next_HCTxPortWEn <= 1'b1;
                                next_HCTxPortData <= frameNum[7:0];
                                next_HCTxPortCntl <= `TX_PACKET_STREAM;
                        end
                `SEND_SOF_WAIT_RDY4:
                        if (HCTxPortRdy == 1'b1)
                        begin
                                NextState_sndPkt <= `SEND_SOF_FIN1;
                                next_HCTxPortWEn <= 1'b1;
                                next_HCTxPortData <= {5'b00000, frameNum[10:8]};
                                next_HCTxPortCntl <= `TX_PACKET_STREAM;
                        end
                `SEND_SOF_CLR_WEN1:
                begin
                        next_HCTxPortWEn <= 1'b0;
                        NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
                end
                `DATA0_DATA1_READ_FIFO:
                begin
                        next_HCTxPortWEn <= 1'b1;
                        next_HCTxPortData <= fifoData;
                        next_HCTxPortCntl <= `TX_PACKET_STREAM;
                        NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
                end
                `DATA0_DATA1_WAIT_READ_FIFO:
                        if (HCTxPortRdy == 1'b1)
                        begin
                                NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
                                next_fifoReadEn <= 1'b1;
                        end
                `DATA0_DATA1_FIFO_EMPTY:
                        if (fifoEmpty == 1'b0)
                                NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
                        else
                                NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
                `DATA0_DATA1_FIN:
                begin
                        next_HCTxPortWEn <= 1'b0;
                        NextState_sndPkt <= `FIN_SP;
                end
                `DATA0_DATA1_TERM_BYTE:
                        if (HCTxPortRdy == 1'b1)
                        begin
                                NextState_sndPkt <= `DATA0_DATA1_FIN;
                                //Last byte is not valid data,
                                //but the 'TX_PACKET_STOP' flag is required
                                //by the SIE state machine to detect end of data packet
                                next_HCTxPortWEn <= 1'b1;
                                next_HCTxPortData <= 8'h00;
                                next_HCTxPortCntl <= `TX_PACKET_STOP;
                        end
                `DATA0_DATA1_CLR_WEN:
                begin
                        next_HCTxPortWEn <= 1'b0;
                        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
                end
                `DATA0_DATA1_CLR_REN:
                begin
                        next_fifoReadEn <= 1'b0;
                        NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
                end
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sndPkt_CurrentState
        if (rst)
                CurrState_sndPkt <= `START_SP;
        else
                CurrState_sndPkt <= NextState_sndPkt;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sndPkt_RegOutput
        if (rst)
        begin
                sendPacketRdy <= 1'b1;
                HCTxPortReq <= 1'b0;
                HCTxPortWEn <= 1'b0;
                HCTxPortData <= 8'h00;
                HCTxPortCntl <= 8'h00;
                frameNum <= 11'h000;
                fifoReadEn <= 1'b0;
        end
        else
        begin
                sendPacketRdy <= next_sendPacketRdy;
                HCTxPortReq <= next_HCTxPortReq;
                HCTxPortWEn <= next_HCTxPortWEn;
                HCTxPortData <= next_HCTxPortData;
                HCTxPortCntl <= next_HCTxPortCntl;
                frameNum <= next_frameNum;
                fifoReadEn <= next_fifoReadEn;
        end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacket.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author :`
6			`// Company :`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacket.v`
11			`// Generated : 09/25/04 06:36:27`
12			`// From : c:\projects\USBHostSlave\RTL\hostController\sendpacket.asf`
13			`// By : FSM2VHDL ver. 4.0.5.2`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbSerialInterfaceEngine_h.v"
23			`include "usbConstants_h.v"
24
25
26
27			`module sendPacket (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, rst, sendPacketRdy, sendPacketWEn);`
28			`input HCTxPortGnt;`
29			`input HCTxPortRdy;`
30			`input [3:0] PID;`
31			`input [6:0] TxAddr;`
32			`input clk;`
33			`input [7:0] fifoData;`
34			`input fifoEmpty;`
35			`input rst;`
36			`input sendPacketWEn;`
37			`output [7:0] HCTxPortCntl;`
38			`output [7:0] HCTxPortData;`
39			`output HCTxPortReq;`
40			`output HCTxPortWEn;`
41			`output [3:0] TxEndP;`
42			`output fifoReadEn;`
43			`output [10:0] frameNum;`
44			`output sendPacketRdy;`
45
46			`reg [7:0] HCTxPortCntl, next_HCTxPortCntl;`
47			`reg [7:0] HCTxPortData, next_HCTxPortData;`
48			`wire HCTxPortGnt;`
49			`wire HCTxPortRdy;`
50			`reg HCTxPortReq, next_HCTxPortReq;`
51			`reg HCTxPortWEn, next_HCTxPortWEn;`
52			`wire [3:0] PID;`
53			`wire [6:0] TxAddr;`
54			`reg [3:0] TxEndP, next_TxEndP;`
55			`wire clk;`
56			`wire [7:0] fifoData;`
57			`wire fifoEmpty;`
58			`reg fifoReadEn, next_fifoReadEn;`
59			`reg [10:0] frameNum, next_frameNum;`
60			`wire rst;`
61			`reg sendPacketRdy, next_sendPacketRdy;`
62			`wire sendPacketWEn;`
63
64			`// diagram signals declarations`
65			`reg [7:0]PIDNotPID;`
66
67			`// BINARY ENCODED state machine: sndPkt`
68			`// State codes definitions:`
69			`define START_SP 5'b00000
70			`define WAIT_ENABLE 5'b00001
71			`define SP_WAIT_GNT 5'b00010
72			`define SEND_PID_WAIT_RDY 5'b00011
73			`define SEND_PID_FIN 5'b00100
74			`define FIN_SP 5'b00101
75			`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
76			`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
77			`define OUT_IN_SETUP_FIN 5'b01000
78			`define SEND_SOF_FIN1 5'b01001
79			`define SEND_SOF_WAIT_RDY3 5'b01010
80			`define SEND_SOF_WAIT_RDY4 5'b01011
81			`define DATA0_DATA1_READ_FIFO 5'b01100
82			`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
83			`define DATA0_DATA1_FIFO_EMPTY 5'b01110
84			`define DATA0_DATA1_FIN 5'b01111
85			`define DATA0_DATA1_TERM_BYTE 5'b10000
86			`define OUT_IN_SETUP_CLR_WEN1 5'b10001
87			`define SEND_SOF_CLR_WEN1 5'b10010
88			`define DATA0_DATA1_CLR_WEN 5'b10011
89			`define DATA0_DATA1_CLR_REN 5'b10100
90
91			`reg [4:0] CurrState_sndPkt;`
92			`reg [4:0] NextState_sndPkt;`
93
94			`// Diagram actions (continuous assignments allowed only: assign ...)`
95			`always @(PID)`
96			`begin`
97			`PIDNotPID <= { (PID ^ 4'hf), PID };`
98			`end`
99
100
101			`//--------------------------------------------------------------------`
102			`// Machine: sndPkt`
103			`//--------------------------------------------------------------------`
104			`//----------------------------------`
105			`// NextState logic (combinatorial)`
106			`//----------------------------------`
107			`always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PID or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)`
108			`begin : sndPkt_NextState`
109			`NextState_sndPkt <= CurrState_sndPkt;`
110			`// Set default values for outputs and signals`
111			`next_sendPacketRdy <= sendPacketRdy;`
112			`next_HCTxPortReq <= HCTxPortReq;`
113			`next_HCTxPortWEn <= HCTxPortWEn;`
114			`next_HCTxPortData <= HCTxPortData;`
115			`next_HCTxPortCntl <= HCTxPortCntl;`
116			`next_frameNum <= frameNum;`
117			`next_fifoReadEn <= fifoReadEn;`
118			`case (CurrState_sndPkt) // synopsys parallel_case full_case`
119			`START_SP:
120			NextState_sndPkt <= `WAIT_ENABLE;
121			`WAIT_ENABLE:
122			`if (sendPacketWEn == 1'b1)`
123			`begin`
124			NextState_sndPkt <= `SP_WAIT_GNT;
125			`next_sendPacketRdy <= 1'b0;`
126			`next_HCTxPortReq <= 1'b1;`
127			`end`
128			`SP_WAIT_GNT:
129			`if (HCTxPortGnt == 1'b1)`
130			NextState_sndPkt <= `SEND_PID_WAIT_RDY;
131			`FIN_SP:
132			`begin`
133			NextState_sndPkt <= `WAIT_ENABLE;
134			`next_sendPacketRdy <= 1'b1;`
135			`next_HCTxPortReq <= 1'b0;`
136			`end`
137			`SEND_PID_WAIT_RDY:
138			`if (HCTxPortRdy == 1'b1)`
139			`begin`
140			NextState_sndPkt <= `SEND_PID_FIN;
141			`next_HCTxPortWEn <= 1'b1;`
142			`next_HCTxPortData <= PIDNotPID;`
143			next_HCTxPortCntl <= `TX_PACKET_START;
144			`end`
145			`SEND_PID_FIN:
146			`begin`
147			`next_HCTxPortWEn <= 1'b0;`
148			if (PID == `DATA0 \|\| PID == `DATA1)
149			NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
150			else if (PID == `SOF)
151			NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
152			else if (PID == `OUT \|\|
153			PID == `IN \|\|
154			PID == `SETUP)
155			NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
156			`else`
157			NextState_sndPkt <= `FIN_SP;
158			`end`
159			`OUT_IN_SETUP_WAIT_RDY1:
160			`if (HCTxPortRdy == 1'b1)`
161			`begin`
162			NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
163			`next_HCTxPortWEn <= 1'b1;`
164			`next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};`
165			next_HCTxPortCntl <= `TX_PACKET_STREAM;
166			`end`
167			`OUT_IN_SETUP_WAIT_RDY2:
168			`if (HCTxPortRdy == 1'b1)`
169			`begin`
170			NextState_sndPkt <= `OUT_IN_SETUP_FIN;
171			`next_HCTxPortWEn <= 1'b1;`
172			`next_HCTxPortData <= {5'b00000, TxEndP[3:1]};`
173			next_HCTxPortCntl <= `TX_PACKET_STREAM;
174			`end`
175			`OUT_IN_SETUP_FIN:
176			`begin`
177			`next_HCTxPortWEn <= 1'b0;`
178			NextState_sndPkt <= `FIN_SP;
179			`end`
180			`OUT_IN_SETUP_CLR_WEN1:
181			`begin`
182			`next_HCTxPortWEn <= 1'b0;`
183			NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
184			`end`
185			`SEND_SOF_FIN1:
186			`begin`
187			`next_HCTxPortWEn <= 1'b0;`
188			`next_frameNum <= frameNum + 1'b1;`
189			NextState_sndPkt <= `FIN_SP;
190			`end`
191			`SEND_SOF_WAIT_RDY3:
192			`if (HCTxPortRdy == 1'b1)`
193			`begin`
194			NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
195			`next_HCTxPortWEn <= 1'b1;`
196			`next_HCTxPortData <= frameNum[7:0];`
197			next_HCTxPortCntl <= `TX_PACKET_STREAM;
198			`end`
199			`SEND_SOF_WAIT_RDY4:
200			`if (HCTxPortRdy == 1'b1)`
201			`begin`
202			NextState_sndPkt <= `SEND_SOF_FIN1;
203			`next_HCTxPortWEn <= 1'b1;`
204			`next_HCTxPortData <= {5'b00000, frameNum[10:8]};`
205			next_HCTxPortCntl <= `TX_PACKET_STREAM;
206			`end`
207			`SEND_SOF_CLR_WEN1:
208			`begin`
209			`next_HCTxPortWEn <= 1'b0;`
210			NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
211			`end`
212			`DATA0_DATA1_READ_FIFO:
213			`begin`
214			`next_HCTxPortWEn <= 1'b1;`
215			`next_HCTxPortData <= fifoData;`
216			next_HCTxPortCntl <= `TX_PACKET_STREAM;
217			NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
218			`end`
219			`DATA0_DATA1_WAIT_READ_FIFO:
220			`if (HCTxPortRdy == 1'b1)`
221			`begin`
222			NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
223			`next_fifoReadEn <= 1'b1;`
224			`end`
225			`DATA0_DATA1_FIFO_EMPTY:
226			`if (fifoEmpty == 1'b0)`
227			NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
228			`else`
229			NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
230			`DATA0_DATA1_FIN:
231			`begin`
232			`next_HCTxPortWEn <= 1'b0;`
233			NextState_sndPkt <= `FIN_SP;
234			`end`
235			`DATA0_DATA1_TERM_BYTE:
236			`if (HCTxPortRdy == 1'b1)`
237			`begin`
238			NextState_sndPkt <= `DATA0_DATA1_FIN;
239			`//Last byte is not valid data,`
240			`//but the 'TX_PACKET_STOP' flag is required`
241			`//by the SIE state machine to detect end of data packet`
242			`next_HCTxPortWEn <= 1'b1;`
243			`next_HCTxPortData <= 8'h00;`
244			next_HCTxPortCntl <= `TX_PACKET_STOP;
245			`end`
246			`DATA0_DATA1_CLR_WEN:
247			`begin`
248			`next_HCTxPortWEn <= 1'b0;`
249			NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
250			`end`
251			`DATA0_DATA1_CLR_REN:
252			`begin`
253			`next_fifoReadEn <= 1'b0;`
254			NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
255			`end`
256			`endcase`
257			`end`
258
259			`//----------------------------------`
260			`// Current State Logic (sequential)`
261			`//----------------------------------`
262			`always @ (posedge clk)`
263			`begin : sndPkt_CurrentState`
264			`if (rst)`
265			CurrState_sndPkt <= `START_SP;
266			`else`
267			`CurrState_sndPkt <= NextState_sndPkt;`
268			`end`
269
270			`//----------------------------------`
271			`// Registered outputs logic`
272			`//----------------------------------`
273			`always @ (posedge clk)`
274			`begin : sndPkt_RegOutput`
275			`if (rst)`
276			`begin`
277			`sendPacketRdy <= 1'b1;`
278			`HCTxPortReq <= 1'b0;`
279			`HCTxPortWEn <= 1'b0;`
280			`HCTxPortData <= 8'h00;`
281			`HCTxPortCntl <= 8'h00;`
282			`frameNum <= 11'h000;`
283			`fifoReadEn <= 1'b0;`
284			`end`
285			`else`
286			`begin`
287			`sendPacketRdy <= next_sendPacketRdy;`
288			`HCTxPortReq <= next_HCTxPortReq;`
289			`HCTxPortWEn <= next_HCTxPortWEn;`
290			`HCTxPortData <= next_HCTxPortData;`
291			`HCTxPortCntl <= next_HCTxPortCntl;`
292			`frameNum <= next_frameNum;`
293			`fifoReadEn <= next_fifoReadEn;`
294			`end`
295			`end`
296
297			`endmodule`