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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacketcheckpreamble.v] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// sendpacketcheckpreamble
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbConstants_h.v"
 
module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
input   clk;
input   preAmbleEnable;
input   rst;
input   [3:0]sendPacketCPPID;
input   sendPacketCPWEn;
input   sendPacketRdy;
output  sendPacketCPReady;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
 
wire    clk;
wire    preAmbleEnable;
wire    rst;
wire    [3:0]sendPacketCPPID;
reg     sendPacketCPReady, next_sendPacketCPReady;
wire    sendPacketCPWEn;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
 
// BINARY ENCODED state machine: sendPktCP
// State codes definitions:
`define SPC_WAIT_EN 4'b0000
`define START_SPC 4'b0001
`define CHK_PREAM 4'b0010
`define PREAM_PKT_SND_PREAM 4'b0011
`define PREAM_PKT_WAIT_RDY1 4'b0100
`define PREAM_PKT_PREAM_SENT 4'b0101
`define PREAM_PKT_SND_PID 4'b0110
`define PREAM_PKT_PID_SENT 4'b0111
`define REG_PKT_SEND_PID 4'b1000
`define REG_PKT_WAIT_RDY1 4'b1001
`define REG_PKT_WAIT_RDY 4'b1010
`define READY 4'b1011
`define PREAM_PKT_WAIT_RDY2 4'b1100
`define PREAM_PKT_WAIT_RDY3 4'b1101
 
reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
 
 
// Machine: sendPktCP
 
// NextState logic (combinatorial)
always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
begin
  NextState_sendPktCP <= CurrState_sendPktCP;
  // Set default values for outputs and signals
  next_sendPacketCPReady <= sendPacketCPReady;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketPID <= sendPacketPID;
  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
    `SPC_WAIT_EN:
    begin
      if (sendPacketCPWEn == 1'b1)
      begin
        NextState_sendPktCP <= `CHK_PREAM;
        next_sendPacketCPReady <= 1'b0;
      end
    end
    `START_SPC:
    begin
      NextState_sendPktCP <= `SPC_WAIT_EN;
    end
    `CHK_PREAM:
    begin
      if (preAmbleEnable == 1'b1)
      begin
        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
      end
      else
      begin
        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
      end
    end
    `READY:
    begin
      next_sendPacketCPReady <= 1'b1;
      NextState_sendPktCP <= `SPC_WAIT_EN;
    end
    `PREAM_PKT_SND_PREAM:
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketPID <= `PREAMBLE;
      NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
    end
    `PREAM_PKT_WAIT_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
      end
    end
    `PREAM_PKT_PREAM_SENT:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
    end
    `PREAM_PKT_SND_PID:
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketPID <= sendPacketCPPID;
      NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
    end
    `PREAM_PKT_PID_SENT:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
    end
    `PREAM_PKT_WAIT_RDY2:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
      end
    end
    `PREAM_PKT_WAIT_RDY3:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_sendPktCP <= `READY;
      end
    end
    `REG_PKT_SEND_PID:
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketPID <= sendPacketCPPID;
      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
    end
    `REG_PKT_WAIT_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_sendPktCP <= `REG_PKT_SEND_PID;
      end
    end
    `REG_PKT_WAIT_RDY:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_sendPktCP <= `READY;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_sendPktCP <= `START_SPC;
  else
    CurrState_sendPktCP <= NextState_sendPktCP;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    sendPacketCPReady <= 1'b1;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
  end
  else
  begin
    sendPacketCPReady <= next_sendPacketCPReady;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// sendpacketcheckpreamble`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbConstants_h.v"
47
48	14	sfielding	`module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);`
49	5	sfielding	`input clk;`
50			`input preAmbleEnable;`
51			`input rst;`
52			`input [3:0]sendPacketCPPID;`
53			`input sendPacketCPWEn;`
54			`input sendPacketRdy;`
55			`output sendPacketCPReady;`
56			`output [3:0]sendPacketPID;`
57			`output sendPacketWEn;`
58
59			`wire clk;`
60			`wire preAmbleEnable;`
61			`wire rst;`
62			`wire [3:0]sendPacketCPPID;`
63			`reg sendPacketCPReady, next_sendPacketCPReady;`
64			`wire sendPacketCPWEn;`
65			`reg [3:0]sendPacketPID, next_sendPacketPID;`
66			`wire sendPacketRdy;`
67			`reg sendPacketWEn, next_sendPacketWEn;`
68
69			`// BINARY ENCODED state machine: sendPktCP`
70			`// State codes definitions:`
71			`define SPC_WAIT_EN 4'b0000
72			`define START_SPC 4'b0001
73			`define CHK_PREAM 4'b0010
74			`define PREAM_PKT_SND_PREAM 4'b0011
75			`define PREAM_PKT_WAIT_RDY1 4'b0100
76	14	sfielding	`define PREAM_PKT_PREAM_SENT 4'b0101
77	5	sfielding	`define PREAM_PKT_SND_PID 4'b0110
78	14	sfielding	`define PREAM_PKT_PID_SENT 4'b0111
79	5	sfielding	`define REG_PKT_SEND_PID 4'b1000
80			`define REG_PKT_WAIT_RDY1 4'b1001
81			`define REG_PKT_WAIT_RDY 4'b1010
82			`define READY 4'b1011
83	14	sfielding	`define PREAM_PKT_WAIT_RDY2 4'b1100
84			`define PREAM_PKT_WAIT_RDY3 4'b1101
85	5	sfielding
86			`reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;`
87
88
89			`// Machine: sendPktCP`
90
91			`// NextState logic (combinatorial)`
92	14	sfielding	`always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)`
93	5	sfielding	`begin`
94			`NextState_sendPktCP <= CurrState_sendPktCP;`
95			`// Set default values for outputs and signals`
96			`next_sendPacketCPReady <= sendPacketCPReady;`
97			`next_sendPacketWEn <= sendPacketWEn;`
98			`next_sendPacketPID <= sendPacketPID;`
99			`case (CurrState_sendPktCP) // synopsys parallel_case full_case`
100			`SPC_WAIT_EN:
101			`begin`
102			`if (sendPacketCPWEn == 1'b1)`
103			`begin`
104			NextState_sendPktCP <= `CHK_PREAM;
105			`next_sendPacketCPReady <= 1'b0;`
106			`end`
107			`end`
108			`START_SPC:
109			`begin`
110			NextState_sendPktCP <= `SPC_WAIT_EN;
111			`end`
112			`CHK_PREAM:
113			`begin`
114			`if (preAmbleEnable == 1'b1)`
115			`begin`
116			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
117			`end`
118			`else`
119			`begin`
120			NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
121			`end`
122			`end`
123			`READY:
124			`begin`
125			`next_sendPacketCPReady <= 1'b1;`
126			NextState_sendPktCP <= `SPC_WAIT_EN;
127			`end`
128			`PREAM_PKT_SND_PREAM:
129			`begin`
130			`next_sendPacketWEn <= 1'b1;`
131			next_sendPacketPID <= `PREAMBLE;
132	14	sfielding	NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
133	5	sfielding	`end`
134			`PREAM_PKT_WAIT_RDY1:
135			`begin`
136			`if (sendPacketRdy == 1'b1)`
137			`begin`
138			NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
139			`end`
140			`end`
141	14	sfielding	`PREAM_PKT_PREAM_SENT:
142	5	sfielding	`begin`
143	14	sfielding	`next_sendPacketWEn <= 1'b0;`
144			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
145	5	sfielding	`end`
146			`PREAM_PKT_SND_PID:
147			`begin`
148			`next_sendPacketWEn <= 1'b1;`
149			`next_sendPacketPID <= sendPacketCPPID;`
150	14	sfielding	NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
151			`end`
152			`PREAM_PKT_PID_SENT:
153			`begin`
154			`next_sendPacketWEn <= 1'b0;`
155	5	sfielding	NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
156			`end`
157	14	sfielding	`PREAM_PKT_WAIT_RDY2:
158			`begin`
159			`if (sendPacketRdy == 1'b1)`
160			`begin`
161			NextState_sendPktCP <= `PREAM_PKT_SND_PID;
162			`end`
163			`end`
164	5	sfielding	`PREAM_PKT_WAIT_RDY3:
165			`begin`
166			`if (sendPacketRdy == 1'b1)`
167			`begin`
168			NextState_sendPktCP <= `READY;
169			`end`
170			`end`
171			`REG_PKT_SEND_PID:
172			`begin`
173			`next_sendPacketWEn <= 1'b1;`
174			`next_sendPacketPID <= sendPacketCPPID;`
175			NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
176			`end`
177			`REG_PKT_WAIT_RDY1:
178			`begin`
179			`if (sendPacketRdy == 1'b1)`
180			`begin`
181			NextState_sendPktCP <= `REG_PKT_SEND_PID;
182			`end`
183			`end`
184			`REG_PKT_WAIT_RDY:
185			`begin`
186			`next_sendPacketWEn <= 1'b0;`
187			NextState_sendPktCP <= `READY;
188			`end`
189			`endcase`
190			`end`
191
192			`// Current State Logic (sequential)`
193			`always @ (posedge clk)`
194			`begin`
195			`if (rst)`
196			CurrState_sendPktCP <= `START_SPC;
197			`else`
198			`CurrState_sendPktCP <= NextState_sendPktCP;`
199			`end`
200
201			`// Registered outputs logic`
202			`always @ (posedge clk)`
203			`begin`
204			`if (rst)`
205			`begin`
206			`sendPacketCPReady <= 1'b1;`
207			`sendPacketWEn <= 1'b0;`
208			`sendPacketPID <= 4'b0;`
209			`end`
210			`else`
211			`begin`
212			`sendPacketCPReady <= next_sendPacketCPReady;`
213			`sendPacketWEn <= next_sendPacketWEn;`
214			`sendPacketPID <= next_sendPacketPID;`
215			`end`
216			`end`
217
218	2	sfielding	`endmodule`

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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacketcheckpreamble.v] - Blame information for rev 14