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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacketcheckpreamble.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : 
// Company     : 
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketcheckpreamble.v
// Generated   : 09/10/04 20:20:24
// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacketcheckpreamble.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbConstants_h.v"
 
module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
input   clk;
input   preAmbleEnable;
input   rst;
input   [3:0] sendPacketCPPID;
input   sendPacketCPWEn;
input   sendPacketRdy;
output  fullSpeedBitRate;
output  fullSpeedPolarity;
output  grabLineControl;                // mux select
output  sendPacketCPReady;
output  [3:0] sendPacketPID;
output  sendPacketWEn;
 
wire    clk;
reg     fullSpeedBitRate, next_fullSpeedBitRate;
reg     fullSpeedPolarity, next_fullSpeedPolarity;
reg     grabLineControl, next_grabLineControl;
wire    preAmbleEnable;
wire    rst;
wire    [3:0] sendPacketCPPID;
reg     sendPacketCPReady, next_sendPacketCPReady;
wire    sendPacketCPWEn;
reg     [3:0] sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
 
// BINARY ENCODED state machine: sendPktCP
// State codes definitions:
`define SPC_WAIT_EN 4'b0000
`define START_SPC 4'b0001
`define CHK_PREAM 4'b0010
`define PREAM_PKT_SND_PREAM 4'b0011
`define PREAM_PKT_WAIT_RDY1 4'b0100
`define PREAM_PKT_WAIT_RDY2 4'b0101
`define PREAM_PKT_SND_PID 4'b0110
`define PREAM_PKT_WAIT_RDY3 4'b0111
`define REG_PKT_SEND_PID 4'b1000
`define REG_PKT_WAIT_RDY1 4'b1001
`define REG_PKT_WAIT_RDY 4'b1010
`define READY 4'b1011
 
reg [3:0] CurrState_sendPktCP;
reg [3:0] NextState_sendPktCP;
 
 
//--------------------------------------------------------------------
// Machine: sendPktCP
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
begin : sendPktCP_NextState
        NextState_sendPktCP <= CurrState_sendPktCP;
        // Set default values for outputs and signals
        next_sendPacketCPReady <= sendPacketCPReady;
        next_sendPacketWEn <= sendPacketWEn;
        next_sendPacketPID <= sendPacketPID;
        next_fullSpeedBitRate <= fullSpeedBitRate;
        next_fullSpeedPolarity <= fullSpeedPolarity;
        next_grabLineControl <= grabLineControl;
        case (CurrState_sendPktCP) // synopsys parallel_case full_case
                `SPC_WAIT_EN:
                        if (sendPacketCPWEn == 1'b1)
                        begin
                                NextState_sendPktCP <= `CHK_PREAM;
                                next_sendPacketCPReady <= 1'b0;
                        end
                `START_SPC:
                        NextState_sendPktCP <= `SPC_WAIT_EN;
                `CHK_PREAM:
                        if (preAmbleEnable == 1'b1)
                                NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
                        else
                                NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
                `READY:
                begin
                        next_sendPacketCPReady <= 1'b1;
                        NextState_sendPktCP <= `SPC_WAIT_EN;
                end
                `PREAM_PKT_SND_PREAM:
                begin
                        next_sendPacketWEn <= 1'b1;
                        next_sendPacketPID <= `PREAMBLE;
                        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
                        next_sendPacketWEn <= 1'b0;
                end
                `PREAM_PKT_WAIT_RDY1:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
                                next_fullSpeedBitRate <= 1'b1;
                                next_fullSpeedPolarity <= 1'b1;
                                next_grabLineControl <= 1'b1;
                        end
                `PREAM_PKT_WAIT_RDY2:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_sendPktCP <= `PREAM_PKT_SND_PID;
                                next_fullSpeedBitRate <= 1'b1;
                        end
                `PREAM_PKT_SND_PID:
                begin
                        next_sendPacketWEn <= 1'b1;
                        next_sendPacketPID <= sendPacketCPPID;
                        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
                        next_sendPacketWEn <= 1'b0;
                end
                `PREAM_PKT_WAIT_RDY3:
                        if (sendPacketRdy == 1'b1)
                        begin
                                NextState_sendPktCP <= `READY;
                                next_grabLineControl <= 1'b0;
                        end
                `REG_PKT_SEND_PID:
                begin
                        next_sendPacketWEn <= 1'b1;
                        next_sendPacketPID <= sendPacketCPPID;
                        NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
                end
                `REG_PKT_WAIT_RDY1:
                        if (sendPacketRdy == 1'b1)
                                NextState_sendPktCP <= `REG_PKT_SEND_PID;
                `REG_PKT_WAIT_RDY:
                begin
                        next_sendPacketWEn <= 1'b0;
                        NextState_sendPktCP <= `READY;
                end
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sendPktCP_CurrentState
        if (rst)
                CurrState_sendPktCP <= `START_SPC;
        else
                CurrState_sendPktCP <= NextState_sendPktCP;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sendPktCP_RegOutput
        if (rst)
        begin
                sendPacketWEn <= 1'b0;
                sendPacketPID <= 4'b0;
                fullSpeedBitRate <= 1'b0;
                fullSpeedPolarity <= 1'b0;
                grabLineControl <= 1'b0;
                sendPacketCPReady <= 1'b1;
        end
        else
        begin
                sendPacketWEn <= next_sendPacketWEn;
                sendPacketPID <= next_sendPacketPID;
                fullSpeedBitRate <= next_fullSpeedBitRate;
                fullSpeedPolarity <= next_fullSpeedPolarity;
                grabLineControl <= next_grabLineControl;
                sendPacketCPReady <= next_sendPacketCPReady;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author :`
6			`// Company :`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketcheckpreamble.v`
11			`// Generated : 09/10/04 20:20:24`
12			`// From : c:\projects\USBHostSlave\RTL\hostController\sendpacketcheckpreamble.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbConstants_h.v"
23
24			`module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);`
25			`input clk;`
26			`input preAmbleEnable;`
27			`input rst;`
28			`input [3:0] sendPacketCPPID;`
29			`input sendPacketCPWEn;`
30			`input sendPacketRdy;`
31			`output fullSpeedBitRate;`
32			`output fullSpeedPolarity;`
33			`output grabLineControl; // mux select`
34			`output sendPacketCPReady;`
35			`output [3:0] sendPacketPID;`
36			`output sendPacketWEn;`
37
38			`wire clk;`
39			`reg fullSpeedBitRate, next_fullSpeedBitRate;`
40			`reg fullSpeedPolarity, next_fullSpeedPolarity;`
41			`reg grabLineControl, next_grabLineControl;`
42			`wire preAmbleEnable;`
43			`wire rst;`
44			`wire [3:0] sendPacketCPPID;`
45			`reg sendPacketCPReady, next_sendPacketCPReady;`
46			`wire sendPacketCPWEn;`
47			`reg [3:0] sendPacketPID, next_sendPacketPID;`
48			`wire sendPacketRdy;`
49			`reg sendPacketWEn, next_sendPacketWEn;`
50
51			`// BINARY ENCODED state machine: sendPktCP`
52			`// State codes definitions:`
53			`define SPC_WAIT_EN 4'b0000
54			`define START_SPC 4'b0001
55			`define CHK_PREAM 4'b0010
56			`define PREAM_PKT_SND_PREAM 4'b0011
57			`define PREAM_PKT_WAIT_RDY1 4'b0100
58			`define PREAM_PKT_WAIT_RDY2 4'b0101
59			`define PREAM_PKT_SND_PID 4'b0110
60			`define PREAM_PKT_WAIT_RDY3 4'b0111
61			`define REG_PKT_SEND_PID 4'b1000
62			`define REG_PKT_WAIT_RDY1 4'b1001
63			`define REG_PKT_WAIT_RDY 4'b1010
64			`define READY 4'b1011
65
66			`reg [3:0] CurrState_sendPktCP;`
67			`reg [3:0] NextState_sendPktCP;`
68
69
70			`//--------------------------------------------------------------------`
71			`// Machine: sendPktCP`
72			`//--------------------------------------------------------------------`
73			`//----------------------------------`
74			`// NextState logic (combinatorial)`
75			`//----------------------------------`
76			`always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)`
77			`begin : sendPktCP_NextState`
78			`NextState_sendPktCP <= CurrState_sendPktCP;`
79			`// Set default values for outputs and signals`
80			`next_sendPacketCPReady <= sendPacketCPReady;`
81			`next_sendPacketWEn <= sendPacketWEn;`
82			`next_sendPacketPID <= sendPacketPID;`
83			`next_fullSpeedBitRate <= fullSpeedBitRate;`
84			`next_fullSpeedPolarity <= fullSpeedPolarity;`
85			`next_grabLineControl <= grabLineControl;`
86			`case (CurrState_sendPktCP) // synopsys parallel_case full_case`
87			`SPC_WAIT_EN:
88			`if (sendPacketCPWEn == 1'b1)`
89			`begin`
90			NextState_sendPktCP <= `CHK_PREAM;
91			`next_sendPacketCPReady <= 1'b0;`
92			`end`
93			`START_SPC:
94			NextState_sendPktCP <= `SPC_WAIT_EN;
95			`CHK_PREAM:
96			`if (preAmbleEnable == 1'b1)`
97			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
98			`else`
99			NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
100			`READY:
101			`begin`
102			`next_sendPacketCPReady <= 1'b1;`
103			NextState_sendPktCP <= `SPC_WAIT_EN;
104			`end`
105			`PREAM_PKT_SND_PREAM:
106			`begin`
107			`next_sendPacketWEn <= 1'b1;`
108			next_sendPacketPID <= `PREAMBLE;
109			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
110			`next_sendPacketWEn <= 1'b0;`
111			`end`
112			`PREAM_PKT_WAIT_RDY1:
113			`if (sendPacketRdy == 1'b1)`
114			`begin`
115			NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
116			`next_fullSpeedBitRate <= 1'b1;`
117			`next_fullSpeedPolarity <= 1'b1;`
118			`next_grabLineControl <= 1'b1;`
119			`end`
120			`PREAM_PKT_WAIT_RDY2:
121			`if (sendPacketRdy == 1'b1)`
122			`begin`
123			NextState_sendPktCP <= `PREAM_PKT_SND_PID;
124			`next_fullSpeedBitRate <= 1'b1;`
125			`end`
126			`PREAM_PKT_SND_PID:
127			`begin`
128			`next_sendPacketWEn <= 1'b1;`
129			`next_sendPacketPID <= sendPacketCPPID;`
130			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
131			`next_sendPacketWEn <= 1'b0;`
132			`end`
133			`PREAM_PKT_WAIT_RDY3:
134			`if (sendPacketRdy == 1'b1)`
135			`begin`
136			NextState_sendPktCP <= `READY;
137			`next_grabLineControl <= 1'b0;`
138			`end`
139			`REG_PKT_SEND_PID:
140			`begin`
141			`next_sendPacketWEn <= 1'b1;`
142			`next_sendPacketPID <= sendPacketCPPID;`
143			NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
144			`end`
145			`REG_PKT_WAIT_RDY1:
146			`if (sendPacketRdy == 1'b1)`
147			NextState_sendPktCP <= `REG_PKT_SEND_PID;
148			`REG_PKT_WAIT_RDY:
149			`begin`
150			`next_sendPacketWEn <= 1'b0;`
151			NextState_sendPktCP <= `READY;
152			`end`
153			`endcase`
154			`end`
155
156			`//----------------------------------`
157			`// Current State Logic (sequential)`
158			`//----------------------------------`
159			`always @ (posedge clk)`
160			`begin : sendPktCP_CurrentState`
161			`if (rst)`
162			CurrState_sendPktCP <= `START_SPC;
163			`else`
164			`CurrState_sendPktCP <= NextState_sendPktCP;`
165			`end`
166
167			`//----------------------------------`
168			`// Registered outputs logic`
169			`//----------------------------------`
170			`always @ (posedge clk)`
171			`begin : sendPktCP_RegOutput`
172			`if (rst)`
173			`begin`
174			`sendPacketWEn <= 1'b0;`
175			`sendPacketPID <= 4'b0;`
176			`fullSpeedBitRate <= 1'b0;`
177			`fullSpeedPolarity <= 1'b0;`
178			`grabLineControl <= 1'b0;`
179			`sendPacketCPReady <= 1'b1;`
180			`end`
181			`else`
182			`begin`
183			`sendPacketWEn <= next_sendPacketWEn;`
184			`sendPacketPID <= next_sendPacketPID;`
185			`fullSpeedBitRate <= next_fullSpeedBitRate;`
186			`fullSpeedPolarity <= next_fullSpeedPolarity;`
187			`grabLineControl <= next_grabLineControl;`
188			`sendPacketCPReady <= next_sendPacketCPReady;`
189			`end`
190			`end`
191
192			`endmodule`

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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacketcheckpreamble.v] - Blame information for rev 2