URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacketcheckpreamble.v] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log


 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// sendpacketcheckpreamble
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: sendpacketcheckpreamble.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`timescale 1ns / 1ps
`include "usbConstants_h.v"
 
module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
input   clk;
input   preAmbleEnable;
input   rst;
input   [3:0]sendPacketCPPID;
input   sendPacketCPWEn;
input   sendPacketRdy;
output  fullSpeedBitRate;
output  fullSpeedPolarity;
output  grabLineControl;    // mux select
output  sendPacketCPReady;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
 
wire    clk;
reg     fullSpeedBitRate, next_fullSpeedBitRate;
reg     fullSpeedPolarity, next_fullSpeedPolarity;
reg     grabLineControl, next_grabLineControl;
wire    preAmbleEnable;
wire    rst;
wire    [3:0]sendPacketCPPID;
reg     sendPacketCPReady, next_sendPacketCPReady;
wire    sendPacketCPWEn;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
 
// BINARY ENCODED state machine: sendPktCP
// State codes definitions:
`define SPC_WAIT_EN 4'b0000
`define START_SPC 4'b0001
`define CHK_PREAM 4'b0010
`define PREAM_PKT_SND_PREAM 4'b0011
`define PREAM_PKT_WAIT_RDY1 4'b0100
`define PREAM_PKT_WAIT_RDY2 4'b0101
`define PREAM_PKT_SND_PID 4'b0110
`define PREAM_PKT_WAIT_RDY3 4'b0111
`define REG_PKT_SEND_PID 4'b1000
`define REG_PKT_WAIT_RDY1 4'b1001
`define REG_PKT_WAIT_RDY 4'b1010
`define READY 4'b1011
 
reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
 
 
// Machine: sendPktCP
 
// NextState logic (combinatorial)
always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
begin
  NextState_sendPktCP <= CurrState_sendPktCP;
  // Set default values for outputs and signals
  next_sendPacketCPReady <= sendPacketCPReady;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketPID <= sendPacketPID;
  next_fullSpeedBitRate <= fullSpeedBitRate;
  next_fullSpeedPolarity <= fullSpeedPolarity;
  next_grabLineControl <= grabLineControl;
  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
    `SPC_WAIT_EN:
    begin
      if (sendPacketCPWEn == 1'b1)
      begin
        NextState_sendPktCP <= `CHK_PREAM;
        next_sendPacketCPReady <= 1'b0;
      end
    end
    `START_SPC:
    begin
      NextState_sendPktCP <= `SPC_WAIT_EN;
    end
    `CHK_PREAM:
    begin
      if (preAmbleEnable == 1'b1)
      begin
        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
      end
      else
      begin
        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
      end
    end
    `READY:
    begin
      next_sendPacketCPReady <= 1'b1;
      NextState_sendPktCP <= `SPC_WAIT_EN;
    end
    `PREAM_PKT_SND_PREAM:
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketPID <= `PREAMBLE;
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
      next_sendPacketWEn <= 1'b0;
    end
    `PREAM_PKT_WAIT_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
        next_fullSpeedBitRate <= 1'b1;
        next_fullSpeedPolarity <= 1'b1;
        next_grabLineControl <= 1'b1;
      end
    end
    `PREAM_PKT_WAIT_RDY2:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
        next_fullSpeedBitRate <= 1'b1;
      end
    end
    `PREAM_PKT_SND_PID:
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketPID <= sendPacketCPPID;
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
      next_sendPacketWEn <= 1'b0;
    end
    `PREAM_PKT_WAIT_RDY3:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_sendPktCP <= `READY;
        next_grabLineControl <= 1'b0;
      end
    end
    `REG_PKT_SEND_PID:
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketPID <= sendPacketCPPID;
      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
    end
    `REG_PKT_WAIT_RDY1:
    begin
      if (sendPacketRdy == 1'b1)
      begin
        NextState_sendPktCP <= `REG_PKT_SEND_PID;
      end
    end
    `REG_PKT_WAIT_RDY:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_sendPktCP <= `READY;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_sendPktCP <= `START_SPC;
  else
    CurrState_sendPktCP <= NextState_sendPktCP;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    sendPacketCPReady <= 1'b1;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
    fullSpeedBitRate <= 1'b0;
    fullSpeedPolarity <= 1'b0;
    grabLineControl <= 1'b0;
  end
  else
  begin
    sendPacketCPReady <= next_sendPacketCPReady;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
    fullSpeedBitRate <= next_fullSpeedBitRate;
    fullSpeedPolarity <= next_fullSpeedPolarity;
    grabLineControl <= next_grabLineControl;
  end
end
 
endmodule

Browse

Tools

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacketcheckpreamble.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// sendpacketcheckpreamble`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	7	sfielding	`// $Id: sendpacketcheckpreamble.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $`
46	5	sfielding	`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`timescale 1ns / 1ps
52			`include "usbConstants_h.v"
53
54			`module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);`
55			`input clk;`
56			`input preAmbleEnable;`
57			`input rst;`
58			`input [3:0]sendPacketCPPID;`
59			`input sendPacketCPWEn;`
60			`input sendPacketRdy;`
61			`output fullSpeedBitRate;`
62			`output fullSpeedPolarity;`
63			`output grabLineControl; // mux select`
64			`output sendPacketCPReady;`
65			`output [3:0]sendPacketPID;`
66			`output sendPacketWEn;`
67
68			`wire clk;`
69			`reg fullSpeedBitRate, next_fullSpeedBitRate;`
70			`reg fullSpeedPolarity, next_fullSpeedPolarity;`
71			`reg grabLineControl, next_grabLineControl;`
72			`wire preAmbleEnable;`
73			`wire rst;`
74			`wire [3:0]sendPacketCPPID;`
75			`reg sendPacketCPReady, next_sendPacketCPReady;`
76			`wire sendPacketCPWEn;`
77			`reg [3:0]sendPacketPID, next_sendPacketPID;`
78			`wire sendPacketRdy;`
79			`reg sendPacketWEn, next_sendPacketWEn;`
80
81			`// BINARY ENCODED state machine: sendPktCP`
82			`// State codes definitions:`
83			`define SPC_WAIT_EN 4'b0000
84			`define START_SPC 4'b0001
85			`define CHK_PREAM 4'b0010
86			`define PREAM_PKT_SND_PREAM 4'b0011
87			`define PREAM_PKT_WAIT_RDY1 4'b0100
88			`define PREAM_PKT_WAIT_RDY2 4'b0101
89			`define PREAM_PKT_SND_PID 4'b0110
90			`define PREAM_PKT_WAIT_RDY3 4'b0111
91			`define REG_PKT_SEND_PID 4'b1000
92			`define REG_PKT_WAIT_RDY1 4'b1001
93			`define REG_PKT_WAIT_RDY 4'b1010
94			`define READY 4'b1011
95
96			`reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;`
97
98
99			`// Machine: sendPktCP`
100
101			`// NextState logic (combinatorial)`
102			`always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)`
103			`begin`
104			`NextState_sendPktCP <= CurrState_sendPktCP;`
105			`// Set default values for outputs and signals`
106			`next_sendPacketCPReady <= sendPacketCPReady;`
107			`next_sendPacketWEn <= sendPacketWEn;`
108			`next_sendPacketPID <= sendPacketPID;`
109			`next_fullSpeedBitRate <= fullSpeedBitRate;`
110			`next_fullSpeedPolarity <= fullSpeedPolarity;`
111			`next_grabLineControl <= grabLineControl;`
112			`case (CurrState_sendPktCP) // synopsys parallel_case full_case`
113			`SPC_WAIT_EN:
114			`begin`
115			`if (sendPacketCPWEn == 1'b1)`
116			`begin`
117			NextState_sendPktCP <= `CHK_PREAM;
118			`next_sendPacketCPReady <= 1'b0;`
119			`end`
120			`end`
121			`START_SPC:
122			`begin`
123			NextState_sendPktCP <= `SPC_WAIT_EN;
124			`end`
125			`CHK_PREAM:
126			`begin`
127			`if (preAmbleEnable == 1'b1)`
128			`begin`
129			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
130			`end`
131			`else`
132			`begin`
133			NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
134			`end`
135			`end`
136			`READY:
137			`begin`
138			`next_sendPacketCPReady <= 1'b1;`
139			NextState_sendPktCP <= `SPC_WAIT_EN;
140			`end`
141			`PREAM_PKT_SND_PREAM:
142			`begin`
143			`next_sendPacketWEn <= 1'b1;`
144			next_sendPacketPID <= `PREAMBLE;
145			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
146			`next_sendPacketWEn <= 1'b0;`
147			`end`
148			`PREAM_PKT_WAIT_RDY1:
149			`begin`
150			`if (sendPacketRdy == 1'b1)`
151			`begin`
152			NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
153			`next_fullSpeedBitRate <= 1'b1;`
154			`next_fullSpeedPolarity <= 1'b1;`
155			`next_grabLineControl <= 1'b1;`
156			`end`
157			`end`
158			`PREAM_PKT_WAIT_RDY2:
159			`begin`
160			`if (sendPacketRdy == 1'b1)`
161			`begin`
162			NextState_sendPktCP <= `PREAM_PKT_SND_PID;
163			`next_fullSpeedBitRate <= 1'b1;`
164			`end`
165			`end`
166			`PREAM_PKT_SND_PID:
167			`begin`
168			`next_sendPacketWEn <= 1'b1;`
169			`next_sendPacketPID <= sendPacketCPPID;`
170			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
171			`next_sendPacketWEn <= 1'b0;`
172			`end`
173			`PREAM_PKT_WAIT_RDY3:
174			`begin`
175			`if (sendPacketRdy == 1'b1)`
176			`begin`
177			NextState_sendPktCP <= `READY;
178			`next_grabLineControl <= 1'b0;`
179			`end`
180			`end`
181			`REG_PKT_SEND_PID:
182			`begin`
183			`next_sendPacketWEn <= 1'b1;`
184			`next_sendPacketPID <= sendPacketCPPID;`
185			NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
186			`end`
187			`REG_PKT_WAIT_RDY1:
188			`begin`
189			`if (sendPacketRdy == 1'b1)`
190			`begin`
191			NextState_sendPktCP <= `REG_PKT_SEND_PID;
192			`end`
193			`end`
194			`REG_PKT_WAIT_RDY:
195			`begin`
196			`next_sendPacketWEn <= 1'b0;`
197			NextState_sendPktCP <= `READY;
198			`end`
199			`endcase`
200			`end`
201
202			`// Current State Logic (sequential)`
203			`always @ (posedge clk)`
204			`begin`
205			`if (rst)`
206			CurrState_sendPktCP <= `START_SPC;
207			`else`
208			`CurrState_sendPktCP <= NextState_sendPktCP;`
209			`end`
210
211			`// Registered outputs logic`
212			`always @ (posedge clk)`
213			`begin`
214			`if (rst)`
215			`begin`
216			`sendPacketCPReady <= 1'b1;`
217			`sendPacketWEn <= 1'b0;`
218			`sendPacketPID <= 4'b0;`
219			`fullSpeedBitRate <= 1'b0;`
220			`fullSpeedPolarity <= 1'b0;`
221			`grabLineControl <= 1'b0;`
222			`end`
223			`else`
224			`begin`
225			`sendPacketCPReady <= next_sendPacketCPReady;`
226			`sendPacketWEn <= next_sendPacketWEn;`
227			`sendPacketPID <= next_sendPacketPID;`
228			`fullSpeedBitRate <= next_fullSpeedBitRate;`
229			`fullSpeedPolarity <= next_fullSpeedPolarity;`
230			`grabLineControl <= next_grabLineControl;`
231			`end`
232			`end`
233
234	2	sfielding	`endmodule`