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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sofcontroller.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : Steve
// Company     : Base2Designs
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sofcontroller.v
// Generated   : 09/08/04 06:24:36
// From        : c:\projects\USBHostSlave\RTL\hostController\sofcontroller.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
module SOFController (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, SOFEnable, SOFTimerClr, SOFTimer, clk, rst);
input   HCTxPortGnt;
input   HCTxPortRdy;
input   SOFEnable;
input   SOFTimerClr;
input   clk;
input   rst;
output  [7:0] HCTxPortCntl;
output  [7:0] HCTxPortData;
output  HCTxPortReq;
output  HCTxPortWEn;
output  [15:0] SOFTimer;
 
reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
reg     [7:0] HCTxPortData, next_HCTxPortData;
wire    HCTxPortGnt;
wire    HCTxPortRdy;
reg     HCTxPortReq, next_HCTxPortReq;
reg     HCTxPortWEn, next_HCTxPortWEn;
wire    SOFEnable;
wire    SOFTimerClr;
reg     [15:0] SOFTimer, next_SOFTimer;
wire    clk;
wire    rst;
 
// BINARY ENCODED state machine: sofCntl
// State codes definitions:
`define START_SC 3'b000
`define WAIT_SOF_EN 3'b001
`define WAIT_SEND_RESUME 3'b010
`define INC_TIMER 3'b011
`define SC_WAIT_GNT 3'b100
`define CLR_WEN 3'b101
 
reg [2:0] CurrState_sofCntl;
reg [2:0] NextState_sofCntl;
 
 
//--------------------------------------------------------------------
// Machine: sofCntl
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)
begin : sofCntl_NextState
        NextState_sofCntl <= CurrState_sofCntl;
        // Set default values for outputs and signals
        next_HCTxPortReq <= HCTxPortReq;
        next_HCTxPortWEn <= HCTxPortWEn;
        next_HCTxPortData <= HCTxPortData;
        next_HCTxPortCntl <= HCTxPortCntl;
        next_SOFTimer <= SOFTimer;
        case (CurrState_sofCntl) // synopsys parallel_case full_case
                `START_SC:
                        NextState_sofCntl <= `WAIT_SOF_EN;
                `WAIT_SOF_EN:
                        if (SOFEnable == 1'b1)
                        begin
                                NextState_sofCntl <= `SC_WAIT_GNT;
                                next_HCTxPortReq <= 1'b1;
                        end
                `WAIT_SEND_RESUME:
                        if (HCTxPortRdy == 1'b1)
                        begin
                                NextState_sofCntl <= `CLR_WEN;
                                next_HCTxPortWEn <= 1'b1;
                                next_HCTxPortData <= 8'h00;
                                next_HCTxPortCntl <= `TX_RESUME_START;
                        end
                `INC_TIMER:
                begin
                        next_HCTxPortReq <= 1'b0;
                        if (SOFTimerClr == 1'b1)
                          next_SOFTimer <= 16'h0000;
                        else
                          next_SOFTimer <= SOFTimer + 1'b1;
                        if (SOFEnable == 1'b0)
                        begin
                                NextState_sofCntl <= `WAIT_SOF_EN;
                                next_SOFTimer <= 16'h0000;
                        end
                end
                `SC_WAIT_GNT:
                        if (HCTxPortGnt == 1'b1)
                                NextState_sofCntl <= `WAIT_SEND_RESUME;
                `CLR_WEN:
                begin
                        next_HCTxPortWEn <= 1'b0;
                        NextState_sofCntl <= `INC_TIMER;
                end
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sofCntl_CurrentState
        if (rst)
                CurrState_sofCntl <= `START_SC;
        else
                CurrState_sofCntl <= NextState_sofCntl;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sofCntl_RegOutput
        if (rst)
        begin
                SOFTimer <= 16'h0000;
                HCTxPortCntl <= 8'h00;
                HCTxPortData <= 8'h00;
                HCTxPortWEn <= 1'b0;
                HCTxPortReq <= 1'b0;
        end
        else
        begin
                SOFTimer <= next_SOFTimer;
                HCTxPortCntl <= next_HCTxPortCntl;
                HCTxPortData <= next_HCTxPortData;
                HCTxPortWEn <= next_HCTxPortWEn;
                HCTxPortReq <= next_HCTxPortReq;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author : Steve`
6			`// Company : Base2Designs`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sofcontroller.v`
11			`// Generated : 09/08/04 06:24:36`
12			`// From : c:\projects\USBHostSlave\RTL\hostController\sofcontroller.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbSerialInterfaceEngine_h.v"
23
24			`module SOFController (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, SOFEnable, SOFTimerClr, SOFTimer, clk, rst);`
25			`input HCTxPortGnt;`
26			`input HCTxPortRdy;`
27			`input SOFEnable;`
28			`input SOFTimerClr;`
29			`input clk;`
30			`input rst;`
31			`output [7:0] HCTxPortCntl;`
32			`output [7:0] HCTxPortData;`
33			`output HCTxPortReq;`
34			`output HCTxPortWEn;`
35			`output [15:0] SOFTimer;`
36
37			`reg [7:0] HCTxPortCntl, next_HCTxPortCntl;`
38			`reg [7:0] HCTxPortData, next_HCTxPortData;`
39			`wire HCTxPortGnt;`
40			`wire HCTxPortRdy;`
41			`reg HCTxPortReq, next_HCTxPortReq;`
42			`reg HCTxPortWEn, next_HCTxPortWEn;`
43			`wire SOFEnable;`
44			`wire SOFTimerClr;`
45			`reg [15:0] SOFTimer, next_SOFTimer;`
46			`wire clk;`
47			`wire rst;`
48
49			`// BINARY ENCODED state machine: sofCntl`
50			`// State codes definitions:`
51			`define START_SC 3'b000
52			`define WAIT_SOF_EN 3'b001
53			`define WAIT_SEND_RESUME 3'b010
54			`define INC_TIMER 3'b011
55			`define SC_WAIT_GNT 3'b100
56			`define CLR_WEN 3'b101
57
58			`reg [2:0] CurrState_sofCntl;`
59			`reg [2:0] NextState_sofCntl;`
60
61
62			`//--------------------------------------------------------------------`
63			`// Machine: sofCntl`
64			`//--------------------------------------------------------------------`
65			`//----------------------------------`
66			`// NextState logic (combinatorial)`
67			`//----------------------------------`
68			`always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)`
69			`begin : sofCntl_NextState`
70			`NextState_sofCntl <= CurrState_sofCntl;`
71			`// Set default values for outputs and signals`
72			`next_HCTxPortReq <= HCTxPortReq;`
73			`next_HCTxPortWEn <= HCTxPortWEn;`
74			`next_HCTxPortData <= HCTxPortData;`
75			`next_HCTxPortCntl <= HCTxPortCntl;`
76			`next_SOFTimer <= SOFTimer;`
77			`case (CurrState_sofCntl) // synopsys parallel_case full_case`
78			`START_SC:
79			NextState_sofCntl <= `WAIT_SOF_EN;
80			`WAIT_SOF_EN:
81			`if (SOFEnable == 1'b1)`
82			`begin`
83			NextState_sofCntl <= `SC_WAIT_GNT;
84			`next_HCTxPortReq <= 1'b1;`
85			`end`
86			`WAIT_SEND_RESUME:
87			`if (HCTxPortRdy == 1'b1)`
88			`begin`
89			NextState_sofCntl <= `CLR_WEN;
90			`next_HCTxPortWEn <= 1'b1;`
91			`next_HCTxPortData <= 8'h00;`
92			next_HCTxPortCntl <= `TX_RESUME_START;
93			`end`
94			`INC_TIMER:
95			`begin`
96			`next_HCTxPortReq <= 1'b0;`
97			`if (SOFTimerClr == 1'b1)`
98			`next_SOFTimer <= 16'h0000;`
99			`else`
100			`next_SOFTimer <= SOFTimer + 1'b1;`
101			`if (SOFEnable == 1'b0)`
102			`begin`
103			NextState_sofCntl <= `WAIT_SOF_EN;
104			`next_SOFTimer <= 16'h0000;`
105			`end`
106			`end`
107			`SC_WAIT_GNT:
108			`if (HCTxPortGnt == 1'b1)`
109			NextState_sofCntl <= `WAIT_SEND_RESUME;
110			`CLR_WEN:
111			`begin`
112			`next_HCTxPortWEn <= 1'b0;`
113			NextState_sofCntl <= `INC_TIMER;
114			`end`
115			`endcase`
116			`end`
117
118			`//----------------------------------`
119			`// Current State Logic (sequential)`
120			`//----------------------------------`
121			`always @ (posedge clk)`
122			`begin : sofCntl_CurrentState`
123			`if (rst)`
124			CurrState_sofCntl <= `START_SC;
125			`else`
126			`CurrState_sofCntl <= NextState_sofCntl;`
127			`end`
128
129			`//----------------------------------`
130			`// Registered outputs logic`
131			`//----------------------------------`
132			`always @ (posedge clk)`
133			`begin : sofCntl_RegOutput`
134			`if (rst)`
135			`begin`
136			`SOFTimer <= 16'h0000;`
137			`HCTxPortCntl <= 8'h00;`
138			`HCTxPortData <= 8'h00;`
139			`HCTxPortWEn <= 1'b0;`
140			`HCTxPortReq <= 1'b0;`
141			`end`
142			`else`
143			`begin`
144			`SOFTimer <= next_SOFTimer;`
145			`HCTxPortCntl <= next_HCTxPortCntl;`
146			`HCTxPortData <= next_HCTxPortData;`
147			`HCTxPortWEn <= next_HCTxPortWEn;`
148			`HCTxPortReq <= next_HCTxPortReq;`
149			`end`
150			`end`
151
152			`endmodule`

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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sofcontroller.v] - Blame information for rev 2