OpenCores
URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostSlaveMux/] [hostSlaveMuxBI.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 sfielding
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// hostSlaveMuxBI.v                                             ////
4
////                                                              ////
5
//// This file is part of the usbhostslave opencores effort.
6
//// <http://www.opencores.org/cores//>                           ////
7
////                                                              ////
8
//// Module Description:                                          ////
9
//// 
10
////                                                              ////
11
//// To Do:                                                       ////
12
//// 
13
////                                                              ////
14
//// Author(s):                                                   ////
15
//// - Steve Fielding, sfielding@base2designs.com                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE. See the GNU Lesser General Public License for more  ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from <http://www.opencores.org/lgpl.shtml>                   ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 5 sfielding
// $Id: hostSlaveMuxBI.v,v 1.2 2004-12-18 14:36:12 sfielding Exp $
45 2 sfielding
//
46
// CVS Revision History
47
//
48
// $Log: not supported by cvs2svn $
49 5 sfielding
// Revision 1.1.1.1  2004/10/11 04:00:56  sfielding
50
// Created
51 2 sfielding
//
52 5 sfielding
//
53 2 sfielding
 
54
 module hostSlaveMuxBI (dataIn, dataOut, writeEn, strobe_i, clk, rst,
55 5 sfielding
  hostMode, hostSlaveMuxSel);
56 2 sfielding
 
57
input [7:0] dataIn;
58
input writeEn;
59
input strobe_i;
60
input clk;
61
input rst;
62
output [7:0] dataOut;
63
input hostSlaveMuxSel;
64
output hostMode;
65
 
66
wire [7:0] dataIn;
67
wire writeEn;
68
wire strobe_i;
69
wire clk;
70
wire rst;
71
reg [7:0] dataOut;
72
wire hostSlaveMuxSel;
73
reg hostMode;
74
 
75
//internal wire and regs
76
 
77
//sync write demux
78
always @(posedge clk)
79
begin
80
  if (rst == 1'b1)
81
    hostMode <= 1'b0;
82
  else begin
83 5 sfielding
    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1)
84
      hostMode <= dataIn[0];
85 2 sfielding
  end
86
end
87
 
88
 
89
// async read mux
90
always @(hostMode)
91
begin
92 5 sfielding
  dataOut <= {7'h0, hostMode};
93 2 sfielding
end
94
 
95
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.