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[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbSerialInterfaceEngine_h.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
// usbSerialInterfaceEngine_h.v                                
//////////////////////////////////////////////////////////////////////
 
`ifdef usbSerialInterfaceEngine_h_vdefined
`else
`define usbSerialInterfaceEngine_h_vdefined
 
 // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
`define FS_OVER_SAMPLE_RATE 4
`define LS_OVER_SAMPLE_RATE 32
 
//timeOuts
`define RX_PACKET_TOUT 18
 
//TXStreamControlTypes
`define TX_DIRECT_CONTROL 8'h00
`define TX_RESUME_START 8'h01
`define TX_PACKET_START 8'h02
`define TX_PACKET_STREAM 8'h03
`define TX_PACKET_STOP 8'h04
`define TX_IDLE 8'h05
 
//RXStreamControlTypes
`define RX_PACKET_START 0
`define RX_PACKET_STREAM 1
`define RX_PACKET_STOP 2
 
//USBLineStates
// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
`define ONE_ZERO 2'b10
`define ZERO_ONE 2'b01
`define SE0 2'b00
`define SE1 2'b11
 
//RXStatusIndices
`define CRC_ERROR_BIT 0
`define BIT_STUFF_ERROR_BIT 1
`define RX_OVERFLOW_BIT 2
`define NAK_RXED_BIT 3
`define STALL_RXED_BIT 4
`define ACK_RXED_BIT 5
`define DATA_SEQUENCE_BIT 6
 
//usbWireControlStates
`define TRI_STATE 1'b0
`define DRIVE 1'b1
 
//limits
`define MAX_CONSEC_SAME_BITS 4'h6
`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
`define RESUME_WAIT_TIME 10
`define RESUME_WAIT_TIME_MINUS1 9
`define RESUME_LEN 20
`define CONNECT_WAIT_TIME 8'd20
`define DISCONNECT_WAIT_TIME 8'd20
 
//RXConnectStates
`define DISCONNECT 2'b00
`define LOW_SPEED_CONNECT 2'b01
`define FULL_SPEED_CONNECT 2'b10
 
//TX_RX_InternalStreamTypes
`define DATA_START 8'h00
`define DATA_STOP 8'h01
`define DATA_STREAM 8'h02
`define DATA_BIT_STUFF_ERROR 8'h03
 
//RXStMach states
`define DISCONNECT_ST 4'h0
`define WAIT_FULL_SPEED_CONN_ST 4'h1
`define WAIT_LOW_SPEED_CONN_ST 4'h2
`define CONNECT_LOW_SPEED_ST 4'h3
`define CONNECT_FULL_SPEED_ST 4'h4
`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
 
//RXBitStateMachStates
`define IDLE_BIT_ST 2'b00
`define DATA_RECEIVE_BIT_ST 2'b01
`define WAIT_RESUME_ST 2'b10
`define RESUME_END_WAIT_ST 2'b11
 
//RXByteStateMachStates 
`define IDLE_BYTE_ST 3'b000
`define CHECK_SYNC_ST 3'b001
`define CHECK_PID_ST 3'b010
`define HS_BYTE_ST 3'b011
`define TOKEN_BYTE_ST 3'b100
`define DATA_BYTE_ST 3'b101
 
`endif //usbSerialInterfaceEngine_h_vdefined
 
 

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2	5	sfielding	`// usbSerialInterfaceEngine_h.v`
3			`//////////////////////////////////////////////////////////////////////`
4	2	sfielding
5	5	sfielding	`ifdef usbSerialInterfaceEngine_h_vdefined
6			`else
7			`define usbSerialInterfaceEngine_h_vdefined
8	2	sfielding
9	9	sfielding	`// Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate`
10			`define FS_OVER_SAMPLE_RATE 4
11			`define LS_OVER_SAMPLE_RATE 32
12	2	sfielding
13			`//timeOuts`
14			`define RX_PACKET_TOUT 18
15
16			`//TXStreamControlTypes`
17			`define TX_DIRECT_CONTROL 8'h00
18			`define TX_RESUME_START 8'h01
19			`define TX_PACKET_START 8'h02
20			`define TX_PACKET_STREAM 8'h03
21			`define TX_PACKET_STOP 8'h04
22			`define TX_IDLE 8'h05
23
24			`//RXStreamControlTypes`
25			`define RX_PACKET_START 0
26			`define RX_PACKET_STREAM 1
27			`define RX_PACKET_STOP 2
28
29			`//USBLineStates`
30			`// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo`
31			`define ONE_ZERO 2'b10
32			`define ZERO_ONE 2'b01
33			`define SE0 2'b00
34			`define SE1 2'b11
35
36			`//RXStatusIndices`
37			`define CRC_ERROR_BIT 0
38			`define BIT_STUFF_ERROR_BIT 1
39			`define RX_OVERFLOW_BIT 2
40			`define NAK_RXED_BIT 3
41			`define STALL_RXED_BIT 4
42			`define ACK_RXED_BIT 5
43			`define DATA_SEQUENCE_BIT 6
44
45			`//usbWireControlStates`
46			`define TRI_STATE 1'b0
47			`define DRIVE 1'b1
48
49			`//limits`
50	12	sfielding	`define MAX_CONSEC_SAME_BITS 4'h6
51			`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
52	2	sfielding	`define RESUME_WAIT_TIME 10
53			`define RESUME_WAIT_TIME_MINUS1 9
54			`define RESUME_LEN 20
55			`define CONNECT_WAIT_TIME 8'd20
56			`define DISCONNECT_WAIT_TIME 8'd20
57
58			`//RXConnectStates`
59			`define DISCONNECT 2'b00
60			`define LOW_SPEED_CONNECT 2'b01
61			`define FULL_SPEED_CONNECT 2'b10
62
63			`//TX_RX_InternalStreamTypes`
64			`define DATA_START 8'h00
65			`define DATA_STOP 8'h01
66			`define DATA_STREAM 8'h02
67			`define DATA_BIT_STUFF_ERROR 8'h03
68
69			`//RXStMach states`
70			`define DISCONNECT_ST 4'h0
71			`define WAIT_FULL_SPEED_CONN_ST 4'h1
72			`define WAIT_LOW_SPEED_CONN_ST 4'h2
73			`define CONNECT_LOW_SPEED_ST 4'h3
74			`define CONNECT_FULL_SPEED_ST 4'h4
75			`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
76			`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
77
78			`//RXBitStateMachStates`
79			`define IDLE_BIT_ST 2'b00
80			`define DATA_RECEIVE_BIT_ST 2'b01
81			`define WAIT_RESUME_ST 2'b10
82			`define RESUME_END_WAIT_ST 2'b11
83
84			`//RXByteStateMachStates`
85			`define IDLE_BYTE_ST 3'b000
86			`define CHECK_SYNC_ST 3'b001
87			`define CHECK_PID_ST 3'b010
88			`define HS_BYTE_ST 3'b011
89			`define TOKEN_BYTE_ST 3'b100
90			`define DATA_BYTE_ST 3'b101
91
92	5	sfielding	`endif //usbSerialInterfaceEngine_h_vdefined
93	2	sfielding
94

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[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbSerialInterfaceEngine_h.v] - Blame information for rev 12