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[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbSerialInterfaceEngine_h.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
// usbSerialInterfaceEngine_h.v                                
//
// $Id: usbSerialInterfaceEngine_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
// Created
//////////////////////////////////////////////////////////////////////
 
`ifdef usbSerialInterfaceEngine_h_vdefined
`else
`define usbSerialInterfaceEngine_h_vdefined
 
 // Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate
`define OVER_SAMPLE_RATE 4
 
//timeOuts
`define RX_PACKET_TOUT 18
 
//TXStreamControlTypes
`define TX_DIRECT_CONTROL 8'h00
`define TX_RESUME_START 8'h01
`define TX_PACKET_START 8'h02
`define TX_PACKET_STREAM 8'h03
`define TX_PACKET_STOP 8'h04
`define TX_IDLE 8'h05
 
//RXStreamControlTypes
`define RX_PACKET_START 0
`define RX_PACKET_STREAM 1
`define RX_PACKET_STOP 2
 
//USBLineStates
// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
`define ONE_ZERO 2'b10
`define ZERO_ONE 2'b01
`define SE0 2'b00
`define SE1 2'b11
 
//RXStatusIndices
`define CRC_ERROR_BIT 0
`define BIT_STUFF_ERROR_BIT 1
`define RX_OVERFLOW_BIT 2
`define NAK_RXED_BIT 3
`define STALL_RXED_BIT 4
`define ACK_RXED_BIT 5
`define DATA_SEQUENCE_BIT 6
 
//usbWireControlStates
`define TRI_STATE 1'b0
`define DRIVE 1'b1
 
//limits
`define MAX_CONSEC_SAME_BITS 6
`define RESUME_WAIT_TIME 10
`define RESUME_WAIT_TIME_MINUS1 9
`define RESUME_LEN 20
`define CONNECT_WAIT_TIME 8'd20
`define DISCONNECT_WAIT_TIME 8'd20
 
//RXConnectStates
`define DISCONNECT 2'b00
`define LOW_SPEED_CONNECT 2'b01
`define FULL_SPEED_CONNECT 2'b10
 
//TX_RX_InternalStreamTypes
`define DATA_START 8'h00
`define DATA_STOP 8'h01
`define DATA_STREAM 8'h02
`define DATA_BIT_STUFF_ERROR 8'h03
 
//RXStMach states
`define DISCONNECT_ST 4'h0
`define WAIT_FULL_SPEED_CONN_ST 4'h1
`define WAIT_LOW_SPEED_CONN_ST 4'h2
`define CONNECT_LOW_SPEED_ST 4'h3
`define CONNECT_FULL_SPEED_ST 4'h4
`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
 
//RXBitStateMachStates
`define IDLE_BIT_ST 2'b00
`define DATA_RECEIVE_BIT_ST 2'b01
`define WAIT_RESUME_ST 2'b10
`define RESUME_END_WAIT_ST 2'b11
 
//RXByteStateMachStates 
`define IDLE_BYTE_ST 3'b000
`define CHECK_SYNC_ST 3'b001
`define CHECK_PID_ST 3'b010
`define HS_BYTE_ST 3'b011
`define TOKEN_BYTE_ST 3'b100
`define DATA_BYTE_ST 3'b101
 
`endif //usbSerialInterfaceEngine_h_vdefined
 
 

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2	5	sfielding	`// usbSerialInterfaceEngine_h.v`
3	2	sfielding	`//`
4	5	sfielding	`// $Id: usbSerialInterfaceEngine_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $`
5	2	sfielding	`//`
6			`// CVS Revision History`
7			`//`
8			`// $Log: not supported by cvs2svn $`
9	5	sfielding	`// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding`
10			`// Created`
11			`//////////////////////////////////////////////////////////////////////`
12	2	sfielding
13	5	sfielding	`ifdef usbSerialInterfaceEngine_h_vdefined
14			`else
15			`define usbSerialInterfaceEngine_h_vdefined
16	2	sfielding
17			`// Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate`
18			`define OVER_SAMPLE_RATE 4
19
20			`//timeOuts`
21			`define RX_PACKET_TOUT 18
22
23			`//TXStreamControlTypes`
24			`define TX_DIRECT_CONTROL 8'h00
25			`define TX_RESUME_START 8'h01
26			`define TX_PACKET_START 8'h02
27			`define TX_PACKET_STREAM 8'h03
28			`define TX_PACKET_STOP 8'h04
29			`define TX_IDLE 8'h05
30
31			`//RXStreamControlTypes`
32			`define RX_PACKET_START 0
33			`define RX_PACKET_STREAM 1
34			`define RX_PACKET_STOP 2
35
36			`//USBLineStates`
37			`// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo`
38			`define ONE_ZERO 2'b10
39			`define ZERO_ONE 2'b01
40			`define SE0 2'b00
41			`define SE1 2'b11
42
43			`//RXStatusIndices`
44			`define CRC_ERROR_BIT 0
45			`define BIT_STUFF_ERROR_BIT 1
46			`define RX_OVERFLOW_BIT 2
47			`define NAK_RXED_BIT 3
48			`define STALL_RXED_BIT 4
49			`define ACK_RXED_BIT 5
50			`define DATA_SEQUENCE_BIT 6
51
52			`//usbWireControlStates`
53			`define TRI_STATE 1'b0
54			`define DRIVE 1'b1
55
56			`//limits`
57			`define MAX_CONSEC_SAME_BITS 6
58			`define RESUME_WAIT_TIME 10
59			`define RESUME_WAIT_TIME_MINUS1 9
60			`define RESUME_LEN 20
61			`define CONNECT_WAIT_TIME 8'd20
62			`define DISCONNECT_WAIT_TIME 8'd20
63
64			`//RXConnectStates`
65			`define DISCONNECT 2'b00
66			`define LOW_SPEED_CONNECT 2'b01
67			`define FULL_SPEED_CONNECT 2'b10
68
69			`//TX_RX_InternalStreamTypes`
70			`define DATA_START 8'h00
71			`define DATA_STOP 8'h01
72			`define DATA_STREAM 8'h02
73			`define DATA_BIT_STUFF_ERROR 8'h03
74
75			`//RXStMach states`
76			`define DISCONNECT_ST 4'h0
77			`define WAIT_FULL_SPEED_CONN_ST 4'h1
78			`define WAIT_LOW_SPEED_CONN_ST 4'h2
79			`define CONNECT_LOW_SPEED_ST 4'h3
80			`define CONNECT_FULL_SPEED_ST 4'h4
81			`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
82			`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
83
84			`//RXBitStateMachStates`
85			`define IDLE_BIT_ST 2'b00
86			`define DATA_RECEIVE_BIT_ST 2'b01
87			`define WAIT_RESUME_ST 2'b10
88			`define RESUME_END_WAIT_ST 2'b11
89
90			`//RXByteStateMachStates`
91			`define IDLE_BYTE_ST 3'b000
92			`define CHECK_SYNC_ST 3'b001
93			`define CHECK_PID_ST 3'b010
94			`define HS_BYTE_ST 3'b011
95			`define TOKEN_BYTE_ST 3'b100
96			`define DATA_BYTE_ST 3'b101
97
98	5	sfielding	`endif //usbSerialInterfaceEngine_h_vdefined
99	2	sfielding
100

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[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbSerialInterfaceEngine_h.v] - Blame information for rev 5