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sfielding |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// usbSlaveControl.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: usbSlaveControl_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//endPointConstants
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`define NUM_OF_ENDPOINTS 4
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`define NUM_OF_REGISTERS_PER_ENDPOINT 4
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`define BASE_INDEX_FOR_ENDPOINT_REGS 0
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`define ENDPOINT_CONTROL_REG 0
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`define ENDPOINT_STATUS_REG 1
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`define ENDPOINT_TRANSTYPE_STATUS_REG 2
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`define NAK_TRANSTYPE_STATUS_REG 3
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`define EP0_CTRL_REG 5'h0
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`define EP0_STS_REG 5'h1
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`define EP0_TRAN_TYPE_STS_REG 5'h2
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`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
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`define EP1_CTRL_REG 5'h4
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`define EP1_STS_REG 5'h5
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`define EP1_TRAN_TYPE_STS_REG 5'h6
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`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
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`define EP2_CTRL_REG 5'h8
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`define EP2_STS_REG 5'h9
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`define EP2_TRAN_TYPE_STS_REG 5'ha
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`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
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`define EP3_CTRL_REG 5'hc
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`define EP3_STS_REG 5'hd
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`define EP3_TRAN_TYPE_STS_REG 5'he
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`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
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//SCRegIndices
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`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
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`define SC_CONTROL_REG 5'h10
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`define SC_LINE_STATUS_REG 5'h11
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`define SC_INTERRUPT_STATUS_REG 5'h12
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`define SC_INTERRUPT_MASK_REG 5'h13
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`define SC_ADDRESS 5'h14
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`define SC_FRAME_NUM_MSP 5'h15
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`define SC_FRAME_NUM_LSP 5'h16
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`define SCREG_BUFFER_LEN 5'h17
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//SCRXStatusRegIndices
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`define NAK_SET_MASK 8'h10
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//`define CRC_ERROR_BIT 0
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//`define BIT_STUFF_ERROR_BIT 1
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//`define RX_OVERFLOW_BIT 2
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//`define RX_TIME_OUT_BIT 3
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//`define NAK_SENT_BIT 4
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//`define STALL_SENT_BIT 5
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//`define ACK_RXED_BIT 6
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//`define DATA_SEQUENCE_BIT 7
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//SCEndPointControlRegIndices
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`define ENDPOINT_ENABLE_BIT 0
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`define ENDPOINT_READY_BIT 1
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`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
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`define ENDPOINT_SEND_STALL_BIT 3
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//SCMasterControlegIndices
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`define SC_GLOBAL_ENABLE_BIT 0
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`define SC_TX_LINE_STATE_LSBIT 1
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`define SC_TX_LINE_STATE_MSBIT 2
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`define SC_DIRECT_CONTROL_BIT 3
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`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
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`define SC_FULL_SPEED_LINE_RATE_BIT 5
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//SCinterruptRegIndices
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`define TRANS_DONE_BIT 0
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`define RESUME_INT_BIT 1
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`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
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`define SOF_RECEIVED_BIT 3
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`define NAK_SENT_INT_BIT 4
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//TXTransactionTypes
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`define SC_SETUP_TRANS 0
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`define SC_IN_TRANS 1
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`define SC_OUTDATA_TRANS 2
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//timeOuts
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`define SC_RX_PACKET_TOUT 18
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