URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbSlaveControl_h.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
// usbSlaveControl.v                                           
//
// $Id: usbSlaveControl_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
// Created
//////////////////////////////////////////////////////////////////////
 
`ifdef usbSlaveControl_h_vdefined
`else
`define usbSlaveControl_h_vdefined
 
//endPointConstants 
`define NUM_OF_ENDPOINTS 4
`define NUM_OF_REGISTERS_PER_ENDPOINT 4
`define BASE_INDEX_FOR_ENDPOINT_REGS 0
`define ENDPOINT_CONTROL_REG 0
`define ENDPOINT_STATUS_REG 1
`define ENDPOINT_TRANSTYPE_STATUS_REG 2
`define NAK_TRANSTYPE_STATUS_REG 3
`define EP0_CTRL_REG 5'h0
`define EP0_STS_REG 5'h1
`define EP0_TRAN_TYPE_STS_REG 5'h2
`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
`define EP1_CTRL_REG 5'h4
`define EP1_STS_REG 5'h5
`define EP1_TRAN_TYPE_STS_REG 5'h6
`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
`define EP2_CTRL_REG 5'h8
`define EP2_STS_REG 5'h9
`define EP2_TRAN_TYPE_STS_REG 5'ha
`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
`define EP3_CTRL_REG 5'hc
`define EP3_STS_REG 5'hd
`define EP3_TRAN_TYPE_STS_REG 5'he
`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
 
 
//SCRegIndices 
`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
`define SC_CONTROL_REG 5'h10
`define SC_LINE_STATUS_REG 5'h11
`define SC_INTERRUPT_STATUS_REG 5'h12
`define SC_INTERRUPT_MASK_REG 5'h13
`define SC_ADDRESS 5'h14
`define SC_FRAME_NUM_MSP 5'h15
`define SC_FRAME_NUM_LSP 5'h16
`define SCREG_BUFFER_LEN 5'h17
//SCRXStatusRegIndices 
`define NAK_SET_MASK 8'h10
//`define CRC_ERROR_BIT 0
//`define BIT_STUFF_ERROR_BIT 1
//`define RX_OVERFLOW_BIT 2
//`define RX_TIME_OUT_BIT 3
//`define NAK_SENT_BIT 4
//`define STALL_SENT_BIT 5
//`define ACK_RXED_BIT 6
//`define DATA_SEQUENCE_BIT 7
//SCEndPointControlRegIndices 
`define ENDPOINT_ENABLE_BIT 0
`define ENDPOINT_READY_BIT 1
`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
`define ENDPOINT_SEND_STALL_BIT 3
//SCMasterControlegIndices 
`define SC_GLOBAL_ENABLE_BIT 0
`define SC_TX_LINE_STATE_LSBIT 1
`define SC_TX_LINE_STATE_MSBIT 2
`define SC_DIRECT_CONTROL_BIT 3
`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
`define SC_FULL_SPEED_LINE_RATE_BIT 5
//SCinterruptRegIndices 
`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1
`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
`define SOF_RECEIVED_BIT 3
`define NAK_SENT_INT_BIT 4
//TXTransactionTypes 
`define SC_SETUP_TRANS 0
`define SC_IN_TRANS 1
`define SC_OUTDATA_TRANS 2
//timeOuts 
`define SC_RX_PACKET_TOUT 18
 
`endif //usbSlaveControl_h_vdefined

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2	5	sfielding	`// usbSlaveControl.v`
3	2	sfielding	`//`
4	5	sfielding	`// $Id: usbSlaveControl_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $`
5	2	sfielding	`//`
6			`// CVS Revision History`
7			`//`
8			`// $Log: not supported by cvs2svn $`
9	5	sfielding	`// Revision 1.1.1.1 2004/10/11 04:00:57 sfielding`
10			`// Created`
11			`//////////////////////////////////////////////////////////////////////`
12	2	sfielding
13	5	sfielding	`ifdef usbSlaveControl_h_vdefined
14			`else
15			`define usbSlaveControl_h_vdefined
16	2	sfielding
17			`//endPointConstants`
18			`define NUM_OF_ENDPOINTS 4
19			`define NUM_OF_REGISTERS_PER_ENDPOINT 4
20			`define BASE_INDEX_FOR_ENDPOINT_REGS 0
21			`define ENDPOINT_CONTROL_REG 0
22			`define ENDPOINT_STATUS_REG 1
23			`define ENDPOINT_TRANSTYPE_STATUS_REG 2
24			`define NAK_TRANSTYPE_STATUS_REG 3
25			`define EP0_CTRL_REG 5'h0
26			`define EP0_STS_REG 5'h1
27			`define EP0_TRAN_TYPE_STS_REG 5'h2
28			`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
29			`define EP1_CTRL_REG 5'h4
30			`define EP1_STS_REG 5'h5
31			`define EP1_TRAN_TYPE_STS_REG 5'h6
32			`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
33			`define EP2_CTRL_REG 5'h8
34			`define EP2_STS_REG 5'h9
35			`define EP2_TRAN_TYPE_STS_REG 5'ha
36			`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
37			`define EP3_CTRL_REG 5'hc
38			`define EP3_STS_REG 5'hd
39			`define EP3_TRAN_TYPE_STS_REG 5'he
40			`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
41
42
43			`//SCRegIndices`
44			`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
45			`define SC_CONTROL_REG 5'h10
46			`define SC_LINE_STATUS_REG 5'h11
47			`define SC_INTERRUPT_STATUS_REG 5'h12
48			`define SC_INTERRUPT_MASK_REG 5'h13
49			`define SC_ADDRESS 5'h14
50			`define SC_FRAME_NUM_MSP 5'h15
51			`define SC_FRAME_NUM_LSP 5'h16
52			`define SCREG_BUFFER_LEN 5'h17
53			`//SCRXStatusRegIndices`
54			`define NAK_SET_MASK 8'h10
55			//`define CRC_ERROR_BIT 0
56			//`define BIT_STUFF_ERROR_BIT 1
57			//`define RX_OVERFLOW_BIT 2
58			//`define RX_TIME_OUT_BIT 3
59			//`define NAK_SENT_BIT 4
60			//`define STALL_SENT_BIT 5
61			//`define ACK_RXED_BIT 6
62			//`define DATA_SEQUENCE_BIT 7
63			`//SCEndPointControlRegIndices`
64			`define ENDPOINT_ENABLE_BIT 0
65			`define ENDPOINT_READY_BIT 1
66			`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
67			`define ENDPOINT_SEND_STALL_BIT 3
68			`//SCMasterControlegIndices`
69			`define SC_GLOBAL_ENABLE_BIT 0
70			`define SC_TX_LINE_STATE_LSBIT 1
71			`define SC_TX_LINE_STATE_MSBIT 2
72			`define SC_DIRECT_CONTROL_BIT 3
73			`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
74			`define SC_FULL_SPEED_LINE_RATE_BIT 5
75			`//SCinterruptRegIndices`
76			`define TRANS_DONE_BIT 0
77			`define RESUME_INT_BIT 1
78			`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
79			`define SOF_RECEIVED_BIT 3
80			`define NAK_SENT_INT_BIT 4
81			`//TXTransactionTypes`
82			`define SC_SETUP_TRANS 0
83			`define SC_IN_TRANS 1
84			`define SC_OUTDATA_TRANS 2
85			`//timeOuts`
86			`define SC_RX_PACKET_TOUT 18
87
88	5	sfielding	`endif //usbSlaveControl_h_vdefined

Browse

Tools

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbSlaveControl_h.v] - Blame information for rev 5