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//////////////////////////////////////////////////////////////////////
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//// ////
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//// wishBoneBus_h.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: wishBoneBus_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//memoryMap
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`define HCREG_BASE 8'h00
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`define HCREG_BASE_PLUS_0X10 8'h10
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`define HOST_RX_FIFO_BASE 8'h20
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`define HOST_TX_FIFO_BASE 8'h30
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`define SCREG_BASE 8'h40
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`define SCREG_BASE_PLUS_0X10 8'h50
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`define EP0_RX_FIFO_BASE 8'h60
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`define EP0_TX_FIFO_BASE 8'h70
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`define EP1_RX_FIFO_BASE 8'h80
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`define EP1_TX_FIFO_BASE 8'h90
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`define EP2_RX_FIFO_BASE 8'ha0
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`define EP2_TX_FIFO_BASE 8'hb0
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`define EP3_RX_FIFO_BASE 8'hc0
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`define EP3_TX_FIFO_BASE 8'hd0
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`define HOST_SLAVE_CONTROL_BASE 8'he0
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`define ADDRESS_DECODE_MASK 8'hf0
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//FifoAddresses
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`define FIFO_DATA_REG 3'b000
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`define FIFO_STATUS_REG 3'b001
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`define FIFO_DATA_COUNT_MSB 3'b010
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`define FIFO_DATA_COUNT_LSB 3'b011
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`define FIFO_CONTROL_REG 3'b100
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