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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [SIETransmitter.v] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// SIETransmitter
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
 
module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
input   clk;
input   [15:0]CRC16Result;
input   CRC16UpdateRdy;
input   [4:0]CRC5Result;
input   CRC5UpdateRdy;
input   fullSpeedRateIn;
input   [1:0]JBit;
input   [1:0]KBit;
input   processTxByteRdy;
input   rst;
input   [7:0]SIEPortCtrlIn;
input   [7:0]SIEPortDataIn;
input   SIEPortWEn;
input   USBWireGnt;
input   USBWireRdy;
output  CRC16En;
output  CRC5_8Bit;
output  CRC5En;
output  [7:0]CRCData;
output  processTxByteWEn;
output  rstCRC;
output  SIEPortTxRdy;
output  [7:0]TxByteOut;
output  [7:0]TxByteOutCtrl;
output  TxByteOutFullSpeedRate;
output  USBWireCtrl;
output  [1:0]USBWireData;
output  USBWireFullSpeedRate;
output  USBWireReq;
output  USBWireWEn;
 
wire    clk;
reg     CRC16En, next_CRC16En;
wire    [15:0]CRC16Result;
wire    CRC16UpdateRdy;
reg     CRC5_8Bit, next_CRC5_8Bit;
reg     CRC5En, next_CRC5En;
wire    [4:0]CRC5Result;
wire    CRC5UpdateRdy;
reg     [7:0]CRCData, next_CRCData;
wire    fullSpeedRateIn;
wire    [1:0]JBit;
wire    [1:0]KBit;
wire    processTxByteRdy;
reg     processTxByteWEn, next_processTxByteWEn;
wire    rst;
reg     rstCRC, next_rstCRC;
wire    [7:0]SIEPortCtrlIn;
wire    [7:0]SIEPortDataIn;
reg     SIEPortTxRdy, next_SIEPortTxRdy;
wire    SIEPortWEn;
reg     [7:0]TxByteOut, next_TxByteOut;
reg     [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
reg     TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
reg     USBWireCtrl, next_USBWireCtrl;
reg     [1:0]USBWireData, next_USBWireData;
reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire    USBWireGnt;
wire    USBWireRdy;
reg     USBWireReq, next_USBWireReq;
reg     USBWireWEn, next_USBWireWEn;
 
// diagram signals declarations
reg  [2:0]i, next_i;
reg  [15:0]resumeCnt, next_resumeCnt;
reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
reg  [7:0]SIEPortData, next_SIEPortData;
 
// BINARY ENCODED state machine: SIETx
// State codes definitions:
`define DIR_CTL_CHK_FIN 6'b000000
`define RES_ST_CHK_FIN 6'b000001
`define PKT_ST_CHK_PID 6'b000010
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
`define IDLE 6'b000100
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
`define PKT_ST_HS_PKT_SENT 6'b000111
`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
`define PKT_ST_SPCL_PKT_SENT 6'b001010
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
`define RES_ST_SND_J_1 6'b001110
`define RES_ST_SND_J_2 6'b001111
`define RES_ST_SND_SE0_1 6'b010000
`define RES_ST_SND_SE0_2 6'b010001
`define START_SIETX 6'b010010
`define STX_CHK_ST 6'b010011
`define STX_WAIT_BYTE 6'b010100
`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
`define RES_ST_W_RDY1 6'b011000
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
`define RES_ST_WAIT_GNT 6'b011100
`define DIR_CTL_WAIT_GNT 6'b011101
`define PKT_ST_HS_WAIT_RDY 6'b011110
`define PKT_ST_SPCL_WAIT_RDY 6'b011111
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
`define RES_ST_WAIT_RDY 6'b100011
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
`define DIR_CTL_WAIT_RDY 6'b100110
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
`define PKT_ST_WAIT_RDY_PKT 6'b101001
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
`define TX_LS_EOP_WAIT_GNT1 6'b101101
`define TX_LS_EOP_SND_SE0_2 6'b101110
`define TX_LS_EOP_SND_SE0_1 6'b101111
`define TX_LS_EOP_W_RDY1 6'b110000
`define TX_LS_EOP_SND_J 6'b110001
`define TX_LS_EOP_W_RDY2 6'b110010
`define TX_LS_EOP_W_RDY3 6'b110011
`define RES_ST_DELAY 6'b110100
`define RES_ST_W_RDY2 6'b110101
`define RES_ST_W_RDY3 6'b110110
`define RES_ST_W_RDY4 6'b110111
`define DIR_CTL_DELAY 6'b111000
 
reg [5:0]CurrState_SIETx, NextState_SIETx;
 
 
// Machine: SIETx
 
// NextState logic (combinatorial)
always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
begin
  NextState_SIETx <= CurrState_SIETx;
  // Set default values for outputs and signals
  next_USBWireWEn <= USBWireWEn;
  next_i <= i;
  next_USBWireReq <= USBWireReq;
  next_processTxByteWEn <= processTxByteWEn;
  next_rstCRC <= rstCRC;
  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
  next_TxByteOut <= TxByteOut;
  next_TxByteOutCtrl <= TxByteOutCtrl;
  next_USBWireData <= USBWireData;
  next_USBWireCtrl <= USBWireCtrl;
  next_CRCData <= CRCData;
  next_CRC5En <= CRC5En;
  next_CRC5_8Bit <= CRC5_8Bit;
  next_CRC16En <= CRC16En;
  next_SIEPortTxRdy <= SIEPortTxRdy;
  next_SIEPortData <= SIEPortData;
  next_SIEPortCtrl <= SIEPortCtrl;
  next_resumeCnt <= resumeCnt;
  next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
  case (CurrState_SIETx)  // synopsys parallel_case full_case
    `IDLE:
    begin
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `START_SIETX:
    begin
      next_processTxByteWEn <= 1'b0;
      next_TxByteOut <= 8'h00;
      next_TxByteOutCtrl <= 8'h00;
      next_USBWireData <= 2'b00;
      next_USBWireCtrl <= `TRI_STATE;
      next_USBWireReq <= 1'b0;
      next_USBWireWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      next_CRCData <= 8'h00;
      next_CRC5En <= 1'b0;
      next_CRC5_8Bit <= 1'b0;
      next_CRC16En <= 1'b0;
      next_SIEPortTxRdy <= 1'b0;
      next_SIEPortData <= 8'h00;
      next_SIEPortCtrl <= 8'h00;
      next_i <= 3'h0;
      next_resumeCnt <= 16'h0000;
      next_TxByteOutFullSpeedRate <= 1'b0;
      next_USBWireFullSpeedRate <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `STX_CHK_ST:
    begin
      if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
      begin
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
        next_TxByteOutFullSpeedRate <= 1'b1;
        //SOF and PRE always at full speed
      end
      else if (SIEPortCtrl == `TX_PACKET_START)
      begin
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
      end
      else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
      begin
        NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
        next_USBWireReq <= 1'b1;
      end
      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
      begin
        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
        next_USBWireReq <= 1'b1;
      end
      else if (SIEPortCtrl == `TX_IDLE)
      begin
        NextState_SIETx <= `IDLE;
      end
      else if (SIEPortCtrl == `TX_RESUME_START)
      begin
        NextState_SIETx <= `RES_ST_WAIT_GNT;
        next_USBWireReq <= 1'b1;
        next_resumeCnt <= 16'h0000;
        next_USBWireFullSpeedRate <= 1'b0;
        //resume always uses low speed timing
      end
    end
    `STX_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `STX_CHK_ST;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
        next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
        next_USBWireFullSpeedRate <= fullSpeedRateIn;
      end
    end
    `DIR_CTL_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      next_i <= i + 1'b1;
      if (i == 3'h7)
      begin
        NextState_SIETx <= `STX_WAIT_BYTE;
        next_USBWireReq <= 1'b0;
      end
      else
      begin
        NextState_SIETx <= `DIR_CTL_DELAY;
      end
    end
    `DIR_CTL_WAIT_GNT:
    begin
      next_i <= 3'h0;
      if (USBWireGnt == 1'b1)
      begin
        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
      end
    end
    `DIR_CTL_WAIT_RDY:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `DIR_CTL_CHK_FIN;
        next_USBWireData <= SIEPortData[1:0];
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `DIR_CTL_DELAY:
    begin
      NextState_SIETx <= `DIR_CTL_WAIT_RDY;
    end
    `PKT_ST_CHK_PID:
    begin
      next_processTxByteWEn <= 1'b0;
      if (SIEPortData[1:0] == `TOKEN)
      begin
        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
      end
      else if (SIEPortData[1:0] == `HANDSHAKE)
      begin
        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
      end
      else if (SIEPortData[1:0] == `DATA)
      begin
        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
      end
      else if (SIEPortData[1:0] == `SPECIAL)
      begin
        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
      end
    end
    `PKT_ST_WAIT_RDY_PKT:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_CHK_PID;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= `SYNC_BYTE;
        next_TxByteOutCtrl <= `DATA_START;
      end
    end
    `PKT_ST_DATA_CRC_PKT_SENT1:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
    end
    `PKT_ST_DATA_CRC_PKT_SENT2:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_DATA_CRC_WAIT_RDY1:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= ~CRC16Result[7:0];
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    end
    `PKT_ST_DATA_CRC_WAIT_RDY2:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= ~CRC16Result[15:8];
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_DATA_DATA_CHK_STOP:
    begin
      if (SIEPortCtrl == `TX_PACKET_STOP)
      begin
        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
      end
      else
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
      end
    end
    `PKT_ST_DATA_DATA_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
    end
    `PKT_ST_DATA_DATA_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC16En <= 1'b1;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
    end
    `PKT_ST_DATA_DATA_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_DATA_DATA_WAIT_RDY:
    begin
      next_CRC16En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    end
    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
    begin
      if (CRC16UpdateRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
      end
    end
    `PKT_ST_DATA_PID_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
    end
    `PKT_ST_DATA_PID_WAIT_RDY:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
        next_rstCRC <= 1'b1;
      end
    end
    `PKT_ST_HS_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_HS_WAIT_RDY:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_SPCL_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_SPCL_WAIT_RDY:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_TKN_BYTE1_PKT_SENT1:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
    end
    `PKT_ST_TKN_BYTE1_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC5_8Bit <= 1'b1;
      next_CRC5En <= 1'b1;
      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
    end
    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_TKN_BYTE1_WAIT_RDY:
    begin
      next_CRC5En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    end
    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
    begin
      if (CRC5UpdateRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
      end
    end
    `PKT_ST_TKN_CRC_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_TKN_CRC_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC5_8Bit <= 1'b0;
      next_CRC5En <= 1'b1;
      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
    end
    `PKT_ST_TKN_CRC_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_TKN_CRC_WAIT_RDY:
    begin
      next_CRC5En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
    begin
      if (CRC5UpdateRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
      end
    end
    `PKT_ST_TKN_PID_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
    end
    `PKT_ST_TKN_PID_WAIT_RDY:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
        next_rstCRC <= 1'b1;
      end
    end
    `RES_ST_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      if (resumeCnt == `HOST_TX_RESUME_TIME)
      begin
        NextState_SIETx <= `RES_ST_W_RDY1;
      end
      else
      begin
        NextState_SIETx <= `RES_ST_DELAY;
      end
    end
    `RES_ST_SND_J_1:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `RES_ST_W_RDY4;
    end
    `RES_ST_SND_J_2:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
      next_USBWireFullSpeedRate <= fullSpeedRateIn;
    end
    `RES_ST_SND_SE0_1:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `RES_ST_W_RDY2;
    end
    `RES_ST_SND_SE0_2:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `RES_ST_W_RDY3;
    end
    `RES_ST_W_RDY1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_SND_SE0_1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `RES_ST_WAIT_GNT:
    begin
      if (USBWireGnt == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_WAIT_RDY;
      end
    end
    `RES_ST_WAIT_RDY:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_CHK_FIN;
        next_USBWireData <= KBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
        next_resumeCnt <= resumeCnt  + 1'b1;
      end
    end
    `RES_ST_DELAY:
    begin
      NextState_SIETx <= `RES_ST_WAIT_RDY;
    end
    `RES_ST_W_RDY2:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_SND_SE0_2;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `RES_ST_W_RDY3:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_SND_J_1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `RES_ST_W_RDY4:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_SND_J_2;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `TX_LS_EOP_WAIT_GNT1:
    begin
      if (USBWireGnt == 1'b1)
      begin
        NextState_SIETx <= `TX_LS_EOP_W_RDY1;
      end
    end
    `TX_LS_EOP_SND_SE0_2:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `TX_LS_EOP_W_RDY3;
    end
    `TX_LS_EOP_SND_SE0_1:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `TX_LS_EOP_W_RDY2;
    end
    `TX_LS_EOP_W_RDY1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `TX_LS_EOP_SND_J:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `TX_LS_EOP_W_RDY2:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `TX_LS_EOP_W_RDY3:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `TX_LS_EOP_SND_J;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_SIETx <= `START_SIETX;
  else
    CurrState_SIETx <= NextState_SIETx;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    USBWireWEn <= 1'b0;
    USBWireReq <= 1'b0;
    processTxByteWEn <= 1'b0;
    rstCRC <= 1'b0;
    USBWireFullSpeedRate <= 1'b0;
    TxByteOut <= 8'h00;
    TxByteOutCtrl <= 8'h00;
    USBWireData <= 2'b00;
    USBWireCtrl <= `TRI_STATE;
    CRCData <= 8'h00;
    CRC5En <= 1'b0;
    CRC5_8Bit <= 1'b0;
    CRC16En <= 1'b0;
    SIEPortTxRdy <= 1'b0;
    TxByteOutFullSpeedRate <= 1'b0;
    i <= 3'h0;
    SIEPortData <= 8'h00;
    SIEPortCtrl <= 8'h00;
    resumeCnt <= 16'h0000;
  end
  else
  begin
    USBWireWEn <= next_USBWireWEn;
    USBWireReq <= next_USBWireReq;
    processTxByteWEn <= next_processTxByteWEn;
    rstCRC <= next_rstCRC;
    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
    TxByteOut <= next_TxByteOut;
    TxByteOutCtrl <= next_TxByteOutCtrl;
    USBWireData <= next_USBWireData;
    USBWireCtrl <= next_USBWireCtrl;
    CRCData <= next_CRCData;
    CRC5En <= next_CRC5En;
    CRC5_8Bit <= next_CRC5_8Bit;
    CRC16En <= next_CRC16En;
    SIEPortTxRdy <= next_SIEPortTxRdy;
    TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
    i <= next_i;
    SIEPortData <= next_SIEPortData;
    SIEPortCtrl <= next_SIEPortCtrl;
    resumeCnt <= next_resumeCnt;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// SIETransmitter`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbConstants_h.v"
48
49
50	14	sfielding	`module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);`
51	5	sfielding	`input clk;`
52			`input [15:0]CRC16Result;`
53			`input CRC16UpdateRdy;`
54			`input [4:0]CRC5Result;`
55			`input CRC5UpdateRdy;`
56	14	sfielding	`input fullSpeedRateIn;`
57	5	sfielding	`input [1:0]JBit;`
58			`input [1:0]KBit;`
59			`input processTxByteRdy;`
60			`input rst;`
61			`input [7:0]SIEPortCtrlIn;`
62			`input [7:0]SIEPortDataIn;`
63			`input SIEPortWEn;`
64			`input USBWireGnt;`
65			`input USBWireRdy;`
66			`output CRC16En;`
67			`output CRC5_8Bit;`
68			`output CRC5En;`
69			`output [7:0]CRCData;`
70			`output processTxByteWEn;`
71			`output rstCRC;`
72			`output SIEPortTxRdy;`
73			`output [7:0]TxByteOut;`
74			`output [7:0]TxByteOutCtrl;`
75	14	sfielding	`output TxByteOutFullSpeedRate;`
76	5	sfielding	`output USBWireCtrl;`
77			`output [1:0]USBWireData;`
78	14	sfielding	`output USBWireFullSpeedRate;`
79	5	sfielding	`output USBWireReq;`
80			`output USBWireWEn;`
81
82			`wire clk;`
83			`reg CRC16En, next_CRC16En;`
84			`wire [15:0]CRC16Result;`
85			`wire CRC16UpdateRdy;`
86			`reg CRC5_8Bit, next_CRC5_8Bit;`
87			`reg CRC5En, next_CRC5En;`
88			`wire [4:0]CRC5Result;`
89			`wire CRC5UpdateRdy;`
90			`reg [7:0]CRCData, next_CRCData;`
91	14	sfielding	`wire fullSpeedRateIn;`
92	5	sfielding	`wire [1:0]JBit;`
93			`wire [1:0]KBit;`
94			`wire processTxByteRdy;`
95			`reg processTxByteWEn, next_processTxByteWEn;`
96			`wire rst;`
97			`reg rstCRC, next_rstCRC;`
98			`wire [7:0]SIEPortCtrlIn;`
99			`wire [7:0]SIEPortDataIn;`
100			`reg SIEPortTxRdy, next_SIEPortTxRdy;`
101			`wire SIEPortWEn;`
102			`reg [7:0]TxByteOut, next_TxByteOut;`
103			`reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;`
104	14	sfielding	`reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;`
105	5	sfielding	`reg USBWireCtrl, next_USBWireCtrl;`
106			`reg [1:0]USBWireData, next_USBWireData;`
107	14	sfielding	`reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;`
108	5	sfielding	`wire USBWireGnt;`
109			`wire USBWireRdy;`
110			`reg USBWireReq, next_USBWireReq;`
111			`reg USBWireWEn, next_USBWireWEn;`
112
113			`// diagram signals declarations`
114	14	sfielding	`reg [2:0]i, next_i;`
115			`reg [15:0]resumeCnt, next_resumeCnt;`
116	5	sfielding	`reg [7:0]SIEPortCtrl, next_SIEPortCtrl;`
117			`reg [7:0]SIEPortData, next_SIEPortData;`
118
119			`// BINARY ENCODED state machine: SIETx`
120			`// State codes definitions:`
121	14	sfielding	`define DIR_CTL_CHK_FIN 6'b000000
122			`define RES_ST_CHK_FIN 6'b000001
123	9	sfielding	`define PKT_ST_CHK_PID 6'b000010
124			`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
125			`define IDLE 6'b000100
126	14	sfielding	`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
127			`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
128			`define PKT_ST_HS_PKT_SENT 6'b000111
129			`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
130			`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
131			`define PKT_ST_SPCL_PKT_SENT 6'b001010
132	5	sfielding	`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
133			`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
134			`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
135	14	sfielding	`define RES_ST_SND_J_1 6'b001110
136			`define RES_ST_SND_J_2 6'b001111
137			`define RES_ST_SND_SE0_1 6'b010000
138			`define RES_ST_SND_SE0_2 6'b010001
139			`define START_SIETX 6'b010010
140			`define STX_CHK_ST 6'b010011
141			`define STX_WAIT_BYTE 6'b010100
142			`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
143			`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
144			`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
145			`define RES_ST_W_RDY1 6'b011000
146			`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
147			`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
148			`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
149			`define RES_ST_WAIT_GNT 6'b011100
150			`define DIR_CTL_WAIT_GNT 6'b011101
151			`define PKT_ST_HS_WAIT_RDY 6'b011110
152			`define PKT_ST_SPCL_WAIT_RDY 6'b011111
153			`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
154	9	sfielding	`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
155			`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
156	14	sfielding	`define RES_ST_WAIT_RDY 6'b100011
157			`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
158			`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
159			`define DIR_CTL_WAIT_RDY 6'b100110
160			`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
161			`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
162			`define PKT_ST_WAIT_RDY_PKT 6'b101001
163			`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
164			`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
165			`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
166			`define TX_LS_EOP_WAIT_GNT1 6'b101101
167			`define TX_LS_EOP_SND_SE0_2 6'b101110
168			`define TX_LS_EOP_SND_SE0_1 6'b101111
169			`define TX_LS_EOP_W_RDY1 6'b110000
170			`define TX_LS_EOP_SND_J 6'b110001
171			`define TX_LS_EOP_W_RDY2 6'b110010
172			`define TX_LS_EOP_W_RDY3 6'b110011
173			`define RES_ST_DELAY 6'b110100
174			`define RES_ST_W_RDY2 6'b110101
175			`define RES_ST_W_RDY3 6'b110110
176			`define RES_ST_W_RDY4 6'b110111
177			`define DIR_CTL_DELAY 6'b111000
178	5	sfielding
179			`reg [5:0]CurrState_SIETx, NextState_SIETx;`
180
181
182			`// Machine: SIETx`
183
184			`// NextState logic (combinatorial)`
185	14	sfielding	`always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)`
186	5	sfielding	`begin`
187			`NextState_SIETx <= CurrState_SIETx;`
188			`// Set default values for outputs and signals`
189			`next_USBWireWEn <= USBWireWEn;`
190			`next_i <= i;`
191			`next_USBWireReq <= USBWireReq;`
192			`next_processTxByteWEn <= processTxByteWEn;`
193			`next_rstCRC <= rstCRC;`
194	14	sfielding	`next_USBWireFullSpeedRate <= USBWireFullSpeedRate;`
195			`next_TxByteOut <= TxByteOut;`
196			`next_TxByteOutCtrl <= TxByteOutCtrl;`
197	5	sfielding	`next_USBWireData <= USBWireData;`
198			`next_USBWireCtrl <= USBWireCtrl;`
199			`next_CRCData <= CRCData;`
200			`next_CRC5En <= CRC5En;`
201			`next_CRC5_8Bit <= CRC5_8Bit;`
202			`next_CRC16En <= CRC16En;`
203			`next_SIEPortTxRdy <= SIEPortTxRdy;`
204			`next_SIEPortData <= SIEPortData;`
205			`next_SIEPortCtrl <= SIEPortCtrl;`
206	14	sfielding	`next_resumeCnt <= resumeCnt;`
207			`next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;`
208	5	sfielding	`case (CurrState_SIETx) // synopsys parallel_case full_case`
209	9	sfielding	`IDLE:
210			`begin`
211			NextState_SIETx <= `STX_WAIT_BYTE;
212			`end`
213	5	sfielding	`START_SIETX:
214			`begin`
215			`next_processTxByteWEn <= 1'b0;`
216			`next_TxByteOut <= 8'h00;`
217			`next_TxByteOutCtrl <= 8'h00;`
218			`next_USBWireData <= 2'b00;`
219			next_USBWireCtrl <= `TRI_STATE;
220			`next_USBWireReq <= 1'b0;`
221			`next_USBWireWEn <= 1'b0;`
222			`next_rstCRC <= 1'b0;`
223			`next_CRCData <= 8'h00;`
224			`next_CRC5En <= 1'b0;`
225			`next_CRC5_8Bit <= 1'b0;`
226			`next_CRC16En <= 1'b0;`
227			`next_SIEPortTxRdy <= 1'b0;`
228			`next_SIEPortData <= 8'h00;`
229			`next_SIEPortCtrl <= 8'h00;`
230	14	sfielding	`next_i <= 3'h0;`
231			`next_resumeCnt <= 16'h0000;`
232			`next_TxByteOutFullSpeedRate <= 1'b0;`
233			`next_USBWireFullSpeedRate <= 1'b0;`
234	5	sfielding	NextState_SIETx <= `STX_WAIT_BYTE;
235			`end`
236			`STX_CHK_ST:
237			`begin`
238	14	sfielding	if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF \|\| SIEPortData[3:0] == `PREAMBLE))
239	5	sfielding	`begin`
240	9	sfielding	NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
241	14	sfielding	`next_TxByteOutFullSpeedRate <= 1'b1;`
242			`//SOF and PRE always at full speed`
243	5	sfielding	`end`
244	14	sfielding	else if (SIEPortCtrl == `TX_PACKET_START)
245			`begin`
246			NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
247			`end`
248			else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
249			`begin`
250			NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
251			`next_USBWireReq <= 1'b1;`
252			`end`
253	7	sfielding	else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
254	5	sfielding	`begin`
255	7	sfielding	NextState_SIETx <= `DIR_CTL_WAIT_GNT;
256	5	sfielding	`next_USBWireReq <= 1'b1;`
257			`end`
258	9	sfielding	else if (SIEPortCtrl == `TX_IDLE)
259			`begin`
260			NextState_SIETx <= `IDLE;
261			`end`
262	5	sfielding	else if (SIEPortCtrl == `TX_RESUME_START)
263			`begin`
264			NextState_SIETx <= `RES_ST_WAIT_GNT;
265			`next_USBWireReq <= 1'b1;`
266	14	sfielding	`next_resumeCnt <= 16'h0000;`
267			`next_USBWireFullSpeedRate <= 1'b0;`
268			`//resume always uses low speed timing`
269	5	sfielding	`end`
270			`end`
271			`STX_WAIT_BYTE:
272			`begin`
273			`next_SIEPortTxRdy <= 1'b1;`
274			`if (SIEPortWEn == 1'b1)`
275			`begin`
276			NextState_SIETx <= `STX_CHK_ST;
277			`next_SIEPortData <= SIEPortDataIn;`
278			`next_SIEPortCtrl <= SIEPortCtrlIn;`
279			`next_SIEPortTxRdy <= 1'b0;`
280	14	sfielding	`next_TxByteOutFullSpeedRate <= fullSpeedRateIn;`
281			`next_USBWireFullSpeedRate <= fullSpeedRateIn;`
282	5	sfielding	`end`
283			`end`
284			`DIR_CTL_CHK_FIN:
285			`begin`
286			`next_USBWireWEn <= 1'b0;`
287			`next_i <= i + 1'b1;`
288	14	sfielding	`if (i == 3'h7)`
289	5	sfielding	`begin`
290			NextState_SIETx <= `STX_WAIT_BYTE;
291			`next_USBWireReq <= 1'b0;`
292			`end`
293			`else`
294			`begin`
295	14	sfielding	NextState_SIETx <= `DIR_CTL_DELAY;
296	5	sfielding	`end`
297			`end`
298			`DIR_CTL_WAIT_GNT:
299			`begin`
300	14	sfielding	`next_i <= 3'h0;`
301	5	sfielding	`if (USBWireGnt == 1'b1)`
302			`begin`
303			NextState_SIETx <= `DIR_CTL_WAIT_RDY;
304			`end`
305			`end`
306			`DIR_CTL_WAIT_RDY:
307			`begin`
308			`if (USBWireRdy == 1'b1)`
309			`begin`
310			NextState_SIETx <= `DIR_CTL_CHK_FIN;
311			`next_USBWireData <= SIEPortData[1:0];`
312			next_USBWireCtrl <= `DRIVE;
313			`next_USBWireWEn <= 1'b1;`
314			`end`
315			`end`
316	14	sfielding	`DIR_CTL_DELAY:
317			`begin`
318			NextState_SIETx <= `DIR_CTL_WAIT_RDY;
319			`end`
320	9	sfielding	`PKT_ST_CHK_PID:
321	5	sfielding	`begin`
322	9	sfielding	`next_processTxByteWEn <= 1'b0;`
323			if (SIEPortData[1:0] == `TOKEN)
324	5	sfielding	`begin`
325	9	sfielding	NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
326	5	sfielding	`end`
327	9	sfielding	else if (SIEPortData[1:0] == `HANDSHAKE)
328	5	sfielding	`begin`
329	7	sfielding	NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
330			`end`
331	9	sfielding	else if (SIEPortData[1:0] == `DATA)
332	7	sfielding	`begin`
333	9	sfielding	NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
334	5	sfielding	`end`
335	7	sfielding	else if (SIEPortData[1:0] == `SPECIAL)
336	5	sfielding	`begin`
337	7	sfielding	NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
338	5	sfielding	`end`
339			`end`
340			`PKT_ST_WAIT_RDY_PKT:
341			`begin`
342			`if (processTxByteRdy == 1'b1)`
343			`begin`
344			NextState_SIETx <= `PKT_ST_CHK_PID;
345			`next_processTxByteWEn <= 1'b1;`
346			next_TxByteOut <= `SYNC_BYTE;
347			next_TxByteOutCtrl <= `DATA_START;
348			`end`
349			`end`
350			`PKT_ST_DATA_CRC_PKT_SENT1:
351			`begin`
352			`next_processTxByteWEn <= 1'b0;`
353			NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
354			`end`
355			`PKT_ST_DATA_CRC_PKT_SENT2:
356			`begin`
357			`next_processTxByteWEn <= 1'b0;`
358			NextState_SIETx <= `STX_WAIT_BYTE;
359			`end`
360			`PKT_ST_DATA_CRC_WAIT_RDY1:
361			`begin`
362			`if (processTxByteRdy == 1'b1)`
363			`begin`
364			NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
365			`next_processTxByteWEn <= 1'b1;`
366			`next_TxByteOut <= ~CRC16Result[7:0];`
367			next_TxByteOutCtrl <= `DATA_STREAM;
368			`end`
369			`end`
370			`PKT_ST_DATA_CRC_WAIT_RDY2:
371			`begin`
372			`if (processTxByteRdy == 1'b1)`
373			`begin`
374			NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
375			`next_processTxByteWEn <= 1'b1;`
376			`next_TxByteOut <= ~CRC16Result[15:8];`
377			next_TxByteOutCtrl <= `DATA_STOP;
378			`end`
379			`end`
380			`PKT_ST_DATA_DATA_CHK_STOP:
381			`begin`
382			if (SIEPortCtrl == `TX_PACKET_STOP)
383			`begin`
384			NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
385			`end`
386			`else`
387			`begin`
388			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
389			`end`
390			`end`
391			`PKT_ST_DATA_DATA_PKT_SENT:
392			`begin`
393			`next_processTxByteWEn <= 1'b0;`
394			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
395			`end`
396			`PKT_ST_DATA_DATA_UPD_CRC:
397			`begin`
398			`next_CRCData <= SIEPortData;`
399			`next_CRC16En <= 1'b1;`
400			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
401			`end`
402			`PKT_ST_DATA_DATA_WAIT_BYTE:
403			`begin`
404			`next_SIEPortTxRdy <= 1'b1;`
405			`if (SIEPortWEn == 1'b1)`
406			`begin`
407			NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
408			`next_SIEPortData <= SIEPortDataIn;`
409			`next_SIEPortCtrl <= SIEPortCtrlIn;`
410			`next_SIEPortTxRdy <= 1'b0;`
411			`end`
412			`end`
413			`PKT_ST_DATA_DATA_WAIT_RDY:
414			`begin`
415			`next_CRC16En <= 1'b0;`
416			`if (processTxByteRdy == 1'b1)`
417			`begin`
418			NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
419			`next_processTxByteWEn <= 1'b1;`
420			`next_TxByteOut <= SIEPortData;`
421			next_TxByteOutCtrl <= `DATA_STREAM;
422			`end`
423			`end`
424			`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
425			`begin`
426			`if (CRC16UpdateRdy == 1'b1)`
427			`begin`
428			NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
429			`end`
430			`end`
431			`PKT_ST_DATA_PID_PKT_SENT:
432			`begin`
433			`next_processTxByteWEn <= 1'b0;`
434			`next_rstCRC <= 1'b0;`
435			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
436			`end`
437			`PKT_ST_DATA_PID_WAIT_RDY:
438			`begin`
439			`if (processTxByteRdy == 1'b1)`
440			`begin`
441			NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
442			`next_processTxByteWEn <= 1'b1;`
443			`next_TxByteOut <= SIEPortData;`
444			next_TxByteOutCtrl <= `DATA_STREAM;
445			`next_rstCRC <= 1'b1;`
446			`end`
447			`end`
448			`PKT_ST_HS_PKT_SENT:
449			`begin`
450			`next_processTxByteWEn <= 1'b0;`
451			NextState_SIETx <= `STX_WAIT_BYTE;
452			`end`
453			`PKT_ST_HS_WAIT_RDY:
454			`begin`
455			`if (processTxByteRdy == 1'b1)`
456			`begin`
457			NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
458			`next_processTxByteWEn <= 1'b1;`
459			`next_TxByteOut <= SIEPortData;`
460			next_TxByteOutCtrl <= `DATA_STOP;
461			`end`
462			`end`
463			`PKT_ST_SPCL_PKT_SENT:
464			`begin`
465			`next_processTxByteWEn <= 1'b0;`
466			NextState_SIETx <= `STX_WAIT_BYTE;
467			`end`
468			`PKT_ST_SPCL_WAIT_RDY:
469			`begin`
470			`if (processTxByteRdy == 1'b1)`
471			`begin`
472			NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
473			`next_processTxByteWEn <= 1'b1;`
474			`next_TxByteOut <= SIEPortData;`
475			next_TxByteOutCtrl <= `DATA_STOP;
476			`end`
477			`end`
478			`PKT_ST_TKN_BYTE1_PKT_SENT1:
479			`begin`
480			`next_processTxByteWEn <= 1'b0;`
481			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
482			`end`
483			`PKT_ST_TKN_BYTE1_UPD_CRC:
484			`begin`
485			`next_CRCData <= SIEPortData;`
486			`next_CRC5_8Bit <= 1'b1;`
487			`next_CRC5En <= 1'b1;`
488			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
489			`end`
490			`PKT_ST_TKN_BYTE1_WAIT_BYTE:
491			`begin`
492			`next_SIEPortTxRdy <= 1'b1;`
493			`if (SIEPortWEn == 1'b1)`
494			`begin`
495			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
496			`next_SIEPortData <= SIEPortDataIn;`
497			`next_SIEPortCtrl <= SIEPortCtrlIn;`
498			`next_SIEPortTxRdy <= 1'b0;`
499			`end`
500			`end`

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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [SIETransmitter.v] - Blame information for rev 14