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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [SIETransmitter.v] - Blame information for rev 43

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// File        : ../RTL/serialInterfaceEngine/SIETransmitter.v
// Generated   : 10/15/06 20:31:22
// From        : ../RTL/serialInterfaceEngine/SIETransmitter.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// SIETransmitter
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
 
module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);
input   [15:0] CRC16Result;
input   CRC16UpdateRdy;
input   [4:0] CRC5Result;
input   CRC5UpdateRdy;
input   [1:0] JBit;
input   [1:0] KBit;
input   [7:0] SIEPortCtrlIn;
input   [7:0] SIEPortDataIn;
input   SIEPortWEn;
input   USBWireGnt;
input   USBWireRdy;
input   clk;
input   fullSpeedRateIn;
input   processTxByteRdy;
input   rst;
output  CRC16En;
output  CRC5En;
output  CRC5_8Bit;
output  [7:0] CRCData;
output  SIEPortTxRdy;
output  [7:0] TxByteOutCtrl;
output  TxByteOutFullSpeedRate;
output  [7:0] TxByteOut;
output  USBWireCtrl;
output  [1:0] USBWireData;
output  USBWireFullSpeedRate;
output  USBWireReq;
output  USBWireWEn;
output  processTxByteWEn;
output  rstCRC;
 
reg     CRC16En, next_CRC16En;
wire    [15:0] CRC16Result;
wire    CRC16UpdateRdy;
reg     CRC5En, next_CRC5En;
wire    [4:0] CRC5Result;
wire    CRC5UpdateRdy;
reg     CRC5_8Bit, next_CRC5_8Bit;
reg     [7:0] CRCData, next_CRCData;
wire    [1:0] JBit;
wire    [1:0] KBit;
wire    [7:0] SIEPortCtrlIn;
wire    [7:0] SIEPortDataIn;
reg     SIEPortTxRdy, next_SIEPortTxRdy;
wire    SIEPortWEn;
reg     [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
reg     TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
reg     [7:0] TxByteOut, next_TxByteOut;
reg     USBWireCtrl, next_USBWireCtrl;
reg     [1:0] USBWireData, next_USBWireData;
reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire    USBWireGnt;
wire    USBWireRdy;
reg     USBWireReq, next_USBWireReq;
reg     USBWireWEn, next_USBWireWEn;
wire    clk;
wire    fullSpeedRateIn;
wire    processTxByteRdy;
reg     processTxByteWEn, next_processTxByteWEn;
wire    rst;
reg     rstCRC, next_rstCRC;
 
// diagram signals declarations
reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
reg  [7:0]SIEPortData, next_SIEPortData;
reg  [2:0]i, next_i;
reg  [15:0]resumeCnt, next_resumeCnt;
 
// BINARY ENCODED state machine: SIETx
// State codes definitions:
`define DIR_CTL_CHK_FIN 6'b000000
`define RES_ST_CHK_FIN 6'b000001
`define PKT_ST_CHK_PID 6'b000010
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
`define IDLE 6'b000100
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
`define PKT_ST_HS_PKT_SENT 6'b000111
`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
`define PKT_ST_SPCL_PKT_SENT 6'b001010
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
`define RES_ST_SND_J_1 6'b001110
`define RES_ST_SND_J_2 6'b001111
`define RES_ST_SND_SE0_1 6'b010000
`define RES_ST_SND_SE0_2 6'b010001
`define START_SIETX 6'b010010
`define STX_CHK_ST 6'b010011
`define STX_WAIT_BYTE 6'b010100
`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010
`define DIR_CTL_WAIT_GNT 6'b011011
`define RES_ST_WAIT_GNT 6'b011100
`define PKT_ST_HS_WAIT_RDY 6'b011101
`define DIR_CTL_WAIT_RDY 6'b011110
`define PKT_ST_SPCL_WAIT_RDY 6'b011111
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100010
`define RES_ST_WAIT_RDY 6'b100011
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
`define PKT_ST_WAIT_RDY_PKT 6'b101000
`define RES_ST_W_RDY1 6'b101001
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
`define TX_LS_EOP_WAIT_GNT1 6'b101101
`define TX_LS_EOP_SND_SE0_2 6'b101110
`define TX_LS_EOP_SND_SE0_1 6'b101111
`define TX_LS_EOP_W_RDY1 6'b110000
`define TX_LS_EOP_SND_J 6'b110001
`define TX_LS_EOP_W_RDY2 6'b110010
`define TX_LS_EOP_W_RDY3 6'b110011
`define RES_ST_DELAY 6'b110100
`define RES_ST_W_RDY2 6'b110101
`define RES_ST_W_RDY3 6'b110110
`define RES_ST_W_RDY4 6'b110111
`define DIR_CTL_DELAY 6'b111000
 
reg [5:0] CurrState_SIETx;
reg [5:0] NextState_SIETx;
 
 
//--------------------------------------------------------------------
// Machine: SIETx
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)
begin : SIETx_NextState
  NextState_SIETx <= CurrState_SIETx;
  // Set default values for outputs and signals
  next_processTxByteWEn <= processTxByteWEn;
  next_TxByteOut <= TxByteOut;
  next_TxByteOutCtrl <= TxByteOutCtrl;
  next_USBWireData <= USBWireData;
  next_USBWireCtrl <= USBWireCtrl;
  next_USBWireReq <= USBWireReq;
  next_USBWireWEn <= USBWireWEn;
  next_rstCRC <= rstCRC;
  next_CRCData <= CRCData;
  next_CRC5En <= CRC5En;
  next_CRC5_8Bit <= CRC5_8Bit;
  next_CRC16En <= CRC16En;
  next_SIEPortTxRdy <= SIEPortTxRdy;
  next_SIEPortData <= SIEPortData;
  next_SIEPortCtrl <= SIEPortCtrl;
  next_i <= i;
  next_resumeCnt <= resumeCnt;
  next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
  case (CurrState_SIETx)
    `IDLE:
      NextState_SIETx <= `STX_WAIT_BYTE;
    `START_SIETX:
    begin
      next_processTxByteWEn <= 1'b0;
      next_TxByteOut <= 8'h00;
      next_TxByteOutCtrl <= 8'h00;
      next_USBWireData <= 2'b00;
      next_USBWireCtrl <= `TRI_STATE;
      next_USBWireReq <= 1'b0;
      next_USBWireWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      next_CRCData <= 8'h00;
      next_CRC5En <= 1'b0;
      next_CRC5_8Bit <= 1'b0;
      next_CRC16En <= 1'b0;
      next_SIEPortTxRdy <= 1'b0;
      next_SIEPortData <= 8'h00;
      next_SIEPortCtrl <= 8'h00;
      next_i <= 3'h0;
      next_resumeCnt <= 16'h0000;
      next_TxByteOutFullSpeedRate <= 1'b0;
      next_USBWireFullSpeedRate <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `STX_CHK_ST:
      if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
      begin
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
        next_TxByteOutFullSpeedRate <= 1'b1;
        //SOF and PRE always at full speed
      end
      else if (SIEPortCtrl == `TX_PACKET_START)
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
      else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
      begin
        NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
        next_USBWireReq <= 1'b1;
      end
      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
      begin
        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
        next_USBWireReq <= 1'b1;
      end
      else if (SIEPortCtrl == `TX_IDLE)
        NextState_SIETx <= `IDLE;
      else if (SIEPortCtrl == `TX_RESUME_START)
      begin
        NextState_SIETx <= `RES_ST_WAIT_GNT;
        next_USBWireReq <= 1'b1;
        next_resumeCnt <= 16'h0000;
        next_USBWireFullSpeedRate <= 1'b0;
        //resume always uses low speed timing
      end
    `STX_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `STX_CHK_ST;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
        next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
        next_USBWireFullSpeedRate <= fullSpeedRateIn;
      end
    end
    `DIR_CTL_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      next_i <= i + 1'b1;
      if (i == 3'h7)
      begin
        NextState_SIETx <= `STX_WAIT_BYTE;
        next_USBWireReq <= 1'b0;
      end
      else
        NextState_SIETx <= `DIR_CTL_DELAY;
    end
    `DIR_CTL_WAIT_GNT:
    begin
      next_i <= 3'h0;
      if (USBWireGnt == 1'b1)
        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
    end
    `DIR_CTL_WAIT_RDY:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `DIR_CTL_CHK_FIN;
        next_USBWireData <= SIEPortData[1:0];
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    `DIR_CTL_DELAY:
      NextState_SIETx <= `DIR_CTL_WAIT_RDY;
    `PKT_ST_CHK_PID:
    begin
      next_processTxByteWEn <= 1'b0;
      if (SIEPortData[1:0] == `TOKEN)
        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
      else if (SIEPortData[1:0] == `HANDSHAKE)
        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
      else if (SIEPortData[1:0] == `DATA)
        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
      else if (SIEPortData[1:0] == `SPECIAL)
        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
    end
    `PKT_ST_WAIT_RDY_PKT:
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_CHK_PID;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= `SYNC_BYTE;
        next_TxByteOutCtrl <= `DATA_START;
      end
    `PKT_ST_DATA_CRC_PKT_SENT1:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
    end
    `PKT_ST_DATA_CRC_PKT_SENT2:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_DATA_CRC_WAIT_RDY1:
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= ~CRC16Result[7:0];
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    `PKT_ST_DATA_CRC_WAIT_RDY2:
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= ~CRC16Result[15:8];
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    `PKT_ST_DATA_DATA_CHK_STOP:
      if (SIEPortCtrl == `TX_PACKET_STOP)
        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
      else
        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
    `PKT_ST_DATA_DATA_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
    end
    `PKT_ST_DATA_DATA_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC16En <= 1'b1;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
    end
    `PKT_ST_DATA_DATA_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_DATA_DATA_WAIT_RDY:
    begin
      next_CRC16En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    end
    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
      if (CRC16UpdateRdy == 1'b1)
        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
    `PKT_ST_DATA_PID_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
    end
    `PKT_ST_DATA_PID_WAIT_RDY:
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
        next_rstCRC <= 1'b1;
      end
    `PKT_ST_HS_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_HS_WAIT_RDY:
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    `PKT_ST_SPCL_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_SPCL_WAIT_RDY:
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        if (SIEPortData[3:0] == `PREAMBLE)
          next_TxByteOutCtrl <= `DATA_STOP_PRE;
        else
          next_TxByteOutCtrl <= `DATA_STOP;
      end
    `PKT_ST_TKN_BYTE1_PKT_SENT1:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
    end
    `PKT_ST_TKN_BYTE1_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC5_8Bit <= 1'b1;
      next_CRC5En <= 1'b1;
      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
    end
    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_TKN_BYTE1_WAIT_RDY:
    begin
      next_CRC5En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    end
    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
      if (CRC5UpdateRdy == 1'b1)
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
    `PKT_ST_TKN_CRC_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_TKN_CRC_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC5_8Bit <= 1'b0;
      next_CRC5En <= 1'b1;
      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
    end
    `PKT_ST_TKN_CRC_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_TKN_CRC_WAIT_RDY:
    begin
      next_CRC5En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
      if (CRC5UpdateRdy == 1'b1)
        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
    `PKT_ST_TKN_PID_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
    end
    `PKT_ST_TKN_PID_WAIT_RDY:
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
        next_rstCRC <= 1'b1;
      end
    `RES_ST_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      if (resumeCnt == `HOST_TX_RESUME_TIME)
        NextState_SIETx <= `RES_ST_W_RDY1;
      else
        NextState_SIETx <= `RES_ST_DELAY;
    end
    `RES_ST_SND_J_1:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `RES_ST_W_RDY4;
    end
    `RES_ST_SND_J_2:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
      next_USBWireFullSpeedRate <= fullSpeedRateIn;
    end
    `RES_ST_SND_SE0_1:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `RES_ST_W_RDY2;
    end
    `RES_ST_SND_SE0_2:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `RES_ST_W_RDY3;
    end
    `RES_ST_WAIT_GNT:
      if (USBWireGnt == 1'b1)
        NextState_SIETx <= `RES_ST_WAIT_RDY;
    `RES_ST_WAIT_RDY:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_CHK_FIN;
        next_USBWireData <= KBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
        next_resumeCnt <= resumeCnt  + 1'b1;
      end
    `RES_ST_W_RDY1:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_SND_SE0_1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    `RES_ST_DELAY:
      NextState_SIETx <= `RES_ST_WAIT_RDY;
    `RES_ST_W_RDY2:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_SND_SE0_2;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    `RES_ST_W_RDY3:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_SND_J_1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    `RES_ST_W_RDY4:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_SND_J_2;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
        next_USBWireWEn <= 1'b1;
      end
    `TX_LS_EOP_WAIT_GNT1:
      if (USBWireGnt == 1'b1)
        NextState_SIETx <= `TX_LS_EOP_W_RDY1;
    `TX_LS_EOP_SND_SE0_2:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `TX_LS_EOP_W_RDY3;
    end
    `TX_LS_EOP_SND_SE0_1:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `TX_LS_EOP_W_RDY2;
    end
    `TX_LS_EOP_W_RDY1:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    `TX_LS_EOP_SND_J:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `TX_LS_EOP_W_RDY2:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    `TX_LS_EOP_W_RDY3:
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `TX_LS_EOP_SND_J;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SIETx_CurrentState
  if (rst)
    CurrState_SIETx <= `START_SIETX;
  else
    CurrState_SIETx <= NextState_SIETx;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SIETx_RegOutput
  if (rst)
  begin
    SIEPortData <= 8'h00;
    SIEPortCtrl <= 8'h00;
    i <= 3'h0;
    resumeCnt <= 16'h0000;
    processTxByteWEn <= 1'b0;
    TxByteOut <= 8'h00;
    TxByteOutCtrl <= 8'h00;
    USBWireData <= 2'b00;
    USBWireCtrl <= `TRI_STATE;
    USBWireReq <= 1'b0;
    USBWireWEn <= 1'b0;
    rstCRC <= 1'b0;
    CRCData <= 8'h00;
    CRC5En <= 1'b0;
    CRC5_8Bit <= 1'b0;
    CRC16En <= 1'b0;
    SIEPortTxRdy <= 1'b0;
    TxByteOutFullSpeedRate <= 1'b0;
    USBWireFullSpeedRate <= 1'b0;
  end
  else
  begin
    SIEPortData <= next_SIEPortData;
    SIEPortCtrl <= next_SIEPortCtrl;
    i <= next_i;
    resumeCnt <= next_resumeCnt;
    processTxByteWEn <= next_processTxByteWEn;
    TxByteOut <= next_TxByteOut;
    TxByteOutCtrl <= next_TxByteOutCtrl;
    USBWireData <= next_USBWireData;
    USBWireCtrl <= next_USBWireCtrl;
    USBWireReq <= next_USBWireReq;
    USBWireWEn <= next_USBWireWEn;
    rstCRC <= next_rstCRC;
    CRCData <= next_CRCData;
    CRC5En <= next_CRC5En;
    CRC5_8Bit <= next_CRC5_8Bit;
    CRC16En <= next_CRC16En;
    SIEPortTxRdy <= next_SIEPortTxRdy;
    TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	43	sfielding
2			`// File : ../RTL/serialInterfaceEngine/SIETransmitter.v`
3	34	sfielding	`// Generated : 10/15/06 20:31:22`
4	43	sfielding	`// From : ../RTL/serialInterfaceEngine/SIETransmitter.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// SIETransmitter`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbSerialInterfaceEngine_h.v"
52			`include "usbConstants_h.v"
53
54
55			`module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);`
56			`input [15:0] CRC16Result;`
57			`input CRC16UpdateRdy;`
58			`input [4:0] CRC5Result;`
59			`input CRC5UpdateRdy;`
60			`input [1:0] JBit;`
61			`input [1:0] KBit;`
62			`input [7:0] SIEPortCtrlIn;`
63			`input [7:0] SIEPortDataIn;`
64			`input SIEPortWEn;`
65			`input USBWireGnt;`
66			`input USBWireRdy;`
67			`input clk;`
68			`input fullSpeedRateIn;`
69			`input processTxByteRdy;`
70			`input rst;`
71			`output CRC16En;`
72			`output CRC5En;`
73			`output CRC5_8Bit;`
74			`output [7:0] CRCData;`
75			`output SIEPortTxRdy;`
76			`output [7:0] TxByteOutCtrl;`
77			`output TxByteOutFullSpeedRate;`
78			`output [7:0] TxByteOut;`
79			`output USBWireCtrl;`
80			`output [1:0] USBWireData;`
81			`output USBWireFullSpeedRate;`
82			`output USBWireReq;`
83			`output USBWireWEn;`
84			`output processTxByteWEn;`
85			`output rstCRC;`
86
87			`reg CRC16En, next_CRC16En;`
88			`wire [15:0] CRC16Result;`
89			`wire CRC16UpdateRdy;`
90			`reg CRC5En, next_CRC5En;`
91			`wire [4:0] CRC5Result;`
92			`wire CRC5UpdateRdy;`
93			`reg CRC5_8Bit, next_CRC5_8Bit;`
94			`reg [7:0] CRCData, next_CRCData;`
95			`wire [1:0] JBit;`
96			`wire [1:0] KBit;`
97			`wire [7:0] SIEPortCtrlIn;`
98			`wire [7:0] SIEPortDataIn;`
99			`reg SIEPortTxRdy, next_SIEPortTxRdy;`
100			`wire SIEPortWEn;`
101			`reg [7:0] TxByteOutCtrl, next_TxByteOutCtrl;`
102			`reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;`
103			`reg [7:0] TxByteOut, next_TxByteOut;`
104			`reg USBWireCtrl, next_USBWireCtrl;`
105			`reg [1:0] USBWireData, next_USBWireData;`
106			`reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;`
107			`wire USBWireGnt;`
108			`wire USBWireRdy;`
109			`reg USBWireReq, next_USBWireReq;`
110			`reg USBWireWEn, next_USBWireWEn;`
111			`wire clk;`
112			`wire fullSpeedRateIn;`
113			`wire processTxByteRdy;`
114			`reg processTxByteWEn, next_processTxByteWEn;`
115			`wire rst;`
116			`reg rstCRC, next_rstCRC;`
117
118			`// diagram signals declarations`
119			`reg [7:0]SIEPortCtrl, next_SIEPortCtrl;`
120			`reg [7:0]SIEPortData, next_SIEPortData;`
121			`reg [2:0]i, next_i;`
122			`reg [15:0]resumeCnt, next_resumeCnt;`
123
124			`// BINARY ENCODED state machine: SIETx`
125			`// State codes definitions:`
126			`define DIR_CTL_CHK_FIN 6'b000000
127			`define RES_ST_CHK_FIN 6'b000001
128			`define PKT_ST_CHK_PID 6'b000010
129			`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
130			`define IDLE 6'b000100
131	14	sfielding	`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
132			`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
133			`define PKT_ST_HS_PKT_SENT 6'b000111
134	43	sfielding	`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
135	14	sfielding	`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
136			`define PKT_ST_SPCL_PKT_SENT 6'b001010
137	43	sfielding	`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
138			`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
139			`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
140			`define RES_ST_SND_J_1 6'b001110
141			`define RES_ST_SND_J_2 6'b001111
142			`define RES_ST_SND_SE0_1 6'b010000
143			`define RES_ST_SND_SE0_2 6'b010001
144			`define START_SIETX 6'b010010
145			`define STX_CHK_ST 6'b010011
146			`define STX_WAIT_BYTE 6'b010100
147	14	sfielding	`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
148			`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
149			`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
150	43	sfielding	`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
151	22	sfielding	`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001
152			`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010
153			`define DIR_CTL_WAIT_GNT 6'b011011
154	14	sfielding	`define RES_ST_WAIT_GNT 6'b011100
155	22	sfielding	`define PKT_ST_HS_WAIT_RDY 6'b011101
156			`define DIR_CTL_WAIT_RDY 6'b011110
157	14	sfielding	`define PKT_ST_SPCL_WAIT_RDY 6'b011111
158			`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
159	9	sfielding	`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
160	22	sfielding	`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100010
161	14	sfielding	`define RES_ST_WAIT_RDY 6'b100011
162			`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
163	22	sfielding	`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101
164	43	sfielding	`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
165			`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
166			`define PKT_ST_WAIT_RDY_PKT 6'b101000
167			`define RES_ST_W_RDY1 6'b101001
168			`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
169			`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
170			`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
171			`define TX_LS_EOP_WAIT_GNT1 6'b101101
172			`define TX_LS_EOP_SND_SE0_2 6'b101110
173			`define TX_LS_EOP_SND_SE0_1 6'b101111
174			`define TX_LS_EOP_W_RDY1 6'b110000
175			`define TX_LS_EOP_SND_J 6'b110001
176			`define TX_LS_EOP_W_RDY2 6'b110010
177			`define TX_LS_EOP_W_RDY3 6'b110011
178			`define RES_ST_DELAY 6'b110100
179			`define RES_ST_W_RDY2 6'b110101
180			`define RES_ST_W_RDY3 6'b110110
181			`define RES_ST_W_RDY4 6'b110111
182			`define DIR_CTL_DELAY 6'b111000
183
184			`reg [5:0] CurrState_SIETx;`
185			`reg [5:0] NextState_SIETx;`
186
187
188			`//--------------------------------------------------------------------`
189			`// Machine: SIETx`
190			`//--------------------------------------------------------------------`
191			`//----------------------------------`
192			`// Next State Logic (combinatorial)`
193			`//----------------------------------`
194			`always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)`
195			`begin : SIETx_NextState`
196			`NextState_SIETx <= CurrState_SIETx;`
197			`// Set default values for outputs and signals`
198			`next_processTxByteWEn <= processTxByteWEn;`
199			`next_TxByteOut <= TxByteOut;`
200			`next_TxByteOutCtrl <= TxByteOutCtrl;`
201			`next_USBWireData <= USBWireData;`
202			`next_USBWireCtrl <= USBWireCtrl;`
203			`next_USBWireReq <= USBWireReq;`
204			`next_USBWireWEn <= USBWireWEn;`
205			`next_rstCRC <= rstCRC;`
206			`next_CRCData <= CRCData;`
207			`next_CRC5En <= CRC5En;`
208			`next_CRC5_8Bit <= CRC5_8Bit;`
209			`next_CRC16En <= CRC16En;`
210			`next_SIEPortTxRdy <= SIEPortTxRdy;`
211			`next_SIEPortData <= SIEPortData;`
212			`next_SIEPortCtrl <= SIEPortCtrl;`
213			`next_i <= i;`
214			`next_resumeCnt <= resumeCnt;`
215			`next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;`
216			`next_USBWireFullSpeedRate <= USBWireFullSpeedRate;`
217			`case (CurrState_SIETx)`
218			`IDLE:
219			NextState_SIETx <= `STX_WAIT_BYTE;
220			`START_SIETX:
221			`begin`
222			`next_processTxByteWEn <= 1'b0;`
223			`next_TxByteOut <= 8'h00;`
224			`next_TxByteOutCtrl <= 8'h00;`
225			`next_USBWireData <= 2'b00;`
226			next_USBWireCtrl <= `TRI_STATE;
227			`next_USBWireReq <= 1'b0;`
228			`next_USBWireWEn <= 1'b0;`
229			`next_rstCRC <= 1'b0;`
230			`next_CRCData <= 8'h00;`
231			`next_CRC5En <= 1'b0;`
232			`next_CRC5_8Bit <= 1'b0;`
233			`next_CRC16En <= 1'b0;`
234			`next_SIEPortTxRdy <= 1'b0;`
235			`next_SIEPortData <= 8'h00;`
236			`next_SIEPortCtrl <= 8'h00;`
237			`next_i <= 3'h0;`
238			`next_resumeCnt <= 16'h0000;`
239			`next_TxByteOutFullSpeedRate <= 1'b0;`
240			`next_USBWireFullSpeedRate <= 1'b0;`
241			NextState_SIETx <= `STX_WAIT_BYTE;
242			`end`
243			`STX_CHK_ST:
244			if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF \|\| SIEPortData[3:0] == `PREAMBLE))
245			`begin`
246			NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
247			`next_TxByteOutFullSpeedRate <= 1'b1;`
248			`//SOF and PRE always at full speed`
249			`end`
250			else if (SIEPortCtrl == `TX_PACKET_START)
251			NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
252			else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
253			`begin`
254			NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
255			`next_USBWireReq <= 1'b1;`
256			`end`
257			else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
258			`begin`
259			NextState_SIETx <= `DIR_CTL_WAIT_GNT;
260			`next_USBWireReq <= 1'b1;`
261			`end`
262	34	sfielding	else if (SIEPortCtrl == `TX_IDLE)
263			NextState_SIETx <= `IDLE;
264	43	sfielding	else if (SIEPortCtrl == `TX_RESUME_START)
265			`begin`
266			NextState_SIETx <= `RES_ST_WAIT_GNT;
267			`next_USBWireReq <= 1'b1;`
268			`next_resumeCnt <= 16'h0000;`
269			`next_USBWireFullSpeedRate <= 1'b0;`
270			`//resume always uses low speed timing`
271			`end`
272			`STX_WAIT_BYTE:
273			`begin`
274			`next_SIEPortTxRdy <= 1'b1;`
275			`if (SIEPortWEn == 1'b1)`
276			`begin`
277			NextState_SIETx <= `STX_CHK_ST;
278			`next_SIEPortData <= SIEPortDataIn;`
279			`next_SIEPortCtrl <= SIEPortCtrlIn;`
280			`next_SIEPortTxRdy <= 1'b0;`
281			`next_TxByteOutFullSpeedRate <= fullSpeedRateIn;`
282			`next_USBWireFullSpeedRate <= fullSpeedRateIn;`
283			`end`
284			`end`
285			`DIR_CTL_CHK_FIN:
286			`begin`
287			`next_USBWireWEn <= 1'b0;`
288			`next_i <= i + 1'b1;`
289			`if (i == 3'h7)`
290			`begin`
291			NextState_SIETx <= `STX_WAIT_BYTE;
292			`next_USBWireReq <= 1'b0;`
293			`end`
294			`else`
295			NextState_SIETx <= `DIR_CTL_DELAY;
296			`end`
297			`DIR_CTL_WAIT_GNT:
298			`begin`
299			`next_i <= 3'h0;`
300			`if (USBWireGnt == 1'b1)`
301			NextState_SIETx <= `DIR_CTL_WAIT_RDY;
302			`end`
303			`DIR_CTL_WAIT_RDY:
304			`if (USBWireRdy == 1'b1)`
305			`begin`
306			NextState_SIETx <= `DIR_CTL_CHK_FIN;
307			`next_USBWireData <= SIEPortData[1:0];`
308			next_USBWireCtrl <= `DRIVE;
309			`next_USBWireWEn <= 1'b1;`
310			`end`
311			`DIR_CTL_DELAY:
312			NextState_SIETx <= `DIR_CTL_WAIT_RDY;
313			`PKT_ST_CHK_PID:
314			`begin`
315			`next_processTxByteWEn <= 1'b0;`
316	34	sfielding	if (SIEPortData[1:0] == `TOKEN)
317			NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
318			else if (SIEPortData[1:0] == `HANDSHAKE)
319	43	sfielding	NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
320	34	sfielding	else if (SIEPortData[1:0] == `DATA)
321			NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
322	43	sfielding	else if (SIEPortData[1:0] == `SPECIAL)
323			NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
324			`end`
325			`PKT_ST_WAIT_RDY_PKT:
326			`if (processTxByteRdy == 1'b1)`
327			`begin`
328			NextState_SIETx <= `PKT_ST_CHK_PID;
329			`next_processTxByteWEn <= 1'b1;`
330			next_TxByteOut <= `SYNC_BYTE;
331			next_TxByteOutCtrl <= `DATA_START;
332			`end`
333			`PKT_ST_DATA_CRC_PKT_SENT1:
334			`begin`
335			`next_processTxByteWEn <= 1'b0;`
336			NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
337			`end`
338			`PKT_ST_DATA_CRC_PKT_SENT2:
339			`begin`
340			`next_processTxByteWEn <= 1'b0;`
341			NextState_SIETx <= `STX_WAIT_BYTE;
342			`end`
343			`PKT_ST_DATA_CRC_WAIT_RDY1:
344			`if (processTxByteRdy == 1'b1)`
345			`begin`
346			NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
347			`next_processTxByteWEn <= 1'b1;`
348			`next_TxByteOut <= ~CRC16Result[7:0];`
349			next_TxByteOutCtrl <= `DATA_STREAM;
350			`end`
351			`PKT_ST_DATA_CRC_WAIT_RDY2:
352			`if (processTxByteRdy == 1'b1)`
353			`begin`
354			NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
355			`next_processTxByteWEn <= 1'b1;`
356			`next_TxByteOut <= ~CRC16Result[15:8];`
357			next_TxByteOutCtrl <= `DATA_STOP;
358			`end`
359			`PKT_ST_DATA_DATA_CHK_STOP:
360			if (SIEPortCtrl == `TX_PACKET_STOP)
361			NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
362			`else`
363			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
364			`PKT_ST_DATA_DATA_PKT_SENT:
365			`begin`
366			`next_processTxByteWEn <= 1'b0;`
367			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
368			`end`
369			`PKT_ST_DATA_DATA_UPD_CRC:
370			`begin`
371			`next_CRCData <= SIEPortData;`
372			`next_CRC16En <= 1'b1;`
373			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
374			`end`
375			`PKT_ST_DATA_DATA_WAIT_BYTE:
376			`begin`
377			`next_SIEPortTxRdy <= 1'b1;`
378			`if (SIEPortWEn == 1'b1)`
379			`begin`
380			NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
381			`next_SIEPortData <= SIEPortDataIn;`
382			`next_SIEPortCtrl <= SIEPortCtrlIn;`
383			`next_SIEPortTxRdy <= 1'b0;`
384			`end`
385			`end`
386			`PKT_ST_DATA_DATA_WAIT_RDY:
387			`begin`
388			`next_CRC16En <= 1'b0;`
389			`if (processTxByteRdy == 1'b1)`
390			`begin`
391			NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
392			`next_processTxByteWEn <= 1'b1;`
393			`next_TxByteOut <= SIEPortData;`
394			next_TxByteOutCtrl <= `DATA_STREAM;
395			`end`
396			`end`
397			`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
398			`if (CRC16UpdateRdy == 1'b1)`
399			NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
400			`PKT_ST_DATA_PID_PKT_SENT:
401			`begin`
402			`next_processTxByteWEn <= 1'b0;`
403			`next_rstCRC <= 1'b0;`
404			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
405			`end`
406			`PKT_ST_DATA_PID_WAIT_RDY:
407			`if (processTxByteRdy == 1'b1)`
408			`begin`
409			NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
410			`next_processTxByteWEn <= 1'b1;`
411			`next_TxByteOut <= SIEPortData;`
412			next_TxByteOutCtrl <= `DATA_STREAM;
413			`next_rstCRC <= 1'b1;`
414			`end`
415			`PKT_ST_HS_PKT_SENT:
416			`begin`
417			`next_processTxByteWEn <= 1'b0;`
418			NextState_SIETx <= `STX_WAIT_BYTE;
419			`end`
420			`PKT_ST_HS_WAIT_RDY:
421			`if (processTxByteRdy == 1'b1)`
422			`begin`
423			NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
424			`next_processTxByteWEn <= 1'b1;`
425			`next_TxByteOut <= SIEPortData;`
426			next_TxByteOutCtrl <= `DATA_STOP;
427			`end`
428			`PKT_ST_SPCL_PKT_SENT:
429			`begin`
430			`next_processTxByteWEn <= 1'b0;`
431			NextState_SIETx <= `STX_WAIT_BYTE;
432			`end`
433			`PKT_ST_SPCL_WAIT_RDY:
434			`if (processTxByteRdy == 1'b1)`
435			`begin`
436			NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
437			`next_processTxByteWEn <= 1'b1;`
438			`next_TxByteOut <= SIEPortData;`
439			if (SIEPortData[3:0] == `PREAMBLE)
440			next_TxByteOutCtrl <= `DATA_STOP_PRE;
441			`else`
442			next_TxByteOutCtrl <= `DATA_STOP;
443			`end`
444			`PKT_ST_TKN_BYTE1_PKT_SENT1:
445			`begin`
446			`next_processTxByteWEn <= 1'b0;`
447			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
448			`end`
449			`PKT_ST_TKN_BYTE1_UPD_CRC:
450			`begin`
451			`next_CRCData <= SIEPortData;`
452			`next_CRC5_8Bit <= 1'b1;`
453			`next_CRC5En <= 1'b1;`
454			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
455			`end`
456			`PKT_ST_TKN_BYTE1_WAIT_BYTE:
457			`begin`
458			`next_SIEPortTxRdy <= 1'b1;`
459			`if (SIEPortWEn == 1'b1)`
460			`begin`
461			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
462			`next_SIEPortData <= SIEPortDataIn;`
463			`next_SIEPortCtrl <= SIEPortCtrlIn;`
464			`next_SIEPortTxRdy <= 1'b0;`
465			`end`
466			`end`
467			`PKT_ST_TKN_BYTE1_WAIT_RDY:
468			`begin`
469			`next_CRC5En <= 1'b0;`
470			`if (processTxByteRdy == 1'b1)`
471			`begin`
472			NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
473			`next_processTxByteWEn <= 1'b1;`
474			`next_TxByteOut <= SIEPortData;`
475			next_TxByteOutCtrl <= `DATA_STREAM;
476			`end`
477			`end`
478			`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
479			`if (CRC5UpdateRdy == 1'b1)`
480			NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
481			`PKT_ST_TKN_CRC_PKT_SENT:
482			`begin`
483			`next_processTxByteWEn <= 1'b0;`
484			NextState_SIETx <= `STX_WAIT_BYTE;
485			`end`
486			`PKT_ST_TKN_CRC_UPD_CRC:
487			`begin`
488			`next_CRCData <= SIEPortData;`
489			`next_CRC5_8Bit <= 1'b0;`
490			`next_CRC5En <= 1'b1;`
491			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
492			`end`
493			`PKT_ST_TKN_CRC_WAIT_BYTE:
494			`begin`
495			`next_SIEPortTxRdy <= 1'b1;`
496			`if (SIEPortWEn == 1'b1)`
497			`begin`
498			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
499			`next_SIEPortData <= SIEPortDataIn;`
500			`next_SIEPortCtrl <= SIEPortCtrlIn;`

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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [SIETransmitter.v] - Blame information for rev 43