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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [SIETransmitter.v] - Blame information for rev 9

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// SIETransmitter
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
 
module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
input   clk;
input   [15:0]CRC16Result;
input   CRC16UpdateRdy;
input   [4:0]CRC5Result;
input   CRC5UpdateRdy;
input   [1:0]JBit;
input   [1:0]KBit;
input   processTxByteRdy;
input   rst;
input   [7:0]SIEPortCtrlIn;
input   [7:0]SIEPortDataIn;
input   SIEPortWEn;
input   USBWireGnt;
input   USBWireRdy;
output  CRC16En;
output  CRC5_8Bit;
output  CRC5En;
output  [7:0]CRCData;
output  processTxByteWEn;
output  rstCRC;
output  SIEPortTxRdy;
output  [7:0]TxByteOut;
output  [7:0]TxByteOutCtrl;
output  USBWireCtrl;
output  [1:0]USBWireData;
output  USBWireReq;
output  USBWireWEn;
 
wire    clk;
reg     CRC16En, next_CRC16En;
wire    [15:0]CRC16Result;
wire    CRC16UpdateRdy;
reg     CRC5_8Bit, next_CRC5_8Bit;
reg     CRC5En, next_CRC5En;
wire    [4:0]CRC5Result;
wire    CRC5UpdateRdy;
reg     [7:0]CRCData, next_CRCData;
wire    [1:0]JBit;
wire    [1:0]KBit;
wire    processTxByteRdy;
reg     processTxByteWEn, next_processTxByteWEn;
wire    rst;
reg     rstCRC, next_rstCRC;
wire    [7:0]SIEPortCtrlIn;
wire    [7:0]SIEPortDataIn;
reg     SIEPortTxRdy, next_SIEPortTxRdy;
wire    SIEPortWEn;
reg     [7:0]TxByteOut, next_TxByteOut;
reg     [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
reg     USBWireCtrl, next_USBWireCtrl;
reg     [1:0]USBWireData, next_USBWireData;
wire    USBWireGnt;
wire    USBWireRdy;
reg     USBWireReq, next_USBWireReq;
reg     USBWireWEn, next_USBWireWEn;
 
// diagram signals declarations
reg  [4:0]i, next_i;
reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
reg  [7:0]SIEPortData, next_SIEPortData;
 
// BINARY ENCODED state machine: SIETx
// State codes definitions:
`define RES_ST_CHK_FIN 6'b000000
`define DIR_CTL_CHK_FIN 6'b000001
`define PKT_ST_CHK_PID 6'b000010
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
`define IDLE 6'b000100
`define PKT_ST_TKN_CRC_PKT_SENT 6'b000101
`define PKT_ST_HS_PKT_SENT 6'b000110
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000111
`define PKT_ST_DATA_PID_PKT_SENT 6'b001000
`define PKT_ST_SPCL_PKT_SENT 6'b001001
`define PKT_ST_TKN_PID_PKT_SENT 6'b001010
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
`define RES_ST_S1 6'b001110
`define RES_ST_S3 6'b001111
`define RES_ST_S4 6'b010000
`define RES_ST_S5 6'b010001
`define RES_ST_S6 6'b010010
`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
`define START_SIETX 6'b010110
`define STX_CHK_ST 6'b010111
`define STX_WAIT_BYTE 6'b011000
`define PKT_ST_DATA_DATA_UPD_CRC 6'b011001
`define PKT_ST_TKN_CRC_UPD_CRC 6'b011010
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011011
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011100
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011101
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
`define RES_ST_WAIT_GNT 6'b011111
`define DIR_CTL_WAIT_GNT 6'b100000
`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
`define PKT_ST_SPCL_WAIT_RDY 6'b100011
`define PKT_ST_HS_WAIT_RDY 6'b100100
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100101
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100110
`define DIR_CTL_WAIT_RDY 6'b100111
`define RES_ST_WAIT_RDY 6'b101000
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b101001
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101010
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101011
`define PKT_ST_WAIT_RDY_PKT 6'b101100
`define PKT_ST_SPCL_WAIT_WIRE 6'b101101
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101110
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101111
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110000
 
reg [5:0]CurrState_SIETx, NextState_SIETx;
 
 
// Machine: SIETx
 
// NextState logic (combinatorial)
always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
begin
  NextState_SIETx <= CurrState_SIETx;
  // Set default values for outputs and signals
  next_USBWireWEn <= USBWireWEn;
  next_i <= i;
  next_USBWireReq <= USBWireReq;
  next_processTxByteWEn <= processTxByteWEn;
  next_rstCRC <= rstCRC;
  next_USBWireData <= USBWireData;
  next_USBWireCtrl <= USBWireCtrl;
  next_TxByteOut <= TxByteOut;
  next_TxByteOutCtrl <= TxByteOutCtrl;
  next_CRCData <= CRCData;
  next_CRC5En <= CRC5En;
  next_CRC5_8Bit <= CRC5_8Bit;
  next_CRC16En <= CRC16En;
  next_SIEPortTxRdy <= SIEPortTxRdy;
  next_SIEPortData <= SIEPortData;
  next_SIEPortCtrl <= SIEPortCtrl;
  case (CurrState_SIETx)  // synopsys parallel_case full_case
    `IDLE:
    begin
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `START_SIETX:
    begin
      next_processTxByteWEn <= 1'b0;
      next_TxByteOut <= 8'h00;
      next_TxByteOutCtrl <= 8'h00;
      next_USBWireData <= 2'b00;
      next_USBWireCtrl <= `TRI_STATE;
      next_USBWireReq <= 1'b0;
      next_USBWireWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      next_CRCData <= 8'h00;
      next_CRC5En <= 1'b0;
      next_CRC5_8Bit <= 1'b0;
      next_CRC16En <= 1'b0;
      next_SIEPortTxRdy <= 1'b0;
      next_SIEPortData <= 8'h00;
      next_SIEPortCtrl <= 8'h00;
      next_i <= 5'h0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `STX_CHK_ST:
    begin
      if (SIEPortCtrl == `TX_PACKET_START)
      begin
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
      end
      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
      begin
        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
        next_USBWireReq <= 1'b1;
      end
      else if (SIEPortCtrl == `TX_IDLE)
      begin
        NextState_SIETx <= `IDLE;
      end
      else if (SIEPortCtrl == `TX_RESUME_START)
      begin
        NextState_SIETx <= `RES_ST_WAIT_GNT;
        next_USBWireReq <= 1'b1;
        next_i <= 5'h0;
      end
    end
    `STX_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `STX_CHK_ST;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `DIR_CTL_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      next_i <= i + 1'b1;
      if (i == 5'h7)
      begin
        NextState_SIETx <= `STX_WAIT_BYTE;
        next_USBWireReq <= 1'b0;
      end
      else
      begin
        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
      end
    end
    `DIR_CTL_WAIT_GNT:
    begin
      next_i <= 5'h0;
      if (USBWireGnt == 1'b1)
      begin
        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
      end
    end
    `DIR_CTL_WAIT_RDY:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `DIR_CTL_CHK_FIN;
        next_USBWireData <= SIEPortData[1:0];
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `PKT_ST_CHK_PID:
    begin
      next_processTxByteWEn <= 1'b0;
      if (SIEPortData[1:0] == `TOKEN)
      begin
        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
      end
      else if (SIEPortData[1:0] == `HANDSHAKE)
      begin
        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
      end
      else if (SIEPortData[1:0] == `DATA)
      begin
        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
      end
      else if (SIEPortData[1:0] == `SPECIAL)
      begin
        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
      end
    end
    `PKT_ST_WAIT_RDY_PKT:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_CHK_PID;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= `SYNC_BYTE;
        next_TxByteOutCtrl <= `DATA_START;
      end
    end
    `PKT_ST_DATA_CRC_PKT_SENT1:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
    end
    `PKT_ST_DATA_CRC_PKT_SENT2:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_DATA_CRC_WAIT_RDY1:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= ~CRC16Result[7:0];
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    end
    `PKT_ST_DATA_CRC_WAIT_RDY2:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= ~CRC16Result[15:8];
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_DATA_DATA_CHK_STOP:
    begin
      if (SIEPortCtrl == `TX_PACKET_STOP)
      begin
        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
      end
      else
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
      end
    end
    `PKT_ST_DATA_DATA_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
    end
    `PKT_ST_DATA_DATA_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC16En <= 1'b1;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
    end
    `PKT_ST_DATA_DATA_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_DATA_DATA_WAIT_RDY:
    begin
      next_CRC16En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    end
    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
    begin
      if (CRC16UpdateRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
      end
    end
    `PKT_ST_DATA_PID_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
    end
    `PKT_ST_DATA_PID_WAIT_RDY:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
        next_rstCRC <= 1'b1;
      end
    end
    `PKT_ST_HS_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_HS_WAIT_RDY:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_SPCL_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
    end
    `PKT_ST_SPCL_SEND_IDLE1:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `PKT_ST_SPCL_SEND_IDLE2:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `PKT_ST_SPCL_SEND_IDLE3:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_SPCL_WAIT_RDY:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_SPCL_WAIT_WIRE:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `PKT_ST_TKN_BYTE1_PKT_SENT1:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
    end
    `PKT_ST_TKN_BYTE1_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC5_8Bit <= 1'b1;
      next_CRC5En <= 1'b1;
      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
    end
    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_TKN_BYTE1_WAIT_RDY:
    begin
      next_CRC5En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
      end
    end
    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
    begin
      if (CRC5UpdateRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
      end
    end
    `PKT_ST_TKN_CRC_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `PKT_ST_TKN_CRC_UPD_CRC:
    begin
      next_CRCData <= SIEPortData;
      next_CRC5_8Bit <= 1'b0;
      next_CRC5En <= 1'b1;
      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
    end
    `PKT_ST_TKN_CRC_WAIT_BYTE:
    begin
      next_SIEPortTxRdy <= 1'b1;
      if (SIEPortWEn == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
        next_SIEPortData <= SIEPortDataIn;
        next_SIEPortCtrl <= SIEPortCtrlIn;
        next_SIEPortTxRdy <= 1'b0;
      end
    end
    `PKT_ST_TKN_CRC_WAIT_RDY:
    begin
      next_CRC5En <= 1'b0;
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
        next_TxByteOutCtrl <= `DATA_STOP;
      end
    end
    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
    begin
      if (CRC5UpdateRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
      end
    end
    `PKT_ST_TKN_PID_PKT_SENT:
    begin
      next_processTxByteWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
    end
    `PKT_ST_TKN_PID_WAIT_RDY:
    begin
      if (processTxByteRdy == 1'b1)
      begin
        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= SIEPortData;
        next_TxByteOutCtrl <= `DATA_STREAM;
        next_rstCRC <= 1'b1;
      end
    end
    `RES_ST_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      if (i == `RESUME_LEN)
      begin
        NextState_SIETx <= `RES_ST_S1;
      end
      else
      begin
        NextState_SIETx <= `RES_ST_WAIT_RDY;
      end
    end
    `RES_ST_S1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_S3;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `RES_ST_S3:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_S4;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `RES_ST_S4:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_S5;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `RES_ST_S5:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_S6;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `RES_ST_S6:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      NextState_SIETx <= `STX_WAIT_BYTE;
    end
    `RES_ST_WAIT_GNT:
    begin
      if (USBWireGnt == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_WAIT_RDY;
      end
    end
    `RES_ST_WAIT_RDY:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_SIETx <= `RES_ST_CHK_FIN;
        next_USBWireData <= KBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
        next_i <= i + 1'b1;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_SIETx <= `START_SIETX;
  else
    CurrState_SIETx <= NextState_SIETx;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    USBWireWEn <= 1'b0;
    USBWireReq <= 1'b0;
    processTxByteWEn <= 1'b0;
    rstCRC <= 1'b0;
    USBWireData <= 2'b00;
    USBWireCtrl <= `TRI_STATE;
    TxByteOut <= 8'h00;
    TxByteOutCtrl <= 8'h00;
    CRCData <= 8'h00;
    CRC5En <= 1'b0;
    CRC5_8Bit <= 1'b0;
    CRC16En <= 1'b0;
    SIEPortTxRdy <= 1'b0;
    i <= 5'h0;
    SIEPortData <= 8'h00;
    SIEPortCtrl <= 8'h00;
  end
  else
  begin
    USBWireWEn <= next_USBWireWEn;
    USBWireReq <= next_USBWireReq;
    processTxByteWEn <= next_processTxByteWEn;
    rstCRC <= next_rstCRC;
    USBWireData <= next_USBWireData;
    USBWireCtrl <= next_USBWireCtrl;
    TxByteOut <= next_TxByteOut;
    TxByteOutCtrl <= next_TxByteOutCtrl;
    CRCData <= next_CRCData;
    CRC5En <= next_CRC5En;
    CRC5_8Bit <= next_CRC5_8Bit;
    CRC16En <= next_CRC16En;
    SIEPortTxRdy <= next_SIEPortTxRdy;
    i <= next_i;
    SIEPortData <= next_SIEPortData;
    SIEPortCtrl <= next_SIEPortCtrl;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// SIETransmitter`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbConstants_h.v"
48
49
50			`module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);`
51			`input clk;`
52			`input [15:0]CRC16Result;`
53			`input CRC16UpdateRdy;`
54			`input [4:0]CRC5Result;`
55			`input CRC5UpdateRdy;`
56			`input [1:0]JBit;`
57			`input [1:0]KBit;`
58			`input processTxByteRdy;`
59			`input rst;`
60			`input [7:0]SIEPortCtrlIn;`
61			`input [7:0]SIEPortDataIn;`
62			`input SIEPortWEn;`
63			`input USBWireGnt;`
64			`input USBWireRdy;`
65			`output CRC16En;`
66			`output CRC5_8Bit;`
67			`output CRC5En;`
68			`output [7:0]CRCData;`
69			`output processTxByteWEn;`
70			`output rstCRC;`
71			`output SIEPortTxRdy;`
72			`output [7:0]TxByteOut;`
73			`output [7:0]TxByteOutCtrl;`
74			`output USBWireCtrl;`
75			`output [1:0]USBWireData;`
76			`output USBWireReq;`
77			`output USBWireWEn;`
78
79			`wire clk;`
80			`reg CRC16En, next_CRC16En;`
81			`wire [15:0]CRC16Result;`
82			`wire CRC16UpdateRdy;`
83			`reg CRC5_8Bit, next_CRC5_8Bit;`
84			`reg CRC5En, next_CRC5En;`
85			`wire [4:0]CRC5Result;`
86			`wire CRC5UpdateRdy;`
87			`reg [7:0]CRCData, next_CRCData;`
88			`wire [1:0]JBit;`
89			`wire [1:0]KBit;`
90			`wire processTxByteRdy;`
91			`reg processTxByteWEn, next_processTxByteWEn;`
92			`wire rst;`
93			`reg rstCRC, next_rstCRC;`
94			`wire [7:0]SIEPortCtrlIn;`
95			`wire [7:0]SIEPortDataIn;`
96			`reg SIEPortTxRdy, next_SIEPortTxRdy;`
97			`wire SIEPortWEn;`
98			`reg [7:0]TxByteOut, next_TxByteOut;`
99			`reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;`
100			`reg USBWireCtrl, next_USBWireCtrl;`
101			`reg [1:0]USBWireData, next_USBWireData;`
102			`wire USBWireGnt;`
103			`wire USBWireRdy;`
104			`reg USBWireReq, next_USBWireReq;`
105			`reg USBWireWEn, next_USBWireWEn;`
106
107			`// diagram signals declarations`
108			`reg [4:0]i, next_i;`
109			`reg [7:0]SIEPortCtrl, next_SIEPortCtrl;`
110			`reg [7:0]SIEPortData, next_SIEPortData;`
111
112			`// BINARY ENCODED state machine: SIETx`
113			`// State codes definitions:`
114	7	sfielding	`define RES_ST_CHK_FIN 6'b000000
115	9	sfielding	`define DIR_CTL_CHK_FIN 6'b000001
116			`define PKT_ST_CHK_PID 6'b000010
117			`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
118			`define IDLE 6'b000100
119			`define PKT_ST_TKN_CRC_PKT_SENT 6'b000101
120			`define PKT_ST_HS_PKT_SENT 6'b000110
121			`define PKT_ST_DATA_DATA_PKT_SENT 6'b000111
122			`define PKT_ST_DATA_PID_PKT_SENT 6'b001000
123			`define PKT_ST_SPCL_PKT_SENT 6'b001001
124			`define PKT_ST_TKN_PID_PKT_SENT 6'b001010
125	5	sfielding	`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
126			`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
127			`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
128			`define RES_ST_S1 6'b001110
129			`define RES_ST_S3 6'b001111
130			`define RES_ST_S4 6'b010000
131			`define RES_ST_S5 6'b010001
132			`define RES_ST_S6 6'b010010
133			`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
134			`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
135			`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
136			`define START_SIETX 6'b010110
137			`define STX_CHK_ST 6'b010111
138			`define STX_WAIT_BYTE 6'b011000
139	9	sfielding	`define PKT_ST_DATA_DATA_UPD_CRC 6'b011001
140			`define PKT_ST_TKN_CRC_UPD_CRC 6'b011010
141			`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011011
142			`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011100
143			`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011101
144	5	sfielding	`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
145	9	sfielding	`define RES_ST_WAIT_GNT 6'b011111
146			`define DIR_CTL_WAIT_GNT 6'b100000
147			`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
148			`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
149			`define PKT_ST_SPCL_WAIT_RDY 6'b100011
150			`define PKT_ST_HS_WAIT_RDY 6'b100100
151			`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100101
152			`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100110
153			`define DIR_CTL_WAIT_RDY 6'b100111
154			`define RES_ST_WAIT_RDY 6'b101000
155			`define PKT_ST_DATA_DATA_WAIT_RDY 6'b101001
156			`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101010
157			`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101011
158			`define PKT_ST_WAIT_RDY_PKT 6'b101100
159			`define PKT_ST_SPCL_WAIT_WIRE 6'b101101
160			`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101110
161			`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101111
162			`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110000
163	5	sfielding
164			`reg [5:0]CurrState_SIETx, NextState_SIETx;`
165
166
167			`// Machine: SIETx`
168
169			`// NextState logic (combinatorial)`
170	9	sfielding	`always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)`
171	5	sfielding	`begin`
172			`NextState_SIETx <= CurrState_SIETx;`
173			`// Set default values for outputs and signals`
174			`next_USBWireWEn <= USBWireWEn;`
175			`next_i <= i;`
176			`next_USBWireReq <= USBWireReq;`
177			`next_processTxByteWEn <= processTxByteWEn;`
178			`next_rstCRC <= rstCRC;`
179			`next_USBWireData <= USBWireData;`
180			`next_USBWireCtrl <= USBWireCtrl;`
181			`next_TxByteOut <= TxByteOut;`
182			`next_TxByteOutCtrl <= TxByteOutCtrl;`
183			`next_CRCData <= CRCData;`
184			`next_CRC5En <= CRC5En;`
185			`next_CRC5_8Bit <= CRC5_8Bit;`
186			`next_CRC16En <= CRC16En;`
187			`next_SIEPortTxRdy <= SIEPortTxRdy;`
188			`next_SIEPortData <= SIEPortData;`
189			`next_SIEPortCtrl <= SIEPortCtrl;`
190			`case (CurrState_SIETx) // synopsys parallel_case full_case`
191	9	sfielding	`IDLE:
192			`begin`
193			NextState_SIETx <= `STX_WAIT_BYTE;
194			`end`
195	5	sfielding	`START_SIETX:
196			`begin`
197			`next_processTxByteWEn <= 1'b0;`
198			`next_TxByteOut <= 8'h00;`
199			`next_TxByteOutCtrl <= 8'h00;`
200			`next_USBWireData <= 2'b00;`
201			next_USBWireCtrl <= `TRI_STATE;
202			`next_USBWireReq <= 1'b0;`
203			`next_USBWireWEn <= 1'b0;`
204			`next_rstCRC <= 1'b0;`
205			`next_CRCData <= 8'h00;`
206			`next_CRC5En <= 1'b0;`
207			`next_CRC5_8Bit <= 1'b0;`
208			`next_CRC16En <= 1'b0;`
209			`next_SIEPortTxRdy <= 1'b0;`
210			`next_SIEPortData <= 8'h00;`
211			`next_SIEPortCtrl <= 8'h00;`
212			`next_i <= 5'h0;`
213			NextState_SIETx <= `STX_WAIT_BYTE;
214			`end`
215			`STX_CHK_ST:
216			`begin`
217			if (SIEPortCtrl == `TX_PACKET_START)
218			`begin`
219	9	sfielding	NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
220	5	sfielding	`end`
221	7	sfielding	else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
222	5	sfielding	`begin`
223	7	sfielding	NextState_SIETx <= `DIR_CTL_WAIT_GNT;
224	5	sfielding	`next_USBWireReq <= 1'b1;`
225			`end`
226	9	sfielding	else if (SIEPortCtrl == `TX_IDLE)
227			`begin`
228			NextState_SIETx <= `IDLE;
229			`end`
230	5	sfielding	else if (SIEPortCtrl == `TX_RESUME_START)
231			`begin`
232			NextState_SIETx <= `RES_ST_WAIT_GNT;
233			`next_USBWireReq <= 1'b1;`
234			`next_i <= 5'h0;`
235			`end`
236			`end`
237			`STX_WAIT_BYTE:
238			`begin`
239			`next_SIEPortTxRdy <= 1'b1;`
240			`if (SIEPortWEn == 1'b1)`
241			`begin`
242			NextState_SIETx <= `STX_CHK_ST;
243			`next_SIEPortData <= SIEPortDataIn;`
244			`next_SIEPortCtrl <= SIEPortCtrlIn;`
245			`next_SIEPortTxRdy <= 1'b0;`
246			`end`
247			`end`
248			`DIR_CTL_CHK_FIN:
249			`begin`
250			`next_USBWireWEn <= 1'b0;`
251			`next_i <= i + 1'b1;`
252			`if (i == 5'h7)`
253			`begin`
254			NextState_SIETx <= `STX_WAIT_BYTE;
255			`next_USBWireReq <= 1'b0;`
256			`end`
257			`else`
258			`begin`
259			NextState_SIETx <= `DIR_CTL_WAIT_RDY;
260			`end`
261			`end`
262			`DIR_CTL_WAIT_GNT:
263			`begin`
264			`next_i <= 5'h0;`
265			`if (USBWireGnt == 1'b1)`
266			`begin`
267			NextState_SIETx <= `DIR_CTL_WAIT_RDY;
268			`end`
269			`end`
270			`DIR_CTL_WAIT_RDY:
271			`begin`
272			`if (USBWireRdy == 1'b1)`
273			`begin`
274			NextState_SIETx <= `DIR_CTL_CHK_FIN;
275			`next_USBWireData <= SIEPortData[1:0];`
276			next_USBWireCtrl <= `DRIVE;
277			`next_USBWireWEn <= 1'b1;`
278			`end`
279			`end`
280	9	sfielding	`PKT_ST_CHK_PID:
281	5	sfielding	`begin`
282	9	sfielding	`next_processTxByteWEn <= 1'b0;`
283			if (SIEPortData[1:0] == `TOKEN)
284	5	sfielding	`begin`
285	9	sfielding	NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
286	5	sfielding	`end`
287	9	sfielding	else if (SIEPortData[1:0] == `HANDSHAKE)
288	5	sfielding	`begin`
289	7	sfielding	NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
290			`end`
291	9	sfielding	else if (SIEPortData[1:0] == `DATA)
292	7	sfielding	`begin`
293	9	sfielding	NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
294	5	sfielding	`end`
295	7	sfielding	else if (SIEPortData[1:0] == `SPECIAL)
296	5	sfielding	`begin`
297	7	sfielding	NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
298	5	sfielding	`end`
299			`end`
300			`PKT_ST_WAIT_RDY_PKT:
301			`begin`
302			`if (processTxByteRdy == 1'b1)`
303			`begin`
304			NextState_SIETx <= `PKT_ST_CHK_PID;
305			`next_processTxByteWEn <= 1'b1;`
306			next_TxByteOut <= `SYNC_BYTE;
307			next_TxByteOutCtrl <= `DATA_START;
308			`end`
309			`end`
310			`PKT_ST_DATA_CRC_PKT_SENT1:
311			`begin`
312			`next_processTxByteWEn <= 1'b0;`
313			NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
314			`end`
315			`PKT_ST_DATA_CRC_PKT_SENT2:
316			`begin`
317			`next_processTxByteWEn <= 1'b0;`
318			NextState_SIETx <= `STX_WAIT_BYTE;
319			`end`
320			`PKT_ST_DATA_CRC_WAIT_RDY1:
321			`begin`
322			`if (processTxByteRdy == 1'b1)`
323			`begin`
324			NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
325			`next_processTxByteWEn <= 1'b1;`
326			`next_TxByteOut <= ~CRC16Result[7:0];`
327			next_TxByteOutCtrl <= `DATA_STREAM;
328			`end`
329			`end`
330			`PKT_ST_DATA_CRC_WAIT_RDY2:
331			`begin`
332			`if (processTxByteRdy == 1'b1)`
333			`begin`
334			NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
335			`next_processTxByteWEn <= 1'b1;`
336			`next_TxByteOut <= ~CRC16Result[15:8];`
337			next_TxByteOutCtrl <= `DATA_STOP;
338			`end`
339			`end`
340			`PKT_ST_DATA_DATA_CHK_STOP:
341			`begin`
342			if (SIEPortCtrl == `TX_PACKET_STOP)
343			`begin`
344			NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
345			`end`
346			`else`
347			`begin`
348			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
349			`end`
350			`end`
351			`PKT_ST_DATA_DATA_PKT_SENT:
352			`begin`
353			`next_processTxByteWEn <= 1'b0;`
354			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
355			`end`
356			`PKT_ST_DATA_DATA_UPD_CRC:
357			`begin`
358			`next_CRCData <= SIEPortData;`
359			`next_CRC16En <= 1'b1;`
360			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
361			`end`
362			`PKT_ST_DATA_DATA_WAIT_BYTE:
363			`begin`
364			`next_SIEPortTxRdy <= 1'b1;`
365			`if (SIEPortWEn == 1'b1)`
366			`begin`
367			NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
368			`next_SIEPortData <= SIEPortDataIn;`
369			`next_SIEPortCtrl <= SIEPortCtrlIn;`
370			`next_SIEPortTxRdy <= 1'b0;`
371			`end`
372			`end`
373			`PKT_ST_DATA_DATA_WAIT_RDY:
374			`begin`
375			`next_CRC16En <= 1'b0;`
376			`if (processTxByteRdy == 1'b1)`
377			`begin`
378			NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
379			`next_processTxByteWEn <= 1'b1;`
380			`next_TxByteOut <= SIEPortData;`
381			next_TxByteOutCtrl <= `DATA_STREAM;
382			`end`
383			`end`
384			`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
385			`begin`
386			`if (CRC16UpdateRdy == 1'b1)`
387			`begin`
388			NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
389			`end`
390			`end`
391			`PKT_ST_DATA_PID_PKT_SENT:
392			`begin`
393			`next_processTxByteWEn <= 1'b0;`
394			`next_rstCRC <= 1'b0;`
395			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
396			`end`
397			`PKT_ST_DATA_PID_WAIT_RDY:
398			`begin`
399			`if (processTxByteRdy == 1'b1)`
400			`begin`
401			NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
402			`next_processTxByteWEn <= 1'b1;`
403			`next_TxByteOut <= SIEPortData;`
404			next_TxByteOutCtrl <= `DATA_STREAM;
405			`next_rstCRC <= 1'b1;`
406			`end`
407			`end`
408			`PKT_ST_HS_PKT_SENT:
409			`begin`
410			`next_processTxByteWEn <= 1'b0;`
411			NextState_SIETx <= `STX_WAIT_BYTE;
412			`end`
413			`PKT_ST_HS_WAIT_RDY:
414			`begin`
415			`if (processTxByteRdy == 1'b1)`
416			`begin`
417			NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
418			`next_processTxByteWEn <= 1'b1;`
419			`next_TxByteOut <= SIEPortData;`
420			next_TxByteOutCtrl <= `DATA_STOP;
421			`end`
422			`end`
423			`PKT_ST_SPCL_PKT_SENT:
424			`begin`
425			`next_processTxByteWEn <= 1'b0;`
426			NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
427			`end`
428			`PKT_ST_SPCL_SEND_IDLE1:
429			`begin`
430			`next_USBWireWEn <= 1'b0;`
431			`if (USBWireRdy == 1'b1)`
432			`begin`
433			NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
434			`next_USBWireData <= JBit;`
435			next_USBWireCtrl <= `TRI_STATE;
436			`next_USBWireWEn <= 1'b1;`
437			`end`
438			`end`
439			`PKT_ST_SPCL_SEND_IDLE2:
440			`begin`
441			`next_USBWireWEn <= 1'b0;`
442			`if (USBWireRdy == 1'b1)`
443			`begin`
444			NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
445			`next_USBWireData <= JBit;`
446			next_USBWireCtrl <= `TRI_STATE;
447			`next_USBWireWEn <= 1'b1;`
448			`end`
449			`end`
450			`PKT_ST_SPCL_SEND_IDLE3:
451			`begin`
452			`next_USBWireWEn <= 1'b0;`
453			NextState_SIETx <= `STX_WAIT_BYTE;
454			`end`
455			`PKT_ST_SPCL_WAIT_RDY:
456			`begin`
457			`if (processTxByteRdy == 1'b1)`
458			`begin`
459			NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
460			`next_processTxByteWEn <= 1'b1;`
461			`next_TxByteOut <= SIEPortData;`
462			next_TxByteOutCtrl <= `DATA_STOP;
463			`end`
464			`end`
465			`PKT_ST_SPCL_WAIT_WIRE:
466			`begin`
467			`if (USBWireRdy == 1'b1)`
468			`begin`
469			NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
470			`next_USBWireData <= JBit;`
471			next_USBWireCtrl <= `TRI_STATE;
472			`next_USBWireWEn <= 1'b1;`
473			`end`
474			`end`
475			`PKT_ST_TKN_BYTE1_PKT_SENT1:
476			`begin`
477			`next_processTxByteWEn <= 1'b0;`
478			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
479			`end`
480			`PKT_ST_TKN_BYTE1_UPD_CRC:
481			`begin`
482			`next_CRCData <= SIEPortData;`
483			`next_CRC5_8Bit <= 1'b1;`
484			`next_CRC5En <= 1'b1;`
485			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
486			`end`
487			`PKT_ST_TKN_BYTE1_WAIT_BYTE:
488			`begin`
489			`next_SIEPortTxRdy <= 1'b1;`
490			`if (SIEPortWEn == 1'b1)`
491			`begin`
492			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
493			`next_SIEPortData <= SIEPortDataIn;`
494			`next_SIEPortCtrl <= SIEPortCtrlIn;`
495			`next_SIEPortTxRdy <= 1'b0;`
496			`end`
497			`end`
498			`PKT_ST_TKN_BYTE1_WAIT_RDY:
499			`begin`
500			`next_CRC5En <= 1'b0;`

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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [SIETransmitter.v] - Blame information for rev 9