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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : Steve
// Company     : Base2Designs
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxBit.v
// Generated   : 09/12/04 22:54:47
// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxBit.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
 
module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
input   [1:0] JBit;
input   [1:0] KBit;
input   [1:0] RxBitsIn;
input   clk;
input   processRxBitsWEn;
input   processRxByteRdy;
input   rst;
output  [7:0] RxCtrlOut;
output  [7:0] RxDataOut;
output  processRxBitRdy;
output  processRxByteWEn;
output  resumeDetected;
 
wire    [1:0] JBit;
wire    [1:0] KBit;
wire    [1:0] RxBitsIn;
reg     [7:0] RxCtrlOut, next_RxCtrlOut;
reg     [7:0] RxDataOut, next_RxDataOut;
wire    clk;
reg     processRxBitRdy, next_processRxBitRdy;
wire    processRxBitsWEn;
wire    processRxByteRdy;
reg     processRxByteWEn, next_processRxByteWEn;
reg     resumeDetected, next_resumeDetected;
wire    rst;
 
// diagram signals declarations
reg  [3:0]RXBitCount, next_RXBitCount;
reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
reg  [7:0]RXByte, next_RXByte;
reg  [3:0]RXSameBitCount, next_RXSameBitCount;
reg  [1:0]RxBits, next_RxBits;
reg bitStuffError, next_bitStuffError;
reg  [1:0]oldRXBits, next_oldRXBits;
reg  [3:0]resumeWaitCnt, next_resumeWaitCnt;
 
// BINARY ENCODED state machine: prRxBit
// State codes definitions:
`define START 4'b0000
`define IDLE_FIRST_BIT 4'b0001
`define WAIT_BITS 4'b0010
`define IDLE_CHK_KBIT 4'b0011
`define DATA_RX_LAST_BIT 4'b0100
`define DATA_RX_CHK_SE0 4'b0101
`define DATA_RX_DATA_DESTUFF 4'b0110
`define DATA_RX_BYTE_SEND2 4'b0111
`define DATA_RX_BYTE_WAIT_RDY 4'b1000
`define RES_RX_CHK 4'b1001
`define DATA_RX_ERROR_CHK_RES 4'b1010
`define RES_END_CHK1 4'b1011
`define IDLE_WAIT_PRB_RDY 4'b1100
`define DATA_RX_WAIT_PRB_RDY 4'b1101
`define DATA_RX_ERROR_WAIT_RDY 4'b1110
 
reg [3:0] CurrState_prRxBit;
reg [3:0] NextState_prRxBit;
 
 
//--------------------------------------------------------------------
// Machine: prRxBit
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
begin : prRxBit_NextState
        NextState_prRxBit <= CurrState_prRxBit;
        // Set default values for outputs and signals
        next_processRxByteWEn <= processRxByteWEn;
        next_RxCtrlOut <= RxCtrlOut;
        next_RxDataOut <= RxDataOut;
        next_resumeDetected <= resumeDetected;
        next_RXBitStMachCurrState <= RXBitStMachCurrState;
        next_RxBits <= RxBits;
        next_RXSameBitCount <= RXSameBitCount;
        next_RXBitCount <= RXBitCount;
        next_oldRXBits <= oldRXBits;
        next_RXByte <= RXByte;
        next_bitStuffError <= bitStuffError;
        next_resumeWaitCnt <= resumeWaitCnt;
        next_processRxBitRdy <= processRxBitRdy;
        case (CurrState_prRxBit) // synopsys parallel_case full_case
                `START:
                begin
                        next_processRxByteWEn <= 1'b0;
                        next_RxCtrlOut <= 8'h00;
                        next_RxDataOut <= 8'h00;
                        next_resumeDetected <= 1'b0;
                        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
                        next_RxBits <= 2'b00;
                        next_RXSameBitCount <= 4'h0;
                        next_RXBitCount <= 4'h0;
                        next_oldRXBits <= 2'b00;
                        next_RXByte <= 8'h00;
                        next_bitStuffError <= 1'b0;
                        next_resumeWaitCnt <= 4'h0;
                        next_processRxBitRdy <= 1'b1;
                        NextState_prRxBit <= `WAIT_BITS;
                end
                `WAIT_BITS:
                        if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
                        begin
                                NextState_prRxBit <= `DATA_RX_CHK_SE0;
                                next_RxBits <= RxBitsIn;
                                next_processRxBitRdy <= 1'b0;
                        end
                        else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
                        begin
                                NextState_prRxBit <= `RES_RX_CHK;
                                next_RxBits <= RxBitsIn;
                                next_processRxBitRdy <= 1'b0;
                        end
                        else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
                        begin
                                NextState_prRxBit <= `RES_END_CHK1;
                                next_RxBits <= RxBitsIn;
                                next_processRxBitRdy <= 1'b0;
                        end
                        else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
                        begin
                                NextState_prRxBit <= `IDLE_CHK_KBIT;
                                next_RxBits <= RxBitsIn;
                                next_processRxBitRdy <= 1'b0;
                        end
                `IDLE_FIRST_BIT:
                begin
                        next_processRxByteWEn <= 1'b0;
                        next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
                        next_RXSameBitCount <= 4'h1;
                        next_RXBitCount <= 4'h1;
                        next_oldRXBits <= RxBits;
                        //zero is always the first RZ data bit of a new packet
                        next_RXByte <= 8'h00;
                        NextState_prRxBit <= `WAIT_BITS;
                        next_processRxBitRdy <= 1'b1;
                end
                `IDLE_CHK_KBIT:
                        if (RxBits == KBit)
                                NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
                        else
                        begin
                                NextState_prRxBit <= `WAIT_BITS;
                                next_processRxBitRdy <= 1'b1;
                        end
                `IDLE_WAIT_PRB_RDY:
                        if (processRxByteRdy == 1'b1)
                        begin
                                NextState_prRxBit <= `IDLE_FIRST_BIT;
                                next_RxDataOut <= 8'h00;
                                //redundant data
                                next_RxCtrlOut <= `DATA_START;
                                //start of packet
                                next_processRxByteWEn <= 1'b1;
                        end
                `DATA_RX_LAST_BIT:
                begin
                        next_processRxByteWEn <= 1'b0;
                        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
                        NextState_prRxBit <= `WAIT_BITS;
                        next_processRxBitRdy <= 1'b1;
                end
                `DATA_RX_CHK_SE0:
                begin
                        next_bitStuffError <= 1'b0;
                        if (RxBits == `SE0)
                                NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
                        else
                        begin
                                NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
                                if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
                                begin
                                  next_RXSameBitCount <= RXSameBitCount + 1'b1;
                                    //inc 'RXSameBitCount'
                                    if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error
                                    next_bitStuffError <= 1'b1;
                                        //flag 'bitStuffError'
                                    else                                          //else no bit stuffing error
                                    begin
                                    next_RXBitCount <= RXBitCount + 1'b1;
                                        if (RXBitCount != 4'h7) begin
                                      next_processRxBitRdy <= 1'b1;
                                            //early indication of ready
                                                end
                                    next_RXByte <= { 1'b1, RXByte[7:1]};
                                        //RZ bit = 1 (ie no change in 'RxBits')
                                    end
                                end
                                else                                            //else current 'RxBits' are different from old 'RxBits'
                                begin
                                    if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
                                    begin
                                    next_RXBitCount <= RXBitCount + 1'b1;
                                        if (RXBitCount != 4'h7) begin
                                      next_processRxBitRdy <= 1'b1;
                                            //early indication of ready
                                                end
                                    next_RXByte <= {1'b0, RXByte[7:1]};
                                        //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
                                    end
                                  next_RXSameBitCount <= 4'h1;
                                    //reset 'RXSameBitCount'
                                end
                                next_oldRXBits <= RxBits;
                        end
                end
                `DATA_RX_WAIT_PRB_RDY:
                        if (processRxByteRdy == 1'b1)
                        begin
                                NextState_prRxBit <= `DATA_RX_LAST_BIT;
                                next_RxDataOut <= 8'h00;
                                //redundant data
                                next_RxCtrlOut <= `DATA_STOP;
                                //end of packet
                                next_processRxByteWEn <= 1'b1;
                        end
                `DATA_RX_DATA_DESTUFF:
                        if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
                                NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
                        else if (bitStuffError == 1'b1)
                                NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
                        else
                        begin
                                NextState_prRxBit <= `WAIT_BITS;
                                next_processRxBitRdy <= 1'b1;
                        end
                `DATA_RX_BYTE_SEND2:
                begin
                        next_processRxByteWEn <= 1'b0;
                        NextState_prRxBit <= `WAIT_BITS;
                        next_processRxBitRdy <= 1'b1;
                end
                `DATA_RX_BYTE_WAIT_RDY:
                        if (processRxByteRdy == 1'b1)
                        begin
                                NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
                                next_RXBitCount <= 4'h0;
                                next_RxDataOut <= RXByte;
                                next_RxCtrlOut <= `DATA_STREAM;
                                next_processRxByteWEn <= 1'b1;
                        end
                `DATA_RX_ERROR_CHK_RES:
                begin
                        next_processRxByteWEn <= 1'b0;
                        if (RxBits == JBit)                           //if current bit is a JBit, then
                          next_RXBitStMachCurrState <= `IDLE_BIT_ST;
                            //next state is idle
                        else                                          //else
                        begin
                          next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
                            //check for resume
                          next_resumeWaitCnt <= 0;
                        end
                        NextState_prRxBit <= `WAIT_BITS;
                        next_processRxBitRdy <= 1'b1;
                end
                `DATA_RX_ERROR_WAIT_RDY:
                        if (processRxByteRdy == 1'b1)
                        begin
                                NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
                                next_RxDataOut <= 8'h00;
                                //redundant data
                                next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
                                next_processRxByteWEn <= 1'b1;
                        end
                `RES_RX_CHK:
                begin
                        if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
                          next_RXBitStMachCurrState <= `IDLE_BIT_ST;
                        else
                        begin
                          next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
                            //if we've waited long enough, then
                            if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
                            begin
                            next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
                            next_resumeDetected <= 1'b1;
                                //report resume detected
                            end
                        end
                        NextState_prRxBit <= `WAIT_BITS;
                        next_processRxBitRdy <= 1'b1;
                end
                `RES_END_CHK1:
                begin
                        if (RxBits != KBit)  //line must leave KBit state for the end of resume
                        begin
                          next_RXBitStMachCurrState <= `IDLE_BIT_ST;
                          next_resumeDetected <= 1'b0;
                            //clear resume detected flag
                        end
                        NextState_prRxBit <= `WAIT_BITS;
                        next_processRxBitRdy <= 1'b1;
                end
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prRxBit_CurrentState
        if (rst)
                CurrState_prRxBit <= `START;
        else
                CurrState_prRxBit <= NextState_prRxBit;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prRxBit_RegOutput
        if (rst)
        begin
                RXBitStMachCurrState <= `IDLE_BIT_ST;
                RxBits <= 2'b00;
                RXSameBitCount <= 4'h0;
                RXBitCount <= 4'h0;
                oldRXBits <= 2'b00;
                RXByte <= 8'h00;
                bitStuffError <= 1'b0;
                resumeWaitCnt <= 4'h0;
                processRxByteWEn <= 1'b0;
                RxCtrlOut <= 8'h00;
                RxDataOut <= 8'h00;
                resumeDetected <= 1'b0;
                processRxBitRdy <= 1'b1;
        end
        else
        begin
                RXBitStMachCurrState <= next_RXBitStMachCurrState;
                RxBits <= next_RxBits;
                RXSameBitCount <= next_RXSameBitCount;
                RXBitCount <= next_RXBitCount;
                oldRXBits <= next_oldRXBits;
                RXByte <= next_RXByte;
                bitStuffError <= next_bitStuffError;
                resumeWaitCnt <= next_resumeWaitCnt;
                processRxByteWEn <= next_processRxByteWEn;
                RxCtrlOut <= next_RxCtrlOut;
                RxDataOut <= next_RxDataOut;
                resumeDetected <= next_resumeDetected;
                processRxBitRdy <= next_processRxBitRdy;
        end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author : Steve`
6			`// Company : Base2Designs`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxBit.v`
11			`// Generated : 09/12/04 22:54:47`
12			`// From : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxBit.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbSerialInterfaceEngine_h.v"
23
24
25			`module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);`
26			`input [1:0] JBit;`
27			`input [1:0] KBit;`
28			`input [1:0] RxBitsIn;`
29			`input clk;`
30			`input processRxBitsWEn;`
31			`input processRxByteRdy;`
32			`input rst;`
33			`output [7:0] RxCtrlOut;`
34			`output [7:0] RxDataOut;`
35			`output processRxBitRdy;`
36			`output processRxByteWEn;`
37			`output resumeDetected;`
38
39			`wire [1:0] JBit;`
40			`wire [1:0] KBit;`
41			`wire [1:0] RxBitsIn;`
42			`reg [7:0] RxCtrlOut, next_RxCtrlOut;`
43			`reg [7:0] RxDataOut, next_RxDataOut;`
44			`wire clk;`
45			`reg processRxBitRdy, next_processRxBitRdy;`
46			`wire processRxBitsWEn;`
47			`wire processRxByteRdy;`
48			`reg processRxByteWEn, next_processRxByteWEn;`
49			`reg resumeDetected, next_resumeDetected;`
50			`wire rst;`
51
52			`// diagram signals declarations`
53			`reg [3:0]RXBitCount, next_RXBitCount;`
54			`reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;`
55			`reg [7:0]RXByte, next_RXByte;`
56			`reg [3:0]RXSameBitCount, next_RXSameBitCount;`
57			`reg [1:0]RxBits, next_RxBits;`
58			`reg bitStuffError, next_bitStuffError;`
59			`reg [1:0]oldRXBits, next_oldRXBits;`
60			`reg [3:0]resumeWaitCnt, next_resumeWaitCnt;`
61
62			`// BINARY ENCODED state machine: prRxBit`
63			`// State codes definitions:`
64			`define START 4'b0000
65			`define IDLE_FIRST_BIT 4'b0001
66			`define WAIT_BITS 4'b0010
67			`define IDLE_CHK_KBIT 4'b0011
68			`define DATA_RX_LAST_BIT 4'b0100
69			`define DATA_RX_CHK_SE0 4'b0101
70			`define DATA_RX_DATA_DESTUFF 4'b0110
71			`define DATA_RX_BYTE_SEND2 4'b0111
72			`define DATA_RX_BYTE_WAIT_RDY 4'b1000
73			`define RES_RX_CHK 4'b1001
74			`define DATA_RX_ERROR_CHK_RES 4'b1010
75			`define RES_END_CHK1 4'b1011
76			`define IDLE_WAIT_PRB_RDY 4'b1100
77			`define DATA_RX_WAIT_PRB_RDY 4'b1101
78			`define DATA_RX_ERROR_WAIT_RDY 4'b1110
79
80			`reg [3:0] CurrState_prRxBit;`
81			`reg [3:0] NextState_prRxBit;`
82
83
84			`//--------------------------------------------------------------------`
85			`// Machine: prRxBit`
86			`//--------------------------------------------------------------------`
87			`//----------------------------------`
88			`// NextState logic (combinatorial)`
89			`//----------------------------------`
90			`always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)`
91			`begin : prRxBit_NextState`
92			`NextState_prRxBit <= CurrState_prRxBit;`
93			`// Set default values for outputs and signals`
94			`next_processRxByteWEn <= processRxByteWEn;`
95			`next_RxCtrlOut <= RxCtrlOut;`
96			`next_RxDataOut <= RxDataOut;`
97			`next_resumeDetected <= resumeDetected;`
98			`next_RXBitStMachCurrState <= RXBitStMachCurrState;`
99			`next_RxBits <= RxBits;`
100			`next_RXSameBitCount <= RXSameBitCount;`
101			`next_RXBitCount <= RXBitCount;`
102			`next_oldRXBits <= oldRXBits;`
103			`next_RXByte <= RXByte;`
104			`next_bitStuffError <= bitStuffError;`
105			`next_resumeWaitCnt <= resumeWaitCnt;`
106			`next_processRxBitRdy <= processRxBitRdy;`
107			`case (CurrState_prRxBit) // synopsys parallel_case full_case`
108			`START:
109			`begin`
110			`next_processRxByteWEn <= 1'b0;`
111			`next_RxCtrlOut <= 8'h00;`
112			`next_RxDataOut <= 8'h00;`
113			`next_resumeDetected <= 1'b0;`
114			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
115			`next_RxBits <= 2'b00;`
116			`next_RXSameBitCount <= 4'h0;`
117			`next_RXBitCount <= 4'h0;`
118			`next_oldRXBits <= 2'b00;`
119			`next_RXByte <= 8'h00;`
120			`next_bitStuffError <= 1'b0;`
121			`next_resumeWaitCnt <= 4'h0;`
122			`next_processRxBitRdy <= 1'b1;`
123			NextState_prRxBit <= `WAIT_BITS;
124			`end`
125			`WAIT_BITS:
126			if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
127			`begin`
128			NextState_prRxBit <= `DATA_RX_CHK_SE0;
129			`next_RxBits <= RxBitsIn;`
130			`next_processRxBitRdy <= 1'b0;`
131			`end`
132			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
133			`begin`
134			NextState_prRxBit <= `RES_RX_CHK;
135			`next_RxBits <= RxBitsIn;`
136			`next_processRxBitRdy <= 1'b0;`
137			`end`
138			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
139			`begin`
140			NextState_prRxBit <= `RES_END_CHK1;
141			`next_RxBits <= RxBitsIn;`
142			`next_processRxBitRdy <= 1'b0;`
143			`end`
144			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
145			`begin`
146			NextState_prRxBit <= `IDLE_CHK_KBIT;
147			`next_RxBits <= RxBitsIn;`
148			`next_processRxBitRdy <= 1'b0;`
149			`end`
150			`IDLE_FIRST_BIT:
151			`begin`
152			`next_processRxByteWEn <= 1'b0;`
153			next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
154			`next_RXSameBitCount <= 4'h1;`
155			`next_RXBitCount <= 4'h1;`
156			`next_oldRXBits <= RxBits;`
157			`//zero is always the first RZ data bit of a new packet`
158			`next_RXByte <= 8'h00;`
159			NextState_prRxBit <= `WAIT_BITS;
160			`next_processRxBitRdy <= 1'b1;`
161			`end`
162			`IDLE_CHK_KBIT:
163			`if (RxBits == KBit)`
164			NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
165			`else`
166			`begin`
167			NextState_prRxBit <= `WAIT_BITS;
168			`next_processRxBitRdy <= 1'b1;`
169			`end`
170			`IDLE_WAIT_PRB_RDY:
171			`if (processRxByteRdy == 1'b1)`
172			`begin`
173			NextState_prRxBit <= `IDLE_FIRST_BIT;
174			`next_RxDataOut <= 8'h00;`
175			`//redundant data`
176			next_RxCtrlOut <= `DATA_START;
177			`//start of packet`
178			`next_processRxByteWEn <= 1'b1;`
179			`end`
180			`DATA_RX_LAST_BIT:
181			`begin`
182			`next_processRxByteWEn <= 1'b0;`
183			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
184			NextState_prRxBit <= `WAIT_BITS;
185			`next_processRxBitRdy <= 1'b1;`
186			`end`
187			`DATA_RX_CHK_SE0:
188			`begin`
189			`next_bitStuffError <= 1'b0;`
190			if (RxBits == `SE0)
191			NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
192			`else`
193			`begin`
194			NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
195			`if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then`
196			`begin`
197			`next_RXSameBitCount <= RXSameBitCount + 1'b1;`
198			`//inc 'RXSameBitCount'`
199			if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error
200			`next_bitStuffError <= 1'b1;`
201			`//flag 'bitStuffError'`
202			`else //else no bit stuffing error`
203			`begin`
204			`next_RXBitCount <= RXBitCount + 1'b1;`
205			`if (RXBitCount != 4'h7) begin`
206			`next_processRxBitRdy <= 1'b1;`
207			`//early indication of ready`
208			`end`
209			`next_RXByte <= { 1'b1, RXByte[7:1]};`
210			`//RZ bit = 1 (ie no change in 'RxBits')`
211			`end`
212			`end`
213			`else //else current 'RxBits' are different from old 'RxBits'`
214			`begin`
215			if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
216			`begin`
217			`next_RXBitCount <= RXBitCount + 1'b1;`
218			`if (RXBitCount != 4'h7) begin`
219			`next_processRxBitRdy <= 1'b1;`
220			`//early indication of ready`
221			`end`
222			`next_RXByte <= {1'b0, RXByte[7:1]};`
223			`//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')`
224			`end`
225			`next_RXSameBitCount <= 4'h1;`
226			`//reset 'RXSameBitCount'`
227			`end`
228			`next_oldRXBits <= RxBits;`
229			`end`
230			`end`
231			`DATA_RX_WAIT_PRB_RDY:
232			`if (processRxByteRdy == 1'b1)`
233			`begin`
234			NextState_prRxBit <= `DATA_RX_LAST_BIT;
235			`next_RxDataOut <= 8'h00;`
236			`//redundant data`
237			next_RxCtrlOut <= `DATA_STOP;
238			`//end of packet`
239			`next_processRxByteWEn <= 1'b1;`
240			`end`
241			`DATA_RX_DATA_DESTUFF:
242			`if (RXBitCount == 4'h8 & bitStuffError == 1'b0)`
243			NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
244			`else if (bitStuffError == 1'b1)`
245			NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
246			`else`
247			`begin`
248			NextState_prRxBit <= `WAIT_BITS;
249			`next_processRxBitRdy <= 1'b1;`
250			`end`
251			`DATA_RX_BYTE_SEND2:
252			`begin`
253			`next_processRxByteWEn <= 1'b0;`
254			NextState_prRxBit <= `WAIT_BITS;
255			`next_processRxBitRdy <= 1'b1;`
256			`end`
257			`DATA_RX_BYTE_WAIT_RDY:
258			`if (processRxByteRdy == 1'b1)`
259			`begin`
260			NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
261			`next_RXBitCount <= 4'h0;`
262			`next_RxDataOut <= RXByte;`
263			next_RxCtrlOut <= `DATA_STREAM;
264			`next_processRxByteWEn <= 1'b1;`
265			`end`
266			`DATA_RX_ERROR_CHK_RES:
267			`begin`
268			`next_processRxByteWEn <= 1'b0;`
269			`if (RxBits == JBit) //if current bit is a JBit, then`
270			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
271			`//next state is idle`
272			`else //else`
273			`begin`
274			next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
275			`//check for resume`
276			`next_resumeWaitCnt <= 0;`
277			`end`
278			NextState_prRxBit <= `WAIT_BITS;
279			`next_processRxBitRdy <= 1'b1;`
280			`end`
281			`DATA_RX_ERROR_WAIT_RDY:
282			`if (processRxByteRdy == 1'b1)`
283			`begin`
284			NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
285			`next_RxDataOut <= 8'h00;`
286			`//redundant data`
287			next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
288			`next_processRxByteWEn <= 1'b1;`
289			`end`
290			`RES_RX_CHK:
291			`begin`
292			`if (RxBits != KBit) //can only be a resume if line remains in Kbit state`
293			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
294			`else`
295			`begin`
296			`next_resumeWaitCnt <= resumeWaitCnt + 1'b1;`
297			`//if we've waited long enough, then`
298			if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
299			`begin`
300			next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
301			`next_resumeDetected <= 1'b1;`
302			`//report resume detected`
303			`end`
304			`end`
305			NextState_prRxBit <= `WAIT_BITS;
306			`next_processRxBitRdy <= 1'b1;`
307			`end`
308			`RES_END_CHK1:
309			`begin`
310			`if (RxBits != KBit) //line must leave KBit state for the end of resume`
311			`begin`
312			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
313			`next_resumeDetected <= 1'b0;`
314			`//clear resume detected flag`
315			`end`
316			NextState_prRxBit <= `WAIT_BITS;
317			`next_processRxBitRdy <= 1'b1;`
318			`end`
319			`endcase`
320			`end`
321
322			`//----------------------------------`
323			`// Current State Logic (sequential)`
324			`//----------------------------------`
325			`always @ (posedge clk)`
326			`begin : prRxBit_CurrentState`
327			`if (rst)`
328			CurrState_prRxBit <= `START;
329			`else`
330			`CurrState_prRxBit <= NextState_prRxBit;`
331			`end`
332
333			`//----------------------------------`
334			`// Registered outputs logic`
335			`//----------------------------------`
336			`always @ (posedge clk)`
337			`begin : prRxBit_RegOutput`
338			`if (rst)`
339			`begin`
340			RXBitStMachCurrState <= `IDLE_BIT_ST;
341			`RxBits <= 2'b00;`
342			`RXSameBitCount <= 4'h0;`
343			`RXBitCount <= 4'h0;`
344			`oldRXBits <= 2'b00;`
345			`RXByte <= 8'h00;`
346			`bitStuffError <= 1'b0;`
347			`resumeWaitCnt <= 4'h0;`
348			`processRxByteWEn <= 1'b0;`
349			`RxCtrlOut <= 8'h00;`
350			`RxDataOut <= 8'h00;`
351			`resumeDetected <= 1'b0;`
352			`processRxBitRdy <= 1'b1;`
353			`end`
354			`else`
355			`begin`
356			`RXBitStMachCurrState <= next_RXBitStMachCurrState;`
357			`RxBits <= next_RxBits;`
358			`RXSameBitCount <= next_RXSameBitCount;`
359			`RXBitCount <= next_RXBitCount;`
360			`oldRXBits <= next_oldRXBits;`
361			`RXByte <= next_RXByte;`
362			`bitStuffError <= next_bitStuffError;`
363			`resumeWaitCnt <= next_resumeWaitCnt;`
364			`processRxByteWEn <= next_processRxByteWEn;`
365			`RxCtrlOut <= next_RxCtrlOut;`
366			`RxDataOut <= next_RxDataOut;`
367			`resumeDetected <= next_resumeDetected;`
368			`processRxBitRdy <= next_processRxBitRdy;`
369			`end`
370			`end`
371
372			`endmodule`