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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Blame information for rev 44

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// File        : ../RTL/serialInterfaceEngine/processRxBit.v
// Generated   : 11/10/06 05:37:22
// From        : ../RTL/serialInterfaceEngine/processRxBit.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processrxbit
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
 
 
module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, fullSpeedBitRate);
input   [1:0] JBit;
input   [1:0] KBit;
input   [1:0] RxBitsIn;
input   RxWireActive;
input   clk;
input   processRxBitsWEn;
input   processRxByteRdy;
input   rst;
output  [7:0] RxCtrlOut;
output  [7:0] RxDataOut;
output  processRxBitRdy;
output  processRxByteWEn;
output  resumeDetected;
input fullSpeedBitRate;
 
wire    [1:0] JBit;
wire    [1:0] KBit;
wire    [1:0] RxBitsIn;
reg     [7:0] RxCtrlOut, next_RxCtrlOut;
reg     [7:0] RxDataOut, next_RxDataOut;
wire    RxWireActive;
wire    clk;
reg     processRxBitRdy, next_processRxBitRdy;
wire    processRxBitsWEn;
wire    processRxByteRdy;
reg     processRxByteWEn, next_processRxByteWEn;
reg     resumeDetected, next_resumeDetected;
wire    rst;
 
// diagram signals declarations
reg  [3:0]RXBitCount, next_RXBitCount;
reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
reg  [7:0]RXByte, next_RXByte;
reg  [3:0]RXSameBitCount, next_RXSameBitCount;
reg  [1:0]RxBits, next_RxBits;
reg  bitStuffError, next_bitStuffError;
reg  [1:0]oldRXBits, next_oldRXBits;
reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
reg  [7:0]delayCnt, next_delayCnt;
 
// BINARY ENCODED state machine: prRxBit
// State codes definitions:
`define START 4'b0000
`define IDLE_FIRST_BIT 4'b0001
`define WAIT_BITS 4'b0010
`define IDLE_CHK_KBIT 4'b0011
`define DATA_RX_LAST_BIT 4'b0100
`define DATA_RX_CHK_SE0 4'b0101
`define DATA_RX_DATA_DESTUFF 4'b0110
`define DATA_RX_BYTE_SEND2 4'b0111
`define DATA_RX_BYTE_WAIT_RDY 4'b1000
`define RES_RX_CHK 4'b1001
`define DATA_RX_ERROR_CHK_RES 4'b1010
`define RES_END_CHK1 4'b1011
`define IDLE_WAIT_PRB_RDY 4'b1100
`define DATA_RX_WAIT_PRB_RDY 4'b1101
`define DATA_RX_ERROR_WAIT_RDY 4'b1110
`define LOW_SPEED_EOP_DELAY 4'b1111
 
reg [3:0] CurrState_prRxBit;
reg [3:0] NextState_prRxBit;
 
 
//--------------------------------------------------------------------
// Machine: prRxBit
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (*)
begin : prRxBit_NextState
  NextState_prRxBit <= CurrState_prRxBit;
  // Set default values for outputs and signals
  next_processRxByteWEn <= processRxByteWEn;
  next_RxCtrlOut <= RxCtrlOut;
  next_RxDataOut <= RxDataOut;
  next_resumeDetected <= resumeDetected;
  next_RXBitStMachCurrState <= RXBitStMachCurrState;
  next_RxBits <= RxBits;
  next_RXSameBitCount <= RXSameBitCount;
  next_RXBitCount <= RXBitCount;
  next_oldRXBits <= oldRXBits;
  next_RXByte <= RXByte;
  next_bitStuffError <= bitStuffError;
  next_resumeWaitCnt <= resumeWaitCnt;
  next_delayCnt <= delayCnt;
  next_processRxBitRdy <= processRxBitRdy;
  case (CurrState_prRxBit)
    `START:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RxCtrlOut <= 8'h00;
      next_RxDataOut <= 8'h00;
      next_resumeDetected <= 1'b0;
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      next_RxBits <= 2'b00;
      next_RXSameBitCount <= 4'h0;
      next_RXBitCount <= 4'h0;
      next_oldRXBits <= 2'b00;
      next_RXByte <= 8'h00;
      next_bitStuffError <= 1'b0;
      next_resumeWaitCnt <= 5'h0;
      next_processRxBitRdy <= 1'b1;
      NextState_prRxBit <= `WAIT_BITS;
    end
    `WAIT_BITS:
      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
      begin
        NextState_prRxBit <= `RES_RX_CHK;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
      begin
        NextState_prRxBit <= `DATA_RX_CHK_SE0;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
      begin
        NextState_prRxBit <= `IDLE_CHK_KBIT;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
      begin
        NextState_prRxBit <= `RES_END_CHK1;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
    `IDLE_FIRST_BIT:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
      next_RXSameBitCount <= 4'h0;
      next_RXBitCount <= 4'h1;
      next_oldRXBits <= RxBits;
      //zero is always the first RZ data bit of a new packet
      next_RXByte <= 8'h00;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `IDLE_CHK_KBIT:
      if ((RxBits == KBit) && (RxWireActive == 1'b1))
        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
      else
      begin
        NextState_prRxBit <= `WAIT_BITS;
        next_processRxBitRdy <= 1'b1;
      end
    `IDLE_WAIT_PRB_RDY:
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `IDLE_FIRST_BIT;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_START;
        //start of packet
        next_processRxByteWEn <= 1'b1;
      end
    `DATA_RX_LAST_BIT:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_CHK_SE0:
    begin
      next_bitStuffError <= 1'b0;
      if (RxBits == `SE0) begin
        if (fullSpeedBitRate == 1'b0) begin
          NextState_prRxBit <= `LOW_SPEED_EOP_DELAY;
          next_delayCnt <= 8'h00;
        end
        else
          NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
      end
      else
      begin
        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
        begin
          next_RXSameBitCount <= RXSameBitCount + 1'b1;
            //inc 'RXSameBitCount'
            if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
            next_bitStuffError <= 1'b1;
                //flag 'bitStuffError'
            else                                          //else no bit stuffing error
            begin
            next_RXBitCount <= RXBitCount + 1'b1;
                if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
              next_processRxBitRdy <= 1'b1;
                    //early indication of ready
                        end
            next_RXByte <= { 1'b1, RXByte[7:1]};
                //RZ bit = 1 (ie no change in 'RxBits')
            end
        end
        else                                            //else current 'RxBits' are different from old 'RxBits'
        begin
            if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
            begin
            next_RXBitCount <= RXBitCount + 1'b1;
                if (RXBitCount != 4'h7) begin
              next_processRxBitRdy <= 1'b1;
                    //early indication of ready
                        end
            next_RXByte <= {1'b0, RXByte[7:1]};
                //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
            end
           next_RXSameBitCount <= 4'h0;
              //reset 'RXSameBitCount'
        end
        next_oldRXBits <= RxBits;
      end
    end
    `DATA_RX_WAIT_PRB_RDY:
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_LAST_BIT;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_STOP;
        //end of packet
        next_processRxByteWEn <= 1'b1;
      end
    `DATA_RX_DATA_DESTUFF:
      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
      else if (bitStuffError == 1'b1)
        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
      else
      begin
        NextState_prRxBit <= `WAIT_BITS;
        next_processRxBitRdy <= 1'b1;
      end
    `DATA_RX_BYTE_SEND2:
    begin
      next_processRxByteWEn <= 1'b0;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_BYTE_WAIT_RDY:
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
        next_RXBitCount <= 4'h0;
        next_RxDataOut <= RXByte;
        next_RxCtrlOut <= `DATA_STREAM;
        next_processRxByteWEn <= 1'b1;
      end
    `DATA_RX_ERROR_CHK_RES:
    begin
      next_processRxByteWEn <= 1'b0;
      if (RxBits == JBit)                           //if current bit is a JBit, then
        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
          //next state is idle
      else                                          //else
      begin
        next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
          //check for resume
        next_resumeWaitCnt <= 5'h0;
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_ERROR_WAIT_RDY:
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
        next_processRxByteWEn <= 1'b1;
      end
    `RES_RX_CHK:
    begin
      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      else
      begin
        next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
          //if we've waited long enough, then
          if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
          begin
          next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
          next_resumeDetected <= 1'b1;
              //report resume detected
          end
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `RES_END_CHK1:
    begin
      if (RxBits != KBit)  //line must leave KBit state for the end of resume
      begin
        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
        next_resumeDetected <= 1'b0;
          //clear resume detected flag
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `LOW_SPEED_EOP_DELAY:
    begin
      //turn around time must be at least 2 low speed bit periods
      next_delayCnt <= delayCnt + 1'b1;
      if (delayCnt == `LS_OVER_SAMPLE_RATE * 2)
        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
    end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prRxBit_CurrentState
  if (rst)
    CurrState_prRxBit <= `START;
  else
    CurrState_prRxBit <= NextState_prRxBit;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prRxBit_RegOutput
  if (rst)
  begin
    RXBitStMachCurrState <= `IDLE_BIT_ST;
    RxBits <= 2'b00;
    RXSameBitCount <= 4'h0;
    RXBitCount <= 4'h0;
    oldRXBits <= 2'b00;
    RXByte <= 8'h00;
    bitStuffError <= 1'b0;
    resumeWaitCnt <= 5'h0;
    delayCnt <= 8'h00;
    processRxByteWEn <= 1'b0;
    RxCtrlOut <= 8'h00;
    RxDataOut <= 8'h00;
    resumeDetected <= 1'b0;
    processRxBitRdy <= 1'b1;
  end
  else
  begin
    RXBitStMachCurrState <= next_RXBitStMachCurrState;
    RxBits <= next_RxBits;
    RXSameBitCount <= next_RXSameBitCount;
    RXBitCount <= next_RXBitCount;
    oldRXBits <= next_oldRXBits;
    RXByte <= next_RXByte;
    bitStuffError <= next_bitStuffError;
    resumeWaitCnt <= next_resumeWaitCnt;
    delayCnt <= next_delayCnt;
    processRxByteWEn <= next_processRxByteWEn;
    RxCtrlOut <= next_RxCtrlOut;
    RxDataOut <= next_RxDataOut;
    resumeDetected <= next_resumeDetected;
    processRxBitRdy <= next_processRxBitRdy;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Blame information for rev 44

Line No.	Rev	Author	Line
1	44	sfielding
2			`// File : ../RTL/serialInterfaceEngine/processRxBit.v`
3			`// Generated : 11/10/06 05:37:22`
4			`// From : ../RTL/serialInterfaceEngine/processRxBit.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// processrxbit`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbSerialInterfaceEngine_h.v"
52
53
54			`module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, fullSpeedBitRate);`
55			`input [1:0] JBit;`
56			`input [1:0] KBit;`
57			`input [1:0] RxBitsIn;`
58			`input RxWireActive;`
59			`input clk;`
60			`input processRxBitsWEn;`
61			`input processRxByteRdy;`
62			`input rst;`
63			`output [7:0] RxCtrlOut;`
64			`output [7:0] RxDataOut;`
65			`output processRxBitRdy;`
66			`output processRxByteWEn;`
67			`output resumeDetected;`
68			`input fullSpeedBitRate;`
69
70			`wire [1:0] JBit;`
71			`wire [1:0] KBit;`
72			`wire [1:0] RxBitsIn;`
73			`reg [7:0] RxCtrlOut, next_RxCtrlOut;`
74			`reg [7:0] RxDataOut, next_RxDataOut;`
75			`wire RxWireActive;`
76			`wire clk;`
77			`reg processRxBitRdy, next_processRxBitRdy;`
78			`wire processRxBitsWEn;`
79			`wire processRxByteRdy;`
80			`reg processRxByteWEn, next_processRxByteWEn;`
81			`reg resumeDetected, next_resumeDetected;`
82			`wire rst;`
83
84			`// diagram signals declarations`
85			`reg [3:0]RXBitCount, next_RXBitCount;`
86			`reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;`
87			`reg [7:0]RXByte, next_RXByte;`
88			`reg [3:0]RXSameBitCount, next_RXSameBitCount;`
89			`reg [1:0]RxBits, next_RxBits;`
90			`reg bitStuffError, next_bitStuffError;`
91			`reg [1:0]oldRXBits, next_oldRXBits;`
92			`reg [4:0]resumeWaitCnt, next_resumeWaitCnt;`
93			`reg [7:0]delayCnt, next_delayCnt;`
94
95			`// BINARY ENCODED state machine: prRxBit`
96			`// State codes definitions:`
97			`define START 4'b0000
98			`define IDLE_FIRST_BIT 4'b0001
99			`define WAIT_BITS 4'b0010
100			`define IDLE_CHK_KBIT 4'b0011
101			`define DATA_RX_LAST_BIT 4'b0100
102			`define DATA_RX_CHK_SE0 4'b0101
103			`define DATA_RX_DATA_DESTUFF 4'b0110
104			`define DATA_RX_BYTE_SEND2 4'b0111
105			`define DATA_RX_BYTE_WAIT_RDY 4'b1000
106			`define RES_RX_CHK 4'b1001
107			`define DATA_RX_ERROR_CHK_RES 4'b1010
108			`define RES_END_CHK1 4'b1011
109			`define IDLE_WAIT_PRB_RDY 4'b1100
110			`define DATA_RX_WAIT_PRB_RDY 4'b1101
111			`define DATA_RX_ERROR_WAIT_RDY 4'b1110
112			`define LOW_SPEED_EOP_DELAY 4'b1111
113
114			`reg [3:0] CurrState_prRxBit;`
115			`reg [3:0] NextState_prRxBit;`
116
117
118			`//--------------------------------------------------------------------`
119			`// Machine: prRxBit`
120			`//--------------------------------------------------------------------`
121			`//----------------------------------`
122			`// Next State Logic (combinatorial)`
123			`//----------------------------------`
124			`always @ (*)`
125			`begin : prRxBit_NextState`
126			`NextState_prRxBit <= CurrState_prRxBit;`
127			`// Set default values for outputs and signals`
128			`next_processRxByteWEn <= processRxByteWEn;`
129			`next_RxCtrlOut <= RxCtrlOut;`
130			`next_RxDataOut <= RxDataOut;`
131			`next_resumeDetected <= resumeDetected;`
132			`next_RXBitStMachCurrState <= RXBitStMachCurrState;`
133			`next_RxBits <= RxBits;`
134			`next_RXSameBitCount <= RXSameBitCount;`
135			`next_RXBitCount <= RXBitCount;`
136			`next_oldRXBits <= oldRXBits;`
137			`next_RXByte <= RXByte;`
138			`next_bitStuffError <= bitStuffError;`
139			`next_resumeWaitCnt <= resumeWaitCnt;`
140			`next_delayCnt <= delayCnt;`
141			`next_processRxBitRdy <= processRxBitRdy;`
142			`case (CurrState_prRxBit)`
143			`START:
144			`begin`
145			`next_processRxByteWEn <= 1'b0;`
146			`next_RxCtrlOut <= 8'h00;`
147			`next_RxDataOut <= 8'h00;`
148			`next_resumeDetected <= 1'b0;`
149			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
150			`next_RxBits <= 2'b00;`
151			`next_RXSameBitCount <= 4'h0;`
152			`next_RXBitCount <= 4'h0;`
153			`next_oldRXBits <= 2'b00;`
154			`next_RXByte <= 8'h00;`
155			`next_bitStuffError <= 1'b0;`
156			`next_resumeWaitCnt <= 5'h0;`
157			`next_processRxBitRdy <= 1'b1;`
158			NextState_prRxBit <= `WAIT_BITS;
159			`end`
160			`WAIT_BITS:
161			if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
162			`begin`
163			NextState_prRxBit <= `RES_RX_CHK;
164			`next_RxBits <= RxBitsIn;`
165			`next_processRxBitRdy <= 1'b0;`
166			`end`
167			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
168			`begin`
169			NextState_prRxBit <= `DATA_RX_CHK_SE0;
170			`next_RxBits <= RxBitsIn;`
171			`next_processRxBitRdy <= 1'b0;`
172			`end`
173			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
174			`begin`
175			NextState_prRxBit <= `IDLE_CHK_KBIT;
176			`next_RxBits <= RxBitsIn;`
177			`next_processRxBitRdy <= 1'b0;`
178			`end`
179			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
180			`begin`
181			NextState_prRxBit <= `RES_END_CHK1;
182			`next_RxBits <= RxBitsIn;`
183			`next_processRxBitRdy <= 1'b0;`
184			`end`
185			`IDLE_FIRST_BIT:
186			`begin`
187			`next_processRxByteWEn <= 1'b0;`
188			next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
189			`next_RXSameBitCount <= 4'h0;`
190			`next_RXBitCount <= 4'h1;`
191			`next_oldRXBits <= RxBits;`
192			`//zero is always the first RZ data bit of a new packet`
193			`next_RXByte <= 8'h00;`
194			NextState_prRxBit <= `WAIT_BITS;
195			`next_processRxBitRdy <= 1'b1;`
196			`end`
197			`IDLE_CHK_KBIT:
198			`if ((RxBits == KBit) && (RxWireActive == 1'b1))`
199			NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
200			`else`
201			`begin`
202			NextState_prRxBit <= `WAIT_BITS;
203			`next_processRxBitRdy <= 1'b1;`
204			`end`
205			`IDLE_WAIT_PRB_RDY:
206			`if (processRxByteRdy == 1'b1)`
207			`begin`
208			NextState_prRxBit <= `IDLE_FIRST_BIT;
209			`next_RxDataOut <= 8'h00;`
210			`//redundant data`
211			next_RxCtrlOut <= `DATA_START;
212			`//start of packet`
213			`next_processRxByteWEn <= 1'b1;`
214			`end`
215			`DATA_RX_LAST_BIT:
216			`begin`
217			`next_processRxByteWEn <= 1'b0;`
218			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
219			NextState_prRxBit <= `WAIT_BITS;
220			`next_processRxBitRdy <= 1'b1;`
221			`end`
222			`DATA_RX_CHK_SE0:
223			`begin`
224			`next_bitStuffError <= 1'b0;`
225			if (RxBits == `SE0) begin
226			`if (fullSpeedBitRate == 1'b0) begin`
227			NextState_prRxBit <= `LOW_SPEED_EOP_DELAY;
228			`next_delayCnt <= 8'h00;`
229			`end`
230			`else`
231			NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
232			`end`
233			`else`
234			`begin`
235			NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
236			`if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then`
237			`begin`
238			`next_RXSameBitCount <= RXSameBitCount + 1'b1;`
239			`//inc 'RXSameBitCount'`
240			if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
241			`next_bitStuffError <= 1'b1;`
242			`//flag 'bitStuffError'`
243			`else //else no bit stuffing error`
244			`begin`
245			`next_RXBitCount <= RXBitCount + 1'b1;`
246			if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
247			`next_processRxBitRdy <= 1'b1;`
248			`//early indication of ready`
249			`end`
250			`next_RXByte <= { 1'b1, RXByte[7:1]};`
251			`//RZ bit = 1 (ie no change in 'RxBits')`
252			`end`
253			`end`
254			`else //else current 'RxBits' are different from old 'RxBits'`
255			`begin`
256			if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
257			`begin`
258			`next_RXBitCount <= RXBitCount + 1'b1;`
259			`if (RXBitCount != 4'h7) begin`
260			`next_processRxBitRdy <= 1'b1;`
261			`//early indication of ready`
262			`end`
263			`next_RXByte <= {1'b0, RXByte[7:1]};`
264			`//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')`
265			`end`
266			`next_RXSameBitCount <= 4'h0;`
267			`//reset 'RXSameBitCount'`
268			`end`
269			`next_oldRXBits <= RxBits;`
270			`end`
271			`end`
272			`DATA_RX_WAIT_PRB_RDY:
273			`if (processRxByteRdy == 1'b1)`
274			`begin`
275			NextState_prRxBit <= `DATA_RX_LAST_BIT;
276			`next_RxDataOut <= 8'h00;`
277			`//redundant data`
278			next_RxCtrlOut <= `DATA_STOP;
279			`//end of packet`
280			`next_processRxByteWEn <= 1'b1;`
281			`end`
282			`DATA_RX_DATA_DESTUFF:
283			`if (RXBitCount == 4'h8 & bitStuffError == 1'b0)`
284			NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
285			`else if (bitStuffError == 1'b1)`
286			NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
287			`else`
288			`begin`
289			NextState_prRxBit <= `WAIT_BITS;
290			`next_processRxBitRdy <= 1'b1;`
291			`end`
292			`DATA_RX_BYTE_SEND2:
293			`begin`
294			`next_processRxByteWEn <= 1'b0;`
295			NextState_prRxBit <= `WAIT_BITS;
296			`next_processRxBitRdy <= 1'b1;`
297			`end`
298			`DATA_RX_BYTE_WAIT_RDY:
299			`if (processRxByteRdy == 1'b1)`
300			`begin`
301			NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
302			`next_RXBitCount <= 4'h0;`
303			`next_RxDataOut <= RXByte;`
304			next_RxCtrlOut <= `DATA_STREAM;
305			`next_processRxByteWEn <= 1'b1;`
306			`end`
307			`DATA_RX_ERROR_CHK_RES:
308			`begin`
309			`next_processRxByteWEn <= 1'b0;`
310			`if (RxBits == JBit) //if current bit is a JBit, then`
311			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
312			`//next state is idle`
313			`else //else`
314			`begin`
315			next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
316			`//check for resume`
317			`next_resumeWaitCnt <= 5'h0;`
318			`end`
319			NextState_prRxBit <= `WAIT_BITS;
320			`next_processRxBitRdy <= 1'b1;`
321			`end`
322			`DATA_RX_ERROR_WAIT_RDY:
323			`if (processRxByteRdy == 1'b1)`
324			`begin`
325			NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
326			`next_RxDataOut <= 8'h00;`
327			`//redundant data`
328			next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
329			`next_processRxByteWEn <= 1'b1;`
330			`end`
331			`RES_RX_CHK:
332			`begin`
333			`if (RxBits != KBit) //can only be a resume if line remains in Kbit state`
334			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
335			`else`
336			`begin`
337			`next_resumeWaitCnt <= resumeWaitCnt + 1'b1;`
338			`//if we've waited long enough, then`
339			if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
340			`begin`
341			next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
342			`next_resumeDetected <= 1'b1;`
343			`//report resume detected`
344			`end`
345			`end`
346			NextState_prRxBit <= `WAIT_BITS;
347			`next_processRxBitRdy <= 1'b1;`
348			`end`
349			`RES_END_CHK1:
350			`begin`
351			`if (RxBits != KBit) //line must leave KBit state for the end of resume`
352			`begin`
353			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
354			`next_resumeDetected <= 1'b0;`
355			`//clear resume detected flag`
356			`end`
357			NextState_prRxBit <= `WAIT_BITS;
358			`next_processRxBitRdy <= 1'b1;`
359			`end`
360			`LOW_SPEED_EOP_DELAY:
361			`begin`
362			`//turn around time must be at least 2 low speed bit periods`
363			`next_delayCnt <= delayCnt + 1'b1;`
364			if (delayCnt == `LS_OVER_SAMPLE_RATE * 2)
365			NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
366			`end`
367			`endcase`
368			`end`
369
370			`//----------------------------------`
371			`// Current State Logic (sequential)`
372			`//----------------------------------`
373			`always @ (posedge clk)`
374			`begin : prRxBit_CurrentState`
375			`if (rst)`
376			CurrState_prRxBit <= `START;
377			`else`
378			`CurrState_prRxBit <= NextState_prRxBit;`
379			`end`
380
381			`//----------------------------------`
382			`// Registered outputs logic`
383			`//----------------------------------`
384			`always @ (posedge clk)`
385			`begin : prRxBit_RegOutput`
386			`if (rst)`
387			`begin`
388			RXBitStMachCurrState <= `IDLE_BIT_ST;
389			`RxBits <= 2'b00;`
390			`RXSameBitCount <= 4'h0;`
391			`RXBitCount <= 4'h0;`
392			`oldRXBits <= 2'b00;`
393			`RXByte <= 8'h00;`
394			`bitStuffError <= 1'b0;`
395			`resumeWaitCnt <= 5'h0;`
396			`delayCnt <= 8'h00;`
397			`processRxByteWEn <= 1'b0;`
398			`RxCtrlOut <= 8'h00;`
399			`RxDataOut <= 8'h00;`
400			`resumeDetected <= 1'b0;`
401			`processRxBitRdy <= 1'b1;`
402			`end`
403			`else`
404			`begin`
405			`RXBitStMachCurrState <= next_RXBitStMachCurrState;`
406			`RxBits <= next_RxBits;`
407			`RXSameBitCount <= next_RXSameBitCount;`
408			`RXBitCount <= next_RXBitCount;`
409			`oldRXBits <= next_oldRXBits;`
410			`RXByte <= next_RXByte;`
411			`bitStuffError <= next_bitStuffError;`
412			`resumeWaitCnt <= next_resumeWaitCnt;`
413			`delayCnt <= next_delayCnt;`
414			`processRxByteWEn <= next_processRxByteWEn;`
415			`RxCtrlOut <= next_RxCtrlOut;`
416			`RxDataOut <= next_RxDataOut;`
417			`resumeDetected <= next_resumeDetected;`
418			`processRxBitRdy <= next_processRxBitRdy;`
419			`end`
420			`end`
421
422			`endmodule`