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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Blame information for rev 7

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processrxbit
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: processRxBit.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
 
module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut);
input   clk;
input   [1:0]JBit;
input   [1:0]KBit;
input   processRxBitsWEn;
input   processRxByteRdy;
input   rst;
input   [1:0]RxBitsIn;
output  processRxBitRdy;
output  processRxByteWEn;
output  resumeDetected;
output  [7:0]RxCtrlOut;
output  [7:0]RxDataOut;
 
wire    clk;
wire    [1:0]JBit;
wire    [1:0]KBit;
reg     processRxBitRdy, next_processRxBitRdy;
wire    processRxBitsWEn;
wire    processRxByteRdy;
reg     processRxByteWEn, next_processRxByteWEn;
reg     resumeDetected, next_resumeDetected;
wire    rst;
wire    [1:0]RxBitsIn;
reg     [7:0]RxCtrlOut, next_RxCtrlOut;
reg     [7:0]RxDataOut, next_RxDataOut;
 
// diagram signals declarations
reg bitStuffError, next_bitStuffError;
reg  [1:0]oldRXBits, next_oldRXBits;
reg  [3:0]resumeWaitCnt, next_resumeWaitCnt;
reg  [3:0]RXBitCount, next_RXBitCount;
reg  [1:0]RxBits, next_RxBits;
reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
reg  [7:0]RXByte, next_RXByte;
reg  [3:0]RXSameBitCount, next_RXSameBitCount;
 
// BINARY ENCODED state machine: prRxBit
// State codes definitions:
`define START 4'b0000
`define IDLE_FIRST_BIT 4'b0001
`define WAIT_BITS 4'b0010
`define IDLE_CHK_KBIT 4'b0011
`define DATA_RX_LAST_BIT 4'b0100
`define DATA_RX_CHK_SE0 4'b0101
`define DATA_RX_DATA_DESTUFF 4'b0110
`define DATA_RX_BYTE_SEND2 4'b0111
`define DATA_RX_BYTE_WAIT_RDY 4'b1000
`define RES_RX_CHK 4'b1001
`define DATA_RX_ERROR_CHK_RES 4'b1010
`define RES_END_CHK1 4'b1011
`define IDLE_WAIT_PRB_RDY 4'b1100
`define DATA_RX_WAIT_PRB_RDY 4'b1101
`define DATA_RX_ERROR_WAIT_RDY 4'b1110
 
reg [3:0]CurrState_prRxBit, NextState_prRxBit;
 
 
// Machine: prRxBit
 
// NextState logic (combinatorial)
always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
begin
  NextState_prRxBit <= CurrState_prRxBit;
  // Set default values for outputs and signals
  next_processRxByteWEn <= processRxByteWEn;
  next_RxCtrlOut <= RxCtrlOut;
  next_RxDataOut <= RxDataOut;
  next_resumeDetected <= resumeDetected;
  next_RXBitStMachCurrState <= RXBitStMachCurrState;
  next_RxBits <= RxBits;
  next_RXSameBitCount <= RXSameBitCount;
  next_RXBitCount <= RXBitCount;
  next_oldRXBits <= oldRXBits;
  next_RXByte <= RXByte;
  next_bitStuffError <= bitStuffError;
  next_resumeWaitCnt <= resumeWaitCnt;
  next_processRxBitRdy <= processRxBitRdy;
  case (CurrState_prRxBit)  // synopsys parallel_case full_case
    `START:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RxCtrlOut <= 8'h00;
      next_RxDataOut <= 8'h00;
      next_resumeDetected <= 1'b0;
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      next_RxBits <= 2'b00;
      next_RXSameBitCount <= 4'h0;
      next_RXBitCount <= 4'h0;
      next_oldRXBits <= 2'b00;
      next_RXByte <= 8'h00;
      next_bitStuffError <= 1'b0;
      next_resumeWaitCnt <= 4'h0;
      next_processRxBitRdy <= 1'b1;
      NextState_prRxBit <= `WAIT_BITS;
    end
    `WAIT_BITS:
    begin
      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
      begin
        NextState_prRxBit <= `RES_RX_CHK;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
      begin
        NextState_prRxBit <= `DATA_RX_CHK_SE0;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
      begin
        NextState_prRxBit <= `IDLE_CHK_KBIT;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
      begin
        NextState_prRxBit <= `RES_END_CHK1;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
    end
    `IDLE_FIRST_BIT:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
      next_RXSameBitCount <= 4'h1;
      next_RXBitCount <= 4'h1;
      next_oldRXBits <= RxBits;
      //zero is always the first RZ data bit of a new packet
      next_RXByte <= 8'h00;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `IDLE_CHK_KBIT:
    begin
      if (RxBits == KBit)
      begin
        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
      end
      else
      begin
        NextState_prRxBit <= `WAIT_BITS;
        next_processRxBitRdy <= 1'b1;
      end
    end
    `IDLE_WAIT_PRB_RDY:
    begin
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `IDLE_FIRST_BIT;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_START;
        //start of packet
        next_processRxByteWEn <= 1'b1;
      end
    end
    `DATA_RX_LAST_BIT:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_CHK_SE0:
    begin
      next_bitStuffError <= 1'b0;
      if (RxBits == `SE0)
      begin
        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
      end
      else
      begin
        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
        begin
        next_RXSameBitCount <= RXSameBitCount + 1'b1;
        //inc 'RXSameBitCount'
        if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error
        next_bitStuffError <= 1'b1;
        //flag 'bitStuffError'
        else                                          //else no bit stuffing error
        begin
        next_RXBitCount <= RXBitCount + 1'b1;
        if (RXBitCount != 4'h7) begin
        next_processRxBitRdy <= 1'b1;
        //early indication of ready
        end
        next_RXByte <= { 1'b1, RXByte[7:1]};
        //RZ bit <= 1 (ie no change in 'RxBits')
        end
        end
        else                                            //else current 'RxBits' are different from old 'RxBits'
        begin
        if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
        begin
        next_RXBitCount <= RXBitCount + 1'b1;
        if (RXBitCount != 4'h7) begin
        next_processRxBitRdy <= 1'b1;
        //early indication of ready
        end
        next_RXByte <= {1'b0, RXByte[7:1]};
        //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
        end
        next_RXSameBitCount <= 4'h1;
        //reset 'RXSameBitCount'
        end
        next_oldRXBits <= RxBits;
      end
    end
    `DATA_RX_WAIT_PRB_RDY:
    begin
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_LAST_BIT;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_STOP;
        //end of packet
        next_processRxByteWEn <= 1'b1;
      end
    end
    `DATA_RX_DATA_DESTUFF:
    begin
      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
      begin
        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
      end
      else if (bitStuffError == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
      end
      else
      begin
        NextState_prRxBit <= `WAIT_BITS;
        next_processRxBitRdy <= 1'b1;
      end
    end
    `DATA_RX_BYTE_SEND2:
    begin
      next_processRxByteWEn <= 1'b0;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_BYTE_WAIT_RDY:
    begin
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
        next_RXBitCount <= 4'h0;
        next_RxDataOut <= RXByte;
        next_RxCtrlOut <= `DATA_STREAM;
        next_processRxByteWEn <= 1'b1;
      end
    end
    `DATA_RX_ERROR_CHK_RES:
    begin
      next_processRxByteWEn <= 1'b0;
      if (RxBits == JBit)                           //if current bit is a JBit, then
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      //next state is idle
      else                                          //else
      begin
      next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
      //check for resume
      next_resumeWaitCnt <= 0;
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_ERROR_WAIT_RDY:
    begin
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
        next_processRxByteWEn <= 1'b1;
      end
    end
    `RES_RX_CHK:
    begin
      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      else
      begin
      next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
      //if we've waited long enough, then
      if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
      begin
      next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
      next_resumeDetected <= 1'b1;
      //report resume detected
      end
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `RES_END_CHK1:
    begin
      if (RxBits != KBit)  //line must leave KBit state for the end of resume
      begin
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      next_resumeDetected <= 1'b0;
      //clear resume detected flag
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_prRxBit <= `START;
  else
    CurrState_prRxBit <= NextState_prRxBit;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    processRxByteWEn <= 1'b0;
    RxCtrlOut <= 8'h00;
    RxDataOut <= 8'h00;
    resumeDetected <= 1'b0;
    processRxBitRdy <= 1'b1;
    RXBitStMachCurrState <= `IDLE_BIT_ST;
    RxBits <= 2'b00;
    RXSameBitCount <= 4'h0;
    RXBitCount <= 4'h0;
    oldRXBits <= 2'b00;
    RXByte <= 8'h00;
    bitStuffError <= 1'b0;
    resumeWaitCnt <= 4'h0;
  end
  else
  begin
    processRxByteWEn <= next_processRxByteWEn;
    RxCtrlOut <= next_RxCtrlOut;
    RxDataOut <= next_RxDataOut;
    resumeDetected <= next_resumeDetected;
    processRxBitRdy <= next_processRxBitRdy;
    RXBitStMachCurrState <= next_RXBitStMachCurrState;
    RxBits <= next_RxBits;
    RXSameBitCount <= next_RXSameBitCount;
    RXBitCount <= next_RXBitCount;
    oldRXBits <= next_oldRXBits;
    RXByte <= next_RXByte;
    bitStuffError <= next_bitStuffError;
    resumeWaitCnt <= next_resumeWaitCnt;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// processrxbit`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	7	sfielding	`// $Id: processRxBit.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $`
46	5	sfielding	`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`timescale 1ns / 1ps
52			`include "usbSerialInterfaceEngine_h.v"
53
54
55			`module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut);`
56			`input clk;`
57			`input [1:0]JBit;`
58			`input [1:0]KBit;`
59			`input processRxBitsWEn;`
60			`input processRxByteRdy;`
61			`input rst;`
62			`input [1:0]RxBitsIn;`
63			`output processRxBitRdy;`
64			`output processRxByteWEn;`
65			`output resumeDetected;`
66			`output [7:0]RxCtrlOut;`
67			`output [7:0]RxDataOut;`
68
69			`wire clk;`
70			`wire [1:0]JBit;`
71			`wire [1:0]KBit;`
72			`reg processRxBitRdy, next_processRxBitRdy;`
73			`wire processRxBitsWEn;`
74			`wire processRxByteRdy;`
75			`reg processRxByteWEn, next_processRxByteWEn;`
76			`reg resumeDetected, next_resumeDetected;`
77			`wire rst;`
78			`wire [1:0]RxBitsIn;`
79			`reg [7:0]RxCtrlOut, next_RxCtrlOut;`
80			`reg [7:0]RxDataOut, next_RxDataOut;`
81
82			`// diagram signals declarations`
83			`reg bitStuffError, next_bitStuffError;`
84			`reg [1:0]oldRXBits, next_oldRXBits;`
85			`reg [3:0]resumeWaitCnt, next_resumeWaitCnt;`
86			`reg [3:0]RXBitCount, next_RXBitCount;`
87			`reg [1:0]RxBits, next_RxBits;`
88			`reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;`
89			`reg [7:0]RXByte, next_RXByte;`
90			`reg [3:0]RXSameBitCount, next_RXSameBitCount;`
91
92			`// BINARY ENCODED state machine: prRxBit`
93			`// State codes definitions:`
94			`define START 4'b0000
95			`define IDLE_FIRST_BIT 4'b0001
96			`define WAIT_BITS 4'b0010
97			`define IDLE_CHK_KBIT 4'b0011
98			`define DATA_RX_LAST_BIT 4'b0100
99			`define DATA_RX_CHK_SE0 4'b0101
100			`define DATA_RX_DATA_DESTUFF 4'b0110
101			`define DATA_RX_BYTE_SEND2 4'b0111
102			`define DATA_RX_BYTE_WAIT_RDY 4'b1000
103			`define RES_RX_CHK 4'b1001
104			`define DATA_RX_ERROR_CHK_RES 4'b1010
105			`define RES_END_CHK1 4'b1011
106			`define IDLE_WAIT_PRB_RDY 4'b1100
107			`define DATA_RX_WAIT_PRB_RDY 4'b1101
108			`define DATA_RX_ERROR_WAIT_RDY 4'b1110
109
110			`reg [3:0]CurrState_prRxBit, NextState_prRxBit;`
111
112
113			`// Machine: prRxBit`
114
115			`// NextState logic (combinatorial)`
116			`always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)`
117			`begin`
118			`NextState_prRxBit <= CurrState_prRxBit;`
119			`// Set default values for outputs and signals`
120			`next_processRxByteWEn <= processRxByteWEn;`
121			`next_RxCtrlOut <= RxCtrlOut;`
122			`next_RxDataOut <= RxDataOut;`
123			`next_resumeDetected <= resumeDetected;`
124			`next_RXBitStMachCurrState <= RXBitStMachCurrState;`
125			`next_RxBits <= RxBits;`
126			`next_RXSameBitCount <= RXSameBitCount;`
127			`next_RXBitCount <= RXBitCount;`
128			`next_oldRXBits <= oldRXBits;`
129			`next_RXByte <= RXByte;`
130			`next_bitStuffError <= bitStuffError;`
131			`next_resumeWaitCnt <= resumeWaitCnt;`
132			`next_processRxBitRdy <= processRxBitRdy;`
133			`case (CurrState_prRxBit) // synopsys parallel_case full_case`
134			`START:
135			`begin`
136			`next_processRxByteWEn <= 1'b0;`
137			`next_RxCtrlOut <= 8'h00;`
138			`next_RxDataOut <= 8'h00;`
139			`next_resumeDetected <= 1'b0;`
140			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
141			`next_RxBits <= 2'b00;`
142			`next_RXSameBitCount <= 4'h0;`
143			`next_RXBitCount <= 4'h0;`
144			`next_oldRXBits <= 2'b00;`
145			`next_RXByte <= 8'h00;`
146			`next_bitStuffError <= 1'b0;`
147			`next_resumeWaitCnt <= 4'h0;`
148			`next_processRxBitRdy <= 1'b1;`
149			NextState_prRxBit <= `WAIT_BITS;
150			`end`
151			`WAIT_BITS:
152			`begin`
153	7	sfielding	if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
154	5	sfielding	`begin`
155	7	sfielding	NextState_prRxBit <= `RES_RX_CHK;
156	5	sfielding	`next_RxBits <= RxBitsIn;`
157			`next_processRxBitRdy <= 1'b0;`
158			`end`
159	7	sfielding	else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
160	5	sfielding	`begin`
161	7	sfielding	NextState_prRxBit <= `DATA_RX_CHK_SE0;
162	5	sfielding	`next_RxBits <= RxBitsIn;`
163			`next_processRxBitRdy <= 1'b0;`
164			`end`
165	7	sfielding	else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
166	5	sfielding	`begin`
167	7	sfielding	NextState_prRxBit <= `IDLE_CHK_KBIT;
168	5	sfielding	`next_RxBits <= RxBitsIn;`
169			`next_processRxBitRdy <= 1'b0;`
170			`end`
171	7	sfielding	else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
172	5	sfielding	`begin`
173	7	sfielding	NextState_prRxBit <= `RES_END_CHK1;
174	5	sfielding	`next_RxBits <= RxBitsIn;`
175			`next_processRxBitRdy <= 1'b0;`
176			`end`
177			`end`
178			`IDLE_FIRST_BIT:
179			`begin`
180			`next_processRxByteWEn <= 1'b0;`
181			next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
182			`next_RXSameBitCount <= 4'h1;`
183			`next_RXBitCount <= 4'h1;`
184			`next_oldRXBits <= RxBits;`
185			`//zero is always the first RZ data bit of a new packet`
186			`next_RXByte <= 8'h00;`
187			NextState_prRxBit <= `WAIT_BITS;
188			`next_processRxBitRdy <= 1'b1;`
189			`end`
190			`IDLE_CHK_KBIT:
191			`begin`
192			`if (RxBits == KBit)`
193			`begin`
194			NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
195			`end`
196			`else`
197			`begin`
198			NextState_prRxBit <= `WAIT_BITS;
199			`next_processRxBitRdy <= 1'b1;`
200			`end`
201			`end`
202			`IDLE_WAIT_PRB_RDY:
203			`begin`
204			`if (processRxByteRdy == 1'b1)`
205			`begin`
206			NextState_prRxBit <= `IDLE_FIRST_BIT;
207			`next_RxDataOut <= 8'h00;`
208			`//redundant data`
209			next_RxCtrlOut <= `DATA_START;
210			`//start of packet`
211			`next_processRxByteWEn <= 1'b1;`
212			`end`
213			`end`
214			`DATA_RX_LAST_BIT:
215			`begin`
216			`next_processRxByteWEn <= 1'b0;`
217			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
218			NextState_prRxBit <= `WAIT_BITS;
219			`next_processRxBitRdy <= 1'b1;`
220			`end`
221			`DATA_RX_CHK_SE0:
222			`begin`
223			`next_bitStuffError <= 1'b0;`
224			if (RxBits == `SE0)
225			`begin`
226			NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
227			`end`
228			`else`
229			`begin`
230			NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
231			`if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then`
232			`begin`
233			`next_RXSameBitCount <= RXSameBitCount + 1'b1;`
234			`//inc 'RXSameBitCount'`
235			if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error
236			`next_bitStuffError <= 1'b1;`
237			`//flag 'bitStuffError'`
238			`else //else no bit stuffing error`
239			`begin`
240			`next_RXBitCount <= RXBitCount + 1'b1;`
241			`if (RXBitCount != 4'h7) begin`
242			`next_processRxBitRdy <= 1'b1;`
243			`//early indication of ready`
244			`end`
245			`next_RXByte <= { 1'b1, RXByte[7:1]};`
246			`//RZ bit <= 1 (ie no change in 'RxBits')`
247			`end`
248			`end`
249			`else //else current 'RxBits' are different from old 'RxBits'`
250			`begin`
251			if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
252			`begin`
253			`next_RXBitCount <= RXBitCount + 1'b1;`
254			`if (RXBitCount != 4'h7) begin`
255			`next_processRxBitRdy <= 1'b1;`
256			`//early indication of ready`
257			`end`
258			`next_RXByte <= {1'b0, RXByte[7:1]};`
259			`//RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')`
260			`end`
261			`next_RXSameBitCount <= 4'h1;`
262			`//reset 'RXSameBitCount'`
263			`end`
264			`next_oldRXBits <= RxBits;`
265			`end`
266			`end`
267			`DATA_RX_WAIT_PRB_RDY:
268			`begin`
269			`if (processRxByteRdy == 1'b1)`
270			`begin`
271			NextState_prRxBit <= `DATA_RX_LAST_BIT;
272			`next_RxDataOut <= 8'h00;`
273			`//redundant data`
274			next_RxCtrlOut <= `DATA_STOP;
275			`//end of packet`
276			`next_processRxByteWEn <= 1'b1;`
277			`end`
278			`end`
279			`DATA_RX_DATA_DESTUFF:
280			`begin`
281			`if (RXBitCount == 4'h8 & bitStuffError == 1'b0)`
282			`begin`
283			NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
284			`end`
285			`else if (bitStuffError == 1'b1)`
286			`begin`
287			NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
288			`end`
289			`else`
290			`begin`
291			NextState_prRxBit <= `WAIT_BITS;
292			`next_processRxBitRdy <= 1'b1;`
293			`end`
294			`end`
295			`DATA_RX_BYTE_SEND2:
296			`begin`
297			`next_processRxByteWEn <= 1'b0;`
298			NextState_prRxBit <= `WAIT_BITS;
299			`next_processRxBitRdy <= 1'b1;`
300			`end`
301			`DATA_RX_BYTE_WAIT_RDY:
302			`begin`
303			`if (processRxByteRdy == 1'b1)`
304			`begin`
305			NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
306			`next_RXBitCount <= 4'h0;`
307			`next_RxDataOut <= RXByte;`
308			next_RxCtrlOut <= `DATA_STREAM;
309			`next_processRxByteWEn <= 1'b1;`
310			`end`
311			`end`
312			`DATA_RX_ERROR_CHK_RES:
313			`begin`
314			`next_processRxByteWEn <= 1'b0;`
315			`if (RxBits == JBit) //if current bit is a JBit, then`
316			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
317			`//next state is idle`
318			`else //else`
319			`begin`
320			next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
321			`//check for resume`
322			`next_resumeWaitCnt <= 0;`
323			`end`
324			NextState_prRxBit <= `WAIT_BITS;
325			`next_processRxBitRdy <= 1'b1;`
326			`end`
327			`DATA_RX_ERROR_WAIT_RDY:
328			`begin`
329			`if (processRxByteRdy == 1'b1)`
330			`begin`
331			NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
332			`next_RxDataOut <= 8'h00;`
333			`//redundant data`
334			next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
335			`next_processRxByteWEn <= 1'b1;`
336			`end`
337			`end`
338			`RES_RX_CHK:
339			`begin`
340			`if (RxBits != KBit) //can only be a resume if line remains in Kbit state`
341			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
342			`else`
343			`begin`
344			`next_resumeWaitCnt <= resumeWaitCnt + 1'b1;`
345			`//if we've waited long enough, then`
346			if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
347			`begin`
348			next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
349			`next_resumeDetected <= 1'b1;`
350			`//report resume detected`
351			`end`
352			`end`
353			NextState_prRxBit <= `WAIT_BITS;
354			`next_processRxBitRdy <= 1'b1;`
355			`end`
356			`RES_END_CHK1:
357			`begin`
358			`if (RxBits != KBit) //line must leave KBit state for the end of resume`
359			`begin`
360			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
361			`next_resumeDetected <= 1'b0;`
362			`//clear resume detected flag`
363			`end`
364			NextState_prRxBit <= `WAIT_BITS;
365			`next_processRxBitRdy <= 1'b1;`
366			`end`
367			`endcase`
368			`end`
369
370			`// Current State Logic (sequential)`
371			`always @ (posedge clk)`
372			`begin`
373			`if (rst)`
374			CurrState_prRxBit <= `START;
375			`else`
376			`CurrState_prRxBit <= NextState_prRxBit;`
377			`end`
378
379			`// Registered outputs logic`
380			`always @ (posedge clk)`
381			`begin`
382			`if (rst)`
383			`begin`
384			`processRxByteWEn <= 1'b0;`
385			`RxCtrlOut <= 8'h00;`
386			`RxDataOut <= 8'h00;`
387			`resumeDetected <= 1'b0;`
388			`processRxBitRdy <= 1'b1;`
389			RXBitStMachCurrState <= `IDLE_BIT_ST;
390			`RxBits <= 2'b00;`
391			`RXSameBitCount <= 4'h0;`
392			`RXBitCount <= 4'h0;`
393			`oldRXBits <= 2'b00;`
394			`RXByte <= 8'h00;`
395			`bitStuffError <= 1'b0;`
396			`resumeWaitCnt <= 4'h0;`
397			`end`
398			`else`
399			`begin`
400			`processRxByteWEn <= next_processRxByteWEn;`
401			`RxCtrlOut <= next_RxCtrlOut;`
402			`RxDataOut <= next_RxDataOut;`
403			`resumeDetected <= next_resumeDetected;`
404			`processRxBitRdy <= next_processRxBitRdy;`
405			`RXBitStMachCurrState <= next_RXBitStMachCurrState;`
406			`RxBits <= next_RxBits;`
407			`RXSameBitCount <= next_RXSameBitCount;`
408			`RXBitCount <= next_RXBitCount;`
409			`oldRXBits <= next_oldRXBits;`
410			`RXByte <= next_RXByte;`
411			`bitStuffError <= next_bitStuffError;`
412			`resumeWaitCnt <= next_resumeWaitCnt;`
413			`end`
414			`end`
415
416	2	sfielding	`endmodule`

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