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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processTxByte.v] - Blame information for rev 9

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processTxByte
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processTxByte (clk, fullSpeedRate, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
input   clk;
input   fullSpeedRate;
input   [1:0]JBit;
input   [1:0]KBit;
input   processTxByteWEn;
input   rst;
input   [7:0]TxByteCtrlIn;
input   [7:0]TxByteIn;
input   USBWireGnt;
input   USBWireRdy;
output  processTxByteRdy;
output  USBWireCtrl;
output  [1:0]USBWireData;
output  USBWireReq;
output  USBWireWEn;
 
wire    clk;
wire    fullSpeedRate;
wire    [1:0]JBit;
wire    [1:0]KBit;
reg     processTxByteRdy, next_processTxByteRdy;
wire    processTxByteWEn;
wire    rst;
wire    [7:0]TxByteCtrlIn;
wire    [7:0]TxByteIn;
reg     USBWireCtrl, next_USBWireCtrl;
reg     [1:0]USBWireData, next_USBWireData;
wire    USBWireGnt;
wire    USBWireRdy;
reg     USBWireReq, next_USBWireReq;
reg     USBWireWEn, next_USBWireWEn;
 
// diagram signals declarations
reg  [3:0]i, next_i;
reg  [7:0]TxByte, next_TxByte;
reg  [7:0]TxByteCtrl, next_TxByteCtrl;
reg  [1:0]TXLineState, next_TXLineState;
reg  [3:0]TXOneCount, next_TXOneCount;
 
// BINARY ENCODED state machine: prcTxB
// State codes definitions:
`define START_PTBY 5'b00000
`define PTBY_WAIT_EN 5'b00001
`define SEND_BYTE_UPDATE_BYTE 5'b00010
`define SEND_BYTE_WAIT_RDY 5'b00011
`define SEND_BYTE_CHK 5'b00100
`define SEND_BYTE_BIT_STUFF 5'b00101
`define SEND_BYTE_WAIT_RDY2 5'b00110
`define SEND_BYTE_CHK_FIN 5'b00111
`define PTBY_WAIT_GNT 5'b01000
`define STOP_SND_SE0_2 5'b01001
`define STOP_SND_SE0_1 5'b01010
`define STOP_CHK 5'b01011
`define STOP_SND_J 5'b01100
`define STOP_SND_IDLE 5'b01101
`define STOP_FIN 5'b01110
`define WAIT_RDY_WIRE 5'b01111
`define WAIT_RDY_PKT 5'b10000
`define LS_START_SND_IDLE3 5'b10001
`define LS_START_SND_J1 5'b10010
`define LS_START_SND_IDLE1 5'b10011
`define LS_START_SND_IDLE2 5'b10100
`define LS_START_FIN 5'b10101
 
reg [4:0]CurrState_prcTxB, NextState_prcTxB;
 
 
// Machine: prcTxB
 
// NextState logic (combinatorial)
always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
begin
  NextState_prcTxB <= CurrState_prcTxB;
  // Set default values for outputs and signals
  next_processTxByteRdy <= processTxByteRdy;
  next_USBWireData <= USBWireData;
  next_USBWireCtrl <= USBWireCtrl;
  next_USBWireReq <= USBWireReq;
  next_USBWireWEn <= USBWireWEn;
  next_i <= i;
  next_TxByte <= TxByte;
  next_TxByteCtrl <= TxByteCtrl;
  next_TXLineState <= TXLineState;
  next_TXOneCount <= TXOneCount;
  case (CurrState_prcTxB)  // synopsys parallel_case full_case
    `START_PTBY:
    begin
      next_processTxByteRdy <= 1'b0;
      next_USBWireData <= 2'b00;
      next_USBWireCtrl <= `TRI_STATE;
      next_USBWireReq <= 1'b0;
      next_USBWireWEn <= 1'b0;
      next_i <= 4'h0;
      next_TxByte <= 8'h00;
      next_TxByteCtrl <= 8'h00;
      next_TXLineState <= 2'b0;
      next_TXOneCount <= 4'h0;
      NextState_prcTxB <= `PTBY_WAIT_EN;
    end
    `PTBY_WAIT_EN:
    begin
      next_processTxByteRdy <= 1'b1;
      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
      begin
        NextState_prcTxB <= `PTBY_WAIT_GNT;
        next_processTxByteRdy <= 1'b0;
        next_TxByte <= TxByteIn;
        next_TxByteCtrl <= TxByteCtrlIn;
        next_TXOneCount <= 1;
        next_TXLineState <= JBit;
        next_USBWireReq <= 1'b1;
      end
      else if (processTxByteWEn == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
        next_processTxByteRdy <= 1'b0;
        next_TxByte <= TxByteIn;
        next_TxByteCtrl <= TxByteCtrlIn;
        next_i <= 4'h0;
      end
    end
    `PTBY_WAIT_GNT:
    begin
      if (USBWireGnt == 1'b1)
      begin
        NextState_prcTxB <= `WAIT_RDY_WIRE;
      end
    end
    `WAIT_RDY_WIRE:
    begin
      if ((USBWireRdy == 1'b1) && (fullSpeedRate == 1'b0))
      begin
        NextState_prcTxB <= `LS_START_SND_IDLE1;
      end
      else if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `WAIT_RDY_PKT;
        //actively drive the first J bit
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    end
    `WAIT_RDY_PKT:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      next_i <= 4'h0;
    end
    `SEND_BYTE_UPDATE_BYTE:
    begin
      next_i <= i + 1'b1;
      next_TxByte <= {1'b0, TxByte[7:1] };
      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
      next_TXOneCount <= TXOneCount + 1'b1;
      //increment 'TXOneCount'
      else                                        //else this is a zero bit
      begin
      next_TXOneCount <= 4'h1;
      //reset 'TXOneCount'
      if (TXLineState == JBit)
      next_TXLineState <= KBit;
      //toggle the line state
      else
      next_TXLineState <= JBit;
      end
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
    end
    `SEND_BYTE_WAIT_RDY:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_CHK;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= TXLineState;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `SEND_BYTE_CHK:
    begin
      next_USBWireWEn <= 1'b0;
      if (TXOneCount == 4'h6)
      begin
        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
      end
      else if (i != 4'h8)
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      end
      else
      begin
        NextState_prcTxB <= `STOP_CHK;
      end
    end
    `SEND_BYTE_BIT_STUFF:
    begin
      next_TXOneCount <= 4'h1;
      //reset 'TXOneCount'
      if (TXLineState == JBit)
      next_TXLineState <= KBit;
      //toggle the line state
      else
      next_TXLineState <= JBit;
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
    end
    `SEND_BYTE_WAIT_RDY2:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= TXLineState;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `SEND_BYTE_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      if (i == 4'h8)
      begin
        NextState_prcTxB <= `STOP_CHK;
      end
      else
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      end
    end
    `STOP_SND_SE0_2:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_J;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_SND_SE0_1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_SE0_2;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_CHK:
    begin
      if (TxByteCtrl == `DATA_STOP)
      begin
        NextState_prcTxB <= `STOP_SND_SE0_1;
      end
      else
      begin
        NextState_prcTxB <= `PTBY_WAIT_EN;
      end
    end
    `STOP_SND_J:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_IDLE;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `STOP_SND_IDLE:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_FIN;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `STOP_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      //release the wire
      NextState_prcTxB <= `PTBY_WAIT_EN;
    end
    `LS_START_SND_IDLE3:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_J1;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `LS_START_SND_J1:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_FIN;
        //Drive the first JBit
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
      end
    end
    `LS_START_SND_IDLE1:
    begin
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_IDLE2;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `LS_START_SND_IDLE2:
    begin
      next_USBWireWEn <= 1'b0;
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_IDLE3;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    end
    `LS_START_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      next_i <= 4'h0;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_prcTxB <= `START_PTBY;
  else
    CurrState_prcTxB <= NextState_prcTxB;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    processTxByteRdy <= 1'b0;
    USBWireData <= 2'b00;
    USBWireCtrl <= `TRI_STATE;
    USBWireReq <= 1'b0;
    USBWireWEn <= 1'b0;
    i <= 4'h0;
    TxByte <= 8'h00;
    TxByteCtrl <= 8'h00;
    TXLineState <= 2'b0;
    TXOneCount <= 4'h0;
  end
  else
  begin
    processTxByteRdy <= next_processTxByteRdy;
    USBWireData <= next_USBWireData;
    USBWireCtrl <= next_USBWireCtrl;
    USBWireReq <= next_USBWireReq;
    USBWireWEn <= next_USBWireWEn;
    i <= next_i;
    TxByte <= next_TxByte;
    TxByteCtrl <= next_TxByteCtrl;
    TXLineState <= next_TXLineState;
    TXOneCount <= next_TXOneCount;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// processTxByte`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbConstants_h.v"
48
49	9	sfielding	`module processTxByte (clk, fullSpeedRate, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);`
50	5	sfielding	`input clk;`
51	9	sfielding	`input fullSpeedRate;`
52	5	sfielding	`input [1:0]JBit;`
53			`input [1:0]KBit;`
54			`input processTxByteWEn;`
55			`input rst;`
56			`input [7:0]TxByteCtrlIn;`
57			`input [7:0]TxByteIn;`
58			`input USBWireGnt;`
59			`input USBWireRdy;`
60			`output processTxByteRdy;`
61			`output USBWireCtrl;`
62			`output [1:0]USBWireData;`
63			`output USBWireReq;`
64			`output USBWireWEn;`
65
66			`wire clk;`
67	9	sfielding	`wire fullSpeedRate;`
68	5	sfielding	`wire [1:0]JBit;`
69			`wire [1:0]KBit;`
70			`reg processTxByteRdy, next_processTxByteRdy;`
71			`wire processTxByteWEn;`
72			`wire rst;`
73			`wire [7:0]TxByteCtrlIn;`
74			`wire [7:0]TxByteIn;`
75			`reg USBWireCtrl, next_USBWireCtrl;`
76			`reg [1:0]USBWireData, next_USBWireData;`
77			`wire USBWireGnt;`
78			`wire USBWireRdy;`
79			`reg USBWireReq, next_USBWireReq;`
80			`reg USBWireWEn, next_USBWireWEn;`
81
82			`// diagram signals declarations`
83			`reg [3:0]i, next_i;`
84			`reg [7:0]TxByte, next_TxByte;`
85			`reg [7:0]TxByteCtrl, next_TxByteCtrl;`
86			`reg [1:0]TXLineState, next_TXLineState;`
87			`reg [3:0]TXOneCount, next_TXOneCount;`
88
89			`// BINARY ENCODED state machine: prcTxB`
90			`// State codes definitions:`
91	9	sfielding	`define START_PTBY 5'b00000
92			`define PTBY_WAIT_EN 5'b00001
93			`define SEND_BYTE_UPDATE_BYTE 5'b00010
94			`define SEND_BYTE_WAIT_RDY 5'b00011
95			`define SEND_BYTE_CHK 5'b00100
96			`define SEND_BYTE_BIT_STUFF 5'b00101
97			`define SEND_BYTE_WAIT_RDY2 5'b00110
98			`define SEND_BYTE_CHK_FIN 5'b00111
99			`define PTBY_WAIT_GNT 5'b01000
100			`define STOP_SND_SE0_2 5'b01001
101			`define STOP_SND_SE0_1 5'b01010
102			`define STOP_CHK 5'b01011
103			`define STOP_SND_J 5'b01100
104			`define STOP_SND_IDLE 5'b01101
105			`define STOP_FIN 5'b01110
106			`define WAIT_RDY_WIRE 5'b01111
107			`define WAIT_RDY_PKT 5'b10000
108			`define LS_START_SND_IDLE3 5'b10001
109			`define LS_START_SND_J1 5'b10010
110			`define LS_START_SND_IDLE1 5'b10011
111			`define LS_START_SND_IDLE2 5'b10100
112			`define LS_START_FIN 5'b10101
113	5	sfielding
114	9	sfielding	`reg [4:0]CurrState_prcTxB, NextState_prcTxB;`
115	5	sfielding
116
117			`// Machine: prcTxB`
118
119			`// NextState logic (combinatorial)`
120			`always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)`
121			`begin`
122			`NextState_prcTxB <= CurrState_prcTxB;`
123			`// Set default values for outputs and signals`
124			`next_processTxByteRdy <= processTxByteRdy;`
125			`next_USBWireData <= USBWireData;`
126			`next_USBWireCtrl <= USBWireCtrl;`
127			`next_USBWireReq <= USBWireReq;`
128			`next_USBWireWEn <= USBWireWEn;`
129			`next_i <= i;`
130			`next_TxByte <= TxByte;`
131			`next_TxByteCtrl <= TxByteCtrl;`
132			`next_TXLineState <= TXLineState;`
133			`next_TXOneCount <= TXOneCount;`
134			`case (CurrState_prcTxB) // synopsys parallel_case full_case`
135			`START_PTBY:
136			`begin`
137			`next_processTxByteRdy <= 1'b0;`
138			`next_USBWireData <= 2'b00;`
139			next_USBWireCtrl <= `TRI_STATE;
140			`next_USBWireReq <= 1'b0;`
141			`next_USBWireWEn <= 1'b0;`
142			`next_i <= 4'h0;`
143			`next_TxByte <= 8'h00;`
144			`next_TxByteCtrl <= 8'h00;`
145			`next_TXLineState <= 2'b0;`
146			`next_TXOneCount <= 4'h0;`
147			NextState_prcTxB <= `PTBY_WAIT_EN;
148			`end`
149			`PTBY_WAIT_EN:
150			`begin`
151			`next_processTxByteRdy <= 1'b1;`
152			if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
153			`begin`
154			NextState_prcTxB <= `PTBY_WAIT_GNT;
155			`next_processTxByteRdy <= 1'b0;`
156			`next_TxByte <= TxByteIn;`
157			`next_TxByteCtrl <= TxByteCtrlIn;`
158			`next_TXOneCount <= 1;`
159			`next_TXLineState <= JBit;`
160			`next_USBWireReq <= 1'b1;`
161			`end`
162			`else if (processTxByteWEn == 1'b1)`
163			`begin`
164			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
165			`next_processTxByteRdy <= 1'b0;`
166			`next_TxByte <= TxByteIn;`
167			`next_TxByteCtrl <= TxByteCtrlIn;`
168			`next_i <= 4'h0;`
169			`end`
170			`end`
171			`PTBY_WAIT_GNT:
172			`begin`
173			`if (USBWireGnt == 1'b1)`
174			`begin`
175	9	sfielding	NextState_prcTxB <= `WAIT_RDY_WIRE;
176	5	sfielding	`end`
177			`end`
178	9	sfielding	`WAIT_RDY_WIRE:
179			`begin`
180			`if ((USBWireRdy == 1'b1) && (fullSpeedRate == 1'b0))`
181			`begin`
182			NextState_prcTxB <= `LS_START_SND_IDLE1;
183			`end`
184			`else if (USBWireRdy == 1'b1)`
185			`begin`
186			NextState_prcTxB <= `WAIT_RDY_PKT;
187			`//actively drive the first J bit`
188			`next_USBWireData <= JBit;`
189			next_USBWireCtrl <= `DRIVE;
190			`next_USBWireWEn <= 1'b1;`
191			`end`
192			`end`
193			`WAIT_RDY_PKT:
194			`begin`
195			`next_USBWireWEn <= 1'b0;`
196			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
197			`next_i <= 4'h0;`
198			`end`
199	5	sfielding	`SEND_BYTE_UPDATE_BYTE:
200			`begin`
201			`next_i <= i + 1'b1;`
202			`next_TxByte <= {1'b0, TxByte[7:1] };`
203			`if (TxByte[0] == 1'b1) //If this bit is 1, then`
204			`next_TXOneCount <= TXOneCount + 1'b1;`
205			`//increment 'TXOneCount'`
206			`else //else this is a zero bit`
207			`begin`
208			`next_TXOneCount <= 4'h1;`
209			`//reset 'TXOneCount'`
210			`if (TXLineState == JBit)`
211			`next_TXLineState <= KBit;`
212			`//toggle the line state`
213			`else`
214			`next_TXLineState <= JBit;`
215			`end`
216			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
217			`end`
218			`SEND_BYTE_WAIT_RDY:
219			`begin`
220			`if (USBWireRdy == 1'b1)`
221			`begin`
222			NextState_prcTxB <= `SEND_BYTE_CHK;
223			`next_USBWireWEn <= 1'b1;`
224			`next_USBWireData <= TXLineState;`
225			next_USBWireCtrl <= `DRIVE;
226			`end`
227			`end`
228			`SEND_BYTE_CHK:
229			`begin`
230			`next_USBWireWEn <= 1'b0;`
231			`if (TXOneCount == 4'h6)`
232			`begin`
233			NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
234			`end`
235			`else if (i != 4'h8)`
236			`begin`
237			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
238			`end`
239			`else`
240			`begin`
241			NextState_prcTxB <= `STOP_CHK;
242			`end`
243			`end`
244			`SEND_BYTE_BIT_STUFF:
245			`begin`
246			`next_TXOneCount <= 4'h1;`
247			`//reset 'TXOneCount'`
248			`if (TXLineState == JBit)`
249			`next_TXLineState <= KBit;`
250			`//toggle the line state`
251			`else`
252			`next_TXLineState <= JBit;`
253			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
254			`end`
255			`SEND_BYTE_WAIT_RDY2:
256			`begin`
257			`if (USBWireRdy == 1'b1)`
258			`begin`
259			NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
260			`next_USBWireWEn <= 1'b1;`
261			`next_USBWireData <= TXLineState;`
262			next_USBWireCtrl <= `DRIVE;
263			`end`
264			`end`
265			`SEND_BYTE_CHK_FIN:
266			`begin`
267			`next_USBWireWEn <= 1'b0;`
268			`if (i == 4'h8)`
269			`begin`
270			NextState_prcTxB <= `STOP_CHK;
271			`end`
272			`else`
273			`begin`
274			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
275			`end`
276			`end`
277			`STOP_SND_SE0_2:
278			`begin`
279			`next_USBWireWEn <= 1'b0;`
280			`if (USBWireRdy == 1'b1)`
281			`begin`
282			NextState_prcTxB <= `STOP_SND_J;
283			`next_USBWireWEn <= 1'b1;`
284			next_USBWireData <= `SE0;
285			next_USBWireCtrl <= `DRIVE;
286			`end`
287			`end`
288			`STOP_SND_SE0_1:
289			`begin`
290			`if (USBWireRdy == 1'b1)`
291			`begin`
292			NextState_prcTxB <= `STOP_SND_SE0_2;
293			`next_USBWireWEn <= 1'b1;`
294			next_USBWireData <= `SE0;
295			next_USBWireCtrl <= `DRIVE;
296			`end`
297			`end`
298			`STOP_CHK:
299			`begin`
300			if (TxByteCtrl == `DATA_STOP)
301			`begin`
302			NextState_prcTxB <= `STOP_SND_SE0_1;
303			`end`
304			`else`
305			`begin`
306			NextState_prcTxB <= `PTBY_WAIT_EN;
307			`end`
308			`end`
309			`STOP_SND_J:
310			`begin`
311			`next_USBWireWEn <= 1'b0;`
312			`if (USBWireRdy == 1'b1)`
313			`begin`
314			NextState_prcTxB <= `STOP_SND_IDLE;
315			`next_USBWireWEn <= 1'b1;`
316			`next_USBWireData <= JBit;`
317			next_USBWireCtrl <= `DRIVE;
318			`end`
319			`end`
320			`STOP_SND_IDLE:
321			`begin`
322			`next_USBWireWEn <= 1'b0;`
323			`if (USBWireRdy == 1'b1)`
324			`begin`
325			NextState_prcTxB <= `STOP_FIN;
326			`next_USBWireWEn <= 1'b1;`
327			`next_USBWireData <= JBit;`
328			next_USBWireCtrl <= `TRI_STATE;
329			`end`
330			`end`
331			`STOP_FIN:
332			`begin`
333			`next_USBWireWEn <= 1'b0;`
334			`next_USBWireReq <= 1'b0;`
335			`//release the wire`
336			NextState_prcTxB <= `PTBY_WAIT_EN;
337			`end`
338	9	sfielding	`LS_START_SND_IDLE3:
339			`begin`
340			`next_USBWireWEn <= 1'b0;`
341			`if (USBWireRdy == 1'b1)`
342			`begin`
343			NextState_prcTxB <= `LS_START_SND_J1;
344			`next_USBWireWEn <= 1'b1;`
345			`next_USBWireData <= JBit;`
346			next_USBWireCtrl <= `TRI_STATE;
347			`end`
348			`end`
349			`LS_START_SND_J1:
350			`begin`
351			`next_USBWireWEn <= 1'b0;`
352			`if (USBWireRdy == 1'b1)`
353			`begin`
354			NextState_prcTxB <= `LS_START_FIN;
355			`//Drive the first JBit`
356			`next_USBWireWEn <= 1'b1;`
357			`next_USBWireData <= JBit;`
358			next_USBWireCtrl <= `DRIVE;
359			`end`
360			`end`
361			`LS_START_SND_IDLE1:
362			`begin`
363			`if (USBWireRdy == 1'b1)`
364			`begin`
365			NextState_prcTxB <= `LS_START_SND_IDLE2;
366			`next_USBWireWEn <= 1'b1;`
367			`next_USBWireData <= JBit;`
368			next_USBWireCtrl <= `TRI_STATE;
369			`end`
370			`end`
371			`LS_START_SND_IDLE2:
372			`begin`
373			`next_USBWireWEn <= 1'b0;`
374			`if (USBWireRdy == 1'b1)`
375			`begin`
376			NextState_prcTxB <= `LS_START_SND_IDLE3;
377			`next_USBWireWEn <= 1'b1;`
378			`next_USBWireData <= JBit;`
379			next_USBWireCtrl <= `TRI_STATE;
380			`end`
381			`end`
382			`LS_START_FIN:
383			`begin`
384			`next_USBWireWEn <= 1'b0;`
385			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
386			`next_i <= 4'h0;`
387			`end`
388	5	sfielding	`endcase`
389			`end`
390
391			`// Current State Logic (sequential)`
392			`always @ (posedge clk)`
393			`begin`
394			`if (rst)`
395			CurrState_prcTxB <= `START_PTBY;
396			`else`
397			`CurrState_prcTxB <= NextState_prcTxB;`
398			`end`
399
400			`// Registered outputs logic`
401			`always @ (posedge clk)`
402			`begin`
403			`if (rst)`
404			`begin`
405			`processTxByteRdy <= 1'b0;`
406			`USBWireData <= 2'b00;`
407			USBWireCtrl <= `TRI_STATE;
408			`USBWireReq <= 1'b0;`
409			`USBWireWEn <= 1'b0;`
410			`i <= 4'h0;`
411			`TxByte <= 8'h00;`
412			`TxByteCtrl <= 8'h00;`
413			`TXLineState <= 2'b0;`
414			`TXOneCount <= 4'h0;`
415			`end`
416			`else`
417			`begin`
418			`processTxByteRdy <= next_processTxByteRdy;`
419			`USBWireData <= next_USBWireData;`
420			`USBWireCtrl <= next_USBWireCtrl;`
421			`USBWireReq <= next_USBWireReq;`
422			`USBWireWEn <= next_USBWireWEn;`
423			`i <= next_i;`
424			`TxByte <= next_TxByte;`
425			`TxByteCtrl <= next_TxByteCtrl;`
426			`TXLineState <= next_TXLineState;`
427			`TXOneCount <= next_TXOneCount;`
428			`end`
429			`end`
430
431	2	sfielding	`endmodule`

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