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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [siereceiver.v] - Blame information for rev 18

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// SIEReceiver
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
 
module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
input   clk;
input   rst;
input   [1:0]RxWireDataIn;
input   RxWireDataWEn;
output  [1:0]connectState;
 
wire    clk;
reg     [1:0]connectState, next_connectState;
wire    rst;
wire    [1:0]RxWireDataIn;
wire    RxWireDataWEn;
 
// diagram signals declarations
reg  [1:0]RxBits, next_RxBits;
reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
reg  [7:0]RXWaitCount, next_RXWaitCount;
 
// BINARY ENCODED state machine: rcvr
// State codes definitions:
`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
`define LS_CONN_CHK_RX_BITS 4'b0010
`define DISCNCT_CHK_RXBITS 4'b0011
`define WAIT_BIT 4'b0100
`define START_SRX 4'b0101
`define FS_CONN_CHK_RX_BITS1 4'b0110
`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
 
reg [3:0]CurrState_rcvr, NextState_rcvr;
 
 
// Machine: rcvr
 
// NextState logic (combinatorial)
always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
begin
  NextState_rcvr <= CurrState_rcvr;
  // Set default values for outputs and signals
  next_RXWaitCount <= RXWaitCount;
  next_connectState <= connectState;
  next_RXStMachCurrState <= RXStMachCurrState;
  next_RxBits <= RxBits;
  case (CurrState_rcvr)  // synopsys parallel_case full_case
    `WAIT_BIT:
    begin
      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
      begin
        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
      begin
        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
      begin
        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
      begin
        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
      begin
        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
      begin
        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
      begin
        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
        next_RxBits <= RxWireDataIn;
      end
    end
    `START_SRX:
    begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      next_RXWaitCount <= 8'h00;
      next_connectState <= `DISCONNECT;
      next_RxBits <= 2'b00;
      NextState_rcvr <= `WAIT_BIT;
    end
    `DISCNCT_CHK_RXBITS:
    begin
      if (RxBits == `ZERO_ONE)
      begin
        NextState_rcvr <= `WAIT_BIT;
        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
        next_RXWaitCount <= 8'h00;
      end
      else if (RxBits == `ONE_ZERO)
      begin
        NextState_rcvr <= `WAIT_BIT;
        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
        next_RXWaitCount <= 8'h00;
      end
      else
      begin
        NextState_rcvr <= `WAIT_BIT;
      end
    end
    `WAIT_FS_CONN_CHK_RX_BITS:
    begin
      if (RxBits == `ONE_ZERO)
      begin
      next_RXWaitCount <= RXWaitCount + 1'b1;
      if (RXWaitCount == `CONNECT_WAIT_TIME)
      begin
      next_connectState <= `FULL_SPEED_CONNECT;
      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
      end
      end
      else
      begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      end
      NextState_rcvr <= `WAIT_BIT;
    end
    `WAIT_LS_CONN_CHK_RX_BITS:
    begin
      if (RxBits == `ZERO_ONE)
      begin
      next_RXWaitCount <= RXWaitCount + 1'b1;
      if (RXWaitCount == `CONNECT_WAIT_TIME)
      begin
      next_connectState <= `LOW_SPEED_CONNECT;
      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
      end
      end
      else
      begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      end
      NextState_rcvr <= `WAIT_BIT;
    end
    `LS_CONN_CHK_RX_BITS:
    begin
      NextState_rcvr <= `WAIT_BIT;
      if (RxBits == `SE0)
      begin
      next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
      next_RXWaitCount <= 0;
      end
    end
    `FS_CONN_CHK_RX_BITS1:
    begin
      NextState_rcvr <= `WAIT_BIT;
      if (RxBits == `SE0)
      begin
      next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
      next_RXWaitCount <= 0;
      end
    end
    `WAIT_LS_DIS_CHK_RX_BITS:
    begin
      NextState_rcvr <= `WAIT_BIT;
      if (RxBits == `SE0)
      begin
      next_RXWaitCount <= RXWaitCount + 1'b1;
      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
      begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      next_connectState <= `DISCONNECT;
      end
      end
      else
      begin
      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
      end
    end
    `WAIT_FS_DIS_CHK_RX_BITS2:
    begin
      NextState_rcvr <= `WAIT_BIT;
      if (RxBits == `SE0)
      begin
      next_RXWaitCount <= RXWaitCount + 1'b1;
      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
      begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      next_connectState <= `DISCONNECT;
      end
      end
      else
      begin
      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_rcvr <= `START_SRX;
  else
    CurrState_rcvr <= NextState_rcvr;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    connectState <= `DISCONNECT;
    RXWaitCount <= 8'h00;
    RXStMachCurrState <= `DISCONNECT_ST;
    RxBits <= 2'b00;
  end
  else
  begin
    connectState <= next_connectState;
    RXWaitCount <= next_RXWaitCount;
    RXStMachCurrState <= next_RXStMachCurrState;
    RxBits <= next_RxBits;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// SIEReceiver`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47
48
49	9	sfielding	`module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);`
50	5	sfielding	`input clk;`
51			`input rst;`
52			`input [1:0]RxWireDataIn;`
53			`input RxWireDataWEn;`
54			`output [1:0]connectState;`
55
56			`wire clk;`
57			`reg [1:0]connectState, next_connectState;`
58			`wire rst;`
59			`wire [1:0]RxWireDataIn;`
60			`wire RxWireDataWEn;`
61
62			`// diagram signals declarations`
63			`reg [1:0]RxBits, next_RxBits;`
64			`reg [3:0]RXStMachCurrState, next_RXStMachCurrState;`
65			`reg [7:0]RXWaitCount, next_RXWaitCount;`
66
67			`// BINARY ENCODED state machine: rcvr`
68			`// State codes definitions:`
69			`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
70			`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
71			`define LS_CONN_CHK_RX_BITS 4'b0010
72			`define DISCNCT_CHK_RXBITS 4'b0011
73			`define WAIT_BIT 4'b0100
74			`define START_SRX 4'b0101
75	9	sfielding	`define FS_CONN_CHK_RX_BITS1 4'b0110
76			`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
77			`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
78	5	sfielding
79			`reg [3:0]CurrState_rcvr, NextState_rcvr;`
80
81
82			`// Machine: rcvr`
83
84			`// NextState logic (combinatorial)`
85	9	sfielding	`always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)`
86	5	sfielding	`begin`
87			`NextState_rcvr <= CurrState_rcvr;`
88			`// Set default values for outputs and signals`
89			`next_RXWaitCount <= RXWaitCount;`
90			`next_connectState <= connectState;`
91			`next_RXStMachCurrState <= RXStMachCurrState;`
92			`next_RxBits <= RxBits;`
93			`case (CurrState_rcvr) // synopsys parallel_case full_case`
94			`WAIT_BIT:
95			`begin`
96	18	sfielding	if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
97	5	sfielding	`begin`
98	18	sfielding	NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
99	5	sfielding	`next_RxBits <= RxWireDataIn;`
100			`end`
101	18	sfielding	else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
102	5	sfielding	`begin`
103	18	sfielding	NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
104	5	sfielding	`next_RxBits <= RxWireDataIn;`
105			`end`
106	18	sfielding	else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
107	5	sfielding	`begin`
108	18	sfielding	NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
109	5	sfielding	`next_RxBits <= RxWireDataIn;`
110			`end`
111	18	sfielding	else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
112	5	sfielding	`begin`
113	18	sfielding	NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
114	5	sfielding	`next_RxBits <= RxWireDataIn;`
115			`end`
116	18	sfielding	else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
117	5	sfielding	`begin`
118	18	sfielding	NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
119	5	sfielding	`next_RxBits <= RxWireDataIn;`
120			`end`
121			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
122			`begin`
123			NextState_rcvr <= `DISCNCT_CHK_RXBITS;
124			`next_RxBits <= RxWireDataIn;`
125			`end`
126	18	sfielding	else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
127	5	sfielding	`begin`
128	18	sfielding	NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
129	5	sfielding	`next_RxBits <= RxWireDataIn;`
130			`end`
131			`end`
132			`START_SRX:
133			`begin`
134			next_RXStMachCurrState <= `DISCONNECT_ST;
135			`next_RXWaitCount <= 8'h00;`
136			next_connectState <= `DISCONNECT;
137			`next_RxBits <= 2'b00;`
138			NextState_rcvr <= `WAIT_BIT;
139			`end`
140			`DISCNCT_CHK_RXBITS:
141			`begin`
142			if (RxBits == `ZERO_ONE)
143			`begin`
144			NextState_rcvr <= `WAIT_BIT;
145			next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
146			`next_RXWaitCount <= 8'h00;`
147			`end`
148			else if (RxBits == `ONE_ZERO)
149			`begin`
150			NextState_rcvr <= `WAIT_BIT;
151			next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
152			`next_RXWaitCount <= 8'h00;`
153			`end`
154			`else`
155			`begin`
156			NextState_rcvr <= `WAIT_BIT;
157			`end`
158			`end`
159			`WAIT_FS_CONN_CHK_RX_BITS:
160			`begin`
161			if (RxBits == `ONE_ZERO)
162			`begin`
163			`next_RXWaitCount <= RXWaitCount + 1'b1;`
164			if (RXWaitCount == `CONNECT_WAIT_TIME)
165			`begin`
166			next_connectState <= `FULL_SPEED_CONNECT;
167			next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
168			`end`
169			`end`
170			`else`
171			`begin`
172			next_RXStMachCurrState <= `DISCONNECT_ST;
173			`end`
174			NextState_rcvr <= `WAIT_BIT;
175			`end`
176			`WAIT_LS_CONN_CHK_RX_BITS:
177			`begin`
178			if (RxBits == `ZERO_ONE)
179			`begin`
180			`next_RXWaitCount <= RXWaitCount + 1'b1;`
181			if (RXWaitCount == `CONNECT_WAIT_TIME)
182			`begin`
183			next_connectState <= `LOW_SPEED_CONNECT;
184			next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
185			`end`
186			`end`
187			`else`
188			`begin`
189			next_RXStMachCurrState <= `DISCONNECT_ST;
190			`end`
191			NextState_rcvr <= `WAIT_BIT;
192			`end`
193			`LS_CONN_CHK_RX_BITS:
194			`begin`
195	9	sfielding	NextState_rcvr <= `WAIT_BIT;
196			if (RxBits == `SE0)
197	5	sfielding	`begin`
198	9	sfielding	next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
199			`next_RXWaitCount <= 0;`
200	5	sfielding	`end`
201			`end`
202	9	sfielding	`FS_CONN_CHK_RX_BITS1:
203	5	sfielding	`begin`
204			NextState_rcvr <= `WAIT_BIT;
205	9	sfielding	if (RxBits == `SE0)
206	5	sfielding	`begin`
207	9	sfielding	next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
208			`next_RXWaitCount <= 0;`
209	5	sfielding	`end`
210			`end`
211	9	sfielding	`WAIT_LS_DIS_CHK_RX_BITS:
212	5	sfielding	`begin`
213			NextState_rcvr <= `WAIT_BIT;
214	9	sfielding	if (RxBits == `SE0)
215	5	sfielding	`begin`
216	9	sfielding	`next_RXWaitCount <= RXWaitCount + 1'b1;`
217			if (RXWaitCount == `DISCONNECT_WAIT_TIME)
218			`begin`
219			next_RXStMachCurrState <= `DISCONNECT_ST;
220			next_connectState <= `DISCONNECT;
221	5	sfielding	`end`
222	9	sfielding	`end`
223			`else`
224			`begin`
225			next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
226			`end`
227	5	sfielding	`end`
228	9	sfielding	`WAIT_FS_DIS_CHK_RX_BITS2:
229	5	sfielding	`begin`
230			NextState_rcvr <= `WAIT_BIT;
231	9	sfielding	if (RxBits == `SE0)
232	5	sfielding	`begin`
233	9	sfielding	`next_RXWaitCount <= RXWaitCount + 1'b1;`
234			if (RXWaitCount == `DISCONNECT_WAIT_TIME)
235			`begin`
236			next_RXStMachCurrState <= `DISCONNECT_ST;
237			next_connectState <= `DISCONNECT;
238	5	sfielding	`end`
239	9	sfielding	`end`
240			`else`
241			`begin`
242			next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
243			`end`
244	5	sfielding	`end`
245			`endcase`
246			`end`
247
248			`// Current State Logic (sequential)`
249			`always @ (posedge clk)`
250			`begin`
251			`if (rst)`
252			CurrState_rcvr <= `START_SRX;
253			`else`
254			`CurrState_rcvr <= NextState_rcvr;`
255			`end`
256
257			`// Registered outputs logic`
258			`always @ (posedge clk)`
259			`begin`
260			`if (rst)`
261			`begin`
262			connectState <= `DISCONNECT;
263			`RXWaitCount <= 8'h00;`
264			RXStMachCurrState <= `DISCONNECT_ST;
265			`RxBits <= 2'b00;`
266			`end`
267			`else`
268			`begin`
269			`connectState <= next_connectState;`
270			`RXWaitCount <= next_RXWaitCount;`
271			`RXStMachCurrState <= next_RXStMachCurrState;`
272			`RxBits <= next_RxBits;`
273			`end`
274			`end`
275
276	2	sfielding	`endmodule`

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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [siereceiver.v] - Blame information for rev 18