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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [siereceiver.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// SIEReceiver
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: siereceiver.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
 
module SIEReceiver (clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst, RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut);
input   clk;
input   processRxBitRdyIn;
input   rst;
input   [1:0]RxWireDataIn;
input   RxWireDataWEn;
output  [1:0]connectState;
output  processRxBitsWEn;
output  [1:0]RxBitsOut;
output  SIERxRdyOut;
 
wire    clk;
reg     [1:0]connectState, next_connectState;
wire    processRxBitRdyIn;
reg     processRxBitsWEn, next_processRxBitsWEn;
wire    rst;
reg     [1:0]RxBitsOut, next_RxBitsOut;
wire    [1:0]RxWireDataIn;
wire    RxWireDataWEn;
reg     SIERxRdyOut, next_SIERxRdyOut;
 
// diagram signals declarations
reg  [1:0]RxBits, next_RxBits;
reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
reg  [7:0]RXWaitCount, next_RXWaitCount;
 
// BINARY ENCODED state machine: rcvr
// State codes definitions:
`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
`define LS_CONN_CHK_RX_BITS 4'b0010
`define DISCNCT_CHK_RXBITS 4'b0011
`define WAIT_BIT 4'b0100
`define START_SRX 4'b0101
`define LS_CONN_PROC_RX_BITS 4'b0110
`define FS_CONN_CHK_RX_BITS1 4'b0111
`define WAIT_LS_DIS_CHK_RX_BITS 4'b1000
`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
`define FS_CONN_PROC_RX_BITS1 4'b1100
 
reg [3:0]CurrState_rcvr, NextState_rcvr;
 
 
// Machine: rcvr
 
// NextState logic (combinatorial)
always @ (RXWaitCount or processRxBitRdyIn or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or processRxBitsWEn or RxBitsOut or SIERxRdyOut or CurrState_rcvr)
begin
  NextState_rcvr <= CurrState_rcvr;
  // Set default values for outputs and signals
  next_RXWaitCount <= RXWaitCount;
  next_connectState <= connectState;
  next_RXStMachCurrState <= RXStMachCurrState;
  next_processRxBitsWEn <= processRxBitsWEn;
  next_RxBitsOut <= RxBitsOut;
  next_RxBits <= RxBits;
  next_SIERxRdyOut <= SIERxRdyOut;
  case (CurrState_rcvr)  // synopsys parallel_case full_case
    `WAIT_BIT:
    begin
      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
      begin
        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
        next_SIERxRdyOut <= 1'b0;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
      begin
        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
        next_SIERxRdyOut <= 1'b0;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
      begin
        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
        next_RxBits <= RxWireDataIn;
        next_SIERxRdyOut <= 1'b0;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
      begin
        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
        next_SIERxRdyOut <= 1'b0;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
      begin
        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
        next_RxBits <= RxWireDataIn;
        next_SIERxRdyOut <= 1'b0;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
      begin
        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
        next_RxBits <= RxWireDataIn;
        next_SIERxRdyOut <= 1'b0;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
      begin
        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
        next_SIERxRdyOut <= 1'b0;
      end
    end
    `START_SRX:
    begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      next_RXWaitCount <= 8'h00;
      next_connectState <= `DISCONNECT;
      next_RxBits <= 2'b00;
      next_RxBitsOut <= 2'b00;
      next_processRxBitsWEn <= 1'b0;
      next_SIERxRdyOut <= 1'b1;
      NextState_rcvr <= `WAIT_BIT;
    end
    `DISCNCT_CHK_RXBITS:
    begin
      if (RxBits == `ZERO_ONE)
      begin
        NextState_rcvr <= `WAIT_BIT;
        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
        next_RXWaitCount <= 8'h00;
        next_SIERxRdyOut <= 1'b1;
      end
      else if (RxBits == `ONE_ZERO)
      begin
        NextState_rcvr <= `WAIT_BIT;
        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
        next_RXWaitCount <= 8'h00;
        next_SIERxRdyOut <= 1'b1;
      end
      else
      begin
        NextState_rcvr <= `WAIT_BIT;
        next_SIERxRdyOut <= 1'b1;
      end
    end
    `WAIT_FS_CONN_CHK_RX_BITS:
    begin
      if (RxBits == `ONE_ZERO)
      begin
      next_RXWaitCount <= RXWaitCount + 1'b1;
      if (RXWaitCount == `CONNECT_WAIT_TIME)
      begin
      next_connectState <= `FULL_SPEED_CONNECT;
      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
      end
      end
      else
      begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      end
      NextState_rcvr <= `WAIT_BIT;
      next_SIERxRdyOut <= 1'b1;
    end
    `WAIT_LS_CONN_CHK_RX_BITS:
    begin
      if (RxBits == `ZERO_ONE)
      begin
      next_RXWaitCount <= RXWaitCount + 1'b1;
      if (RXWaitCount == `CONNECT_WAIT_TIME)
      begin
      next_connectState <= `LOW_SPEED_CONNECT;
      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
      end
      end
      else
      begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      end
      NextState_rcvr <= `WAIT_BIT;
      next_SIERxRdyOut <= 1'b1;
    end
    `LS_CONN_CHK_RX_BITS:
    begin
      if (processRxBitRdyIn == 1'b1)
      begin
        NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
        if (RxBits == `SE0)
        begin
        next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
        next_RXWaitCount <= 0;
        end
        next_processRxBitsWEn <= 1'b1;
        next_RxBitsOut <= RxBits;
      end
    end
    `LS_CONN_PROC_RX_BITS:
    begin
      next_processRxBitsWEn <= 1'b0;
      NextState_rcvr <= `WAIT_BIT;
      next_SIERxRdyOut <= 1'b1;
    end
    `FS_CONN_CHK_RX_BITS1:
    begin
      if (processRxBitRdyIn == 1'b1)
      begin
        NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
        if (RxBits == `SE0)
        begin
        next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
        next_RXWaitCount <= 0;
        end
        next_processRxBitsWEn <= 1'b1;
        next_RxBitsOut <= RxBits;
        next_SIERxRdyOut <= 1'b1;
        //early indication of ready
      end
    end
    `FS_CONN_PROC_RX_BITS1:
    begin
      next_processRxBitsWEn <= 1'b0;
      NextState_rcvr <= `WAIT_BIT;
      next_SIERxRdyOut <= 1'b1;
    end
    `WAIT_LS_DIS_CHK_RX_BITS:
    begin
      if (processRxBitRdyIn == 1'b1)
      begin
        NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
        if (RxBits == `SE0)
        begin
        next_RXWaitCount <= RXWaitCount + 1'b1;
        if (RXWaitCount == `DISCONNECT_WAIT_TIME)
        begin
        next_RXStMachCurrState <= `DISCONNECT_ST;
        next_connectState <= `DISCONNECT;
        end
        end
        else
        begin
        next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
        end
        next_processRxBitsWEn <= 1'b1;
      end
    end
    `WAIT_LS_DIS_PROC_RX_BITS:
    begin
      next_processRxBitsWEn <= 1'b0;
      NextState_rcvr <= `WAIT_BIT;
      next_SIERxRdyOut <= 1'b1;
    end
    `WAIT_FS_DIS_PROC_RX_BITS2:
    begin
      next_processRxBitsWEn <= 1'b0;
      NextState_rcvr <= `WAIT_BIT;
      next_SIERxRdyOut <= 1'b1;
    end
    `WAIT_FS_DIS_CHK_RX_BITS2:
    begin
      if (processRxBitRdyIn == 1'b1)
      begin
        NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
        if (RxBits == `SE0)
        begin
        next_RXWaitCount <= RXWaitCount + 1'b1;
        if (RXWaitCount == `DISCONNECT_WAIT_TIME)
        begin
        next_RXStMachCurrState <= `DISCONNECT_ST;
        next_connectState <= `DISCONNECT;
        end
        end
        else
        begin
        next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
        end
        next_processRxBitsWEn <= 1'b1;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_rcvr <= `START_SRX;
  else
    CurrState_rcvr <= NextState_rcvr;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    connectState <= `DISCONNECT;
    processRxBitsWEn <= 1'b0;
    RxBitsOut <= 2'b00;
    SIERxRdyOut <= 1'b1;
    RXWaitCount <= 8'h00;
    RXStMachCurrState <= `DISCONNECT_ST;
    RxBits <= 2'b00;
  end
  else
  begin
    connectState <= next_connectState;
    processRxBitsWEn <= next_processRxBitsWEn;
    RxBitsOut <= next_RxBitsOut;
    SIERxRdyOut <= next_SIERxRdyOut;
    RXWaitCount <= next_RXWaitCount;
    RXStMachCurrState <= next_RXStMachCurrState;
    RxBits <= next_RxBits;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [siereceiver.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// SIEReceiver`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// $Id: siereceiver.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`timescale 1ns / 1ps
52			`include "usbSerialInterfaceEngine_h.v"
53
54
55			`module SIEReceiver (clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst, RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut);`
56			`input clk;`
57			`input processRxBitRdyIn;`
58			`input rst;`
59			`input [1:0]RxWireDataIn;`
60			`input RxWireDataWEn;`
61			`output [1:0]connectState;`
62			`output processRxBitsWEn;`
63			`output [1:0]RxBitsOut;`
64			`output SIERxRdyOut;`
65
66			`wire clk;`
67			`reg [1:0]connectState, next_connectState;`
68			`wire processRxBitRdyIn;`
69			`reg processRxBitsWEn, next_processRxBitsWEn;`
70			`wire rst;`
71			`reg [1:0]RxBitsOut, next_RxBitsOut;`
72			`wire [1:0]RxWireDataIn;`
73			`wire RxWireDataWEn;`
74			`reg SIERxRdyOut, next_SIERxRdyOut;`
75
76			`// diagram signals declarations`
77			`reg [1:0]RxBits, next_RxBits;`
78			`reg [3:0]RXStMachCurrState, next_RXStMachCurrState;`
79			`reg [7:0]RXWaitCount, next_RXWaitCount;`
80
81			`// BINARY ENCODED state machine: rcvr`
82			`// State codes definitions:`
83			`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
84			`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
85			`define LS_CONN_CHK_RX_BITS 4'b0010
86			`define DISCNCT_CHK_RXBITS 4'b0011
87			`define WAIT_BIT 4'b0100
88			`define START_SRX 4'b0101
89			`define LS_CONN_PROC_RX_BITS 4'b0110
90			`define FS_CONN_CHK_RX_BITS1 4'b0111
91			`define WAIT_LS_DIS_CHK_RX_BITS 4'b1000
92			`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
93			`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
94			`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
95			`define FS_CONN_PROC_RX_BITS1 4'b1100
96
97			`reg [3:0]CurrState_rcvr, NextState_rcvr;`
98
99
100			`// Machine: rcvr`
101
102			`// NextState logic (combinatorial)`
103			`always @ (RXWaitCount or processRxBitRdyIn or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or processRxBitsWEn or RxBitsOut or SIERxRdyOut or CurrState_rcvr)`
104			`begin`
105			`NextState_rcvr <= CurrState_rcvr;`
106			`// Set default values for outputs and signals`
107			`next_RXWaitCount <= RXWaitCount;`
108			`next_connectState <= connectState;`
109			`next_RXStMachCurrState <= RXStMachCurrState;`
110			`next_processRxBitsWEn <= processRxBitsWEn;`
111			`next_RxBitsOut <= RxBitsOut;`
112			`next_RxBits <= RxBits;`
113			`next_SIERxRdyOut <= SIERxRdyOut;`
114			`case (CurrState_rcvr) // synopsys parallel_case full_case`
115			`WAIT_BIT:
116			`begin`
117			if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
118			`begin`
119			NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
120			`next_RxBits <= RxWireDataIn;`
121			`next_SIERxRdyOut <= 1'b0;`
122			`end`
123			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
124			`begin`
125			NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
126			`next_RxBits <= RxWireDataIn;`
127			`next_SIERxRdyOut <= 1'b0;`
128			`end`
129			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
130			`begin`
131			NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
132			`next_RxBits <= RxWireDataIn;`
133			`next_SIERxRdyOut <= 1'b0;`
134			`end`
135			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
136			`begin`
137			NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
138			`next_RxBits <= RxWireDataIn;`
139			`next_SIERxRdyOut <= 1'b0;`
140			`end`
141			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
142			`begin`
143			NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
144			`next_RxBits <= RxWireDataIn;`
145			`next_SIERxRdyOut <= 1'b0;`
146			`end`
147			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
148			`begin`
149			NextState_rcvr <= `DISCNCT_CHK_RXBITS;
150			`next_RxBits <= RxWireDataIn;`
151			`next_SIERxRdyOut <= 1'b0;`
152			`end`
153			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
154			`begin`
155			NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
156			`next_RxBits <= RxWireDataIn;`
157			`next_SIERxRdyOut <= 1'b0;`
158			`end`
159			`end`
160			`START_SRX:
161			`begin`
162			next_RXStMachCurrState <= `DISCONNECT_ST;
163			`next_RXWaitCount <= 8'h00;`
164			next_connectState <= `DISCONNECT;
165			`next_RxBits <= 2'b00;`
166			`next_RxBitsOut <= 2'b00;`
167			`next_processRxBitsWEn <= 1'b0;`
168			`next_SIERxRdyOut <= 1'b1;`
169			NextState_rcvr <= `WAIT_BIT;
170			`end`
171			`DISCNCT_CHK_RXBITS:
172			`begin`
173			if (RxBits == `ZERO_ONE)
174			`begin`
175			NextState_rcvr <= `WAIT_BIT;
176			next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
177			`next_RXWaitCount <= 8'h00;`
178			`next_SIERxRdyOut <= 1'b1;`
179			`end`
180			else if (RxBits == `ONE_ZERO)
181			`begin`
182			NextState_rcvr <= `WAIT_BIT;
183			next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
184			`next_RXWaitCount <= 8'h00;`
185			`next_SIERxRdyOut <= 1'b1;`
186			`end`
187			`else`
188			`begin`
189			NextState_rcvr <= `WAIT_BIT;
190			`next_SIERxRdyOut <= 1'b1;`
191			`end`
192			`end`
193			`WAIT_FS_CONN_CHK_RX_BITS:
194			`begin`
195			if (RxBits == `ONE_ZERO)
196			`begin`
197			`next_RXWaitCount <= RXWaitCount + 1'b1;`
198			if (RXWaitCount == `CONNECT_WAIT_TIME)
199			`begin`
200			next_connectState <= `FULL_SPEED_CONNECT;
201			next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
202			`end`
203			`end`
204			`else`
205			`begin`
206			next_RXStMachCurrState <= `DISCONNECT_ST;
207			`end`
208			NextState_rcvr <= `WAIT_BIT;
209			`next_SIERxRdyOut <= 1'b1;`
210			`end`
211			`WAIT_LS_CONN_CHK_RX_BITS:
212			`begin`
213			if (RxBits == `ZERO_ONE)
214			`begin`
215			`next_RXWaitCount <= RXWaitCount + 1'b1;`
216			if (RXWaitCount == `CONNECT_WAIT_TIME)
217			`begin`
218			next_connectState <= `LOW_SPEED_CONNECT;
219			next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
220			`end`
221			`end`
222			`else`
223			`begin`
224			next_RXStMachCurrState <= `DISCONNECT_ST;
225			`end`
226			NextState_rcvr <= `WAIT_BIT;
227			`next_SIERxRdyOut <= 1'b1;`
228			`end`
229			`LS_CONN_CHK_RX_BITS:
230			`begin`
231			`if (processRxBitRdyIn == 1'b1)`
232			`begin`
233			NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
234			if (RxBits == `SE0)
235			`begin`
236			next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
237			`next_RXWaitCount <= 0;`
238			`end`
239			`next_processRxBitsWEn <= 1'b1;`
240			`next_RxBitsOut <= RxBits;`
241			`end`
242			`end`
243			`LS_CONN_PROC_RX_BITS:
244			`begin`
245			`next_processRxBitsWEn <= 1'b0;`
246			NextState_rcvr <= `WAIT_BIT;
247			`next_SIERxRdyOut <= 1'b1;`
248			`end`
249			`FS_CONN_CHK_RX_BITS1:
250			`begin`
251			`if (processRxBitRdyIn == 1'b1)`
252			`begin`
253			NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
254			if (RxBits == `SE0)
255			`begin`
256			next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
257			`next_RXWaitCount <= 0;`
258			`end`
259			`next_processRxBitsWEn <= 1'b1;`
260			`next_RxBitsOut <= RxBits;`
261			`next_SIERxRdyOut <= 1'b1;`
262			`//early indication of ready`
263			`end`
264			`end`
265			`FS_CONN_PROC_RX_BITS1:
266			`begin`
267			`next_processRxBitsWEn <= 1'b0;`
268			NextState_rcvr <= `WAIT_BIT;
269			`next_SIERxRdyOut <= 1'b1;`
270			`end`
271			`WAIT_LS_DIS_CHK_RX_BITS:
272			`begin`
273			`if (processRxBitRdyIn == 1'b1)`
274			`begin`
275			NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
276			if (RxBits == `SE0)
277			`begin`
278			`next_RXWaitCount <= RXWaitCount + 1'b1;`
279			if (RXWaitCount == `DISCONNECT_WAIT_TIME)
280			`begin`
281			next_RXStMachCurrState <= `DISCONNECT_ST;
282			next_connectState <= `DISCONNECT;
283			`end`
284			`end`
285			`else`
286			`begin`
287			next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
288			`end`
289			`next_processRxBitsWEn <= 1'b1;`
290			`end`
291			`end`
292			`WAIT_LS_DIS_PROC_RX_BITS:
293			`begin`
294			`next_processRxBitsWEn <= 1'b0;`
295			NextState_rcvr <= `WAIT_BIT;
296			`next_SIERxRdyOut <= 1'b1;`
297			`end`
298			`WAIT_FS_DIS_PROC_RX_BITS2:
299			`begin`
300			`next_processRxBitsWEn <= 1'b0;`
301			NextState_rcvr <= `WAIT_BIT;
302			`next_SIERxRdyOut <= 1'b1;`
303			`end`
304			`WAIT_FS_DIS_CHK_RX_BITS2:
305			`begin`
306			`if (processRxBitRdyIn == 1'b1)`
307			`begin`
308			NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
309			if (RxBits == `SE0)
310			`begin`
311			`next_RXWaitCount <= RXWaitCount + 1'b1;`
312			if (RXWaitCount == `DISCONNECT_WAIT_TIME)
313			`begin`
314			next_RXStMachCurrState <= `DISCONNECT_ST;
315			next_connectState <= `DISCONNECT;
316			`end`
317			`end`
318			`else`
319			`begin`
320			next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
321			`end`
322			`next_processRxBitsWEn <= 1'b1;`
323			`end`
324			`end`
325			`endcase`
326			`end`
327
328			`// Current State Logic (sequential)`
329			`always @ (posedge clk)`
330			`begin`
331			`if (rst)`
332			CurrState_rcvr <= `START_SRX;
333			`else`
334			`CurrState_rcvr <= NextState_rcvr;`
335			`end`
336
337			`// Registered outputs logic`
338			`always @ (posedge clk)`
339			`begin`
340			`if (rst)`
341			`begin`
342			connectState <= `DISCONNECT;
343			`processRxBitsWEn <= 1'b0;`
344			`RxBitsOut <= 2'b00;`
345			`SIERxRdyOut <= 1'b1;`
346			`RXWaitCount <= 8'h00;`
347			RXStMachCurrState <= `DISCONNECT_ST;
348			`RxBits <= 2'b00;`
349			`end`
350			`else`
351			`begin`
352			`connectState <= next_connectState;`
353			`processRxBitsWEn <= next_processRxBitsWEn;`
354			`RxBitsOut <= next_RxBitsOut;`
355			`SIERxRdyOut <= next_SIERxRdyOut;`
356			`RXWaitCount <= next_RXWaitCount;`
357			`RXStMachCurrState <= next_RXStMachCurrState;`
358			`RxBits <= next_RxBits;`
359			`end`
360			`end`
361
362	2	sfielding	`endmodule`