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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [writeUSBWireData.v] - Blame information for rev 43

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// writeUSBWireData.v                                           ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
 
`define BUFFER_FULL  3'b100
 
module writeUSBWireData (
  TxBitsIn,
  TxBitsOut,
   TxDataOutTick,
  TxCtrlIn,
  TxCtrlOut,
  USBWireRdy,
  USBWireWEn,
  TxWireActiveDrive,
  fullSpeedRate,
  clk,
  rst
   );
 
input   [1:0] TxBitsIn;
input   TxCtrlIn;
input   USBWireWEn;
input   clk;
input   fullSpeedRate;
input   rst;
output  [1:0] TxBitsOut;
output TxDataOutTick;
output  TxCtrlOut;
output  USBWireRdy;
output  TxWireActiveDrive;
 
wire    [1:0] TxBitsIn;
reg     [1:0] TxBitsOut;
reg     TxDataOutTick;
wire    TxCtrlIn;
reg     TxCtrlOut;
reg     USBWireRdy;
wire    USBWireWEn;
wire    clk;
wire    fullSpeedRate;
wire    rst;
reg     TxWireActiveDrive;
 
// local registers
reg  [3:0]buffer0;
reg  [3:0]buffer1;
reg  [3:0]buffer2;
reg  [3:0]buffer3;
reg  [2:0]bufferCnt;
reg  [1:0]bufferInIndex;
reg  [1:0]bufferOutIndex;
reg decBufferCnt;
reg  [4:0]i;
reg incBufferCnt;
reg fullSpeedTick;
reg lowSpeedTick;
reg fullSpeedRate_reg;
 
// buffer in state machine state codes:
`define WAIT_BUFFER_NOT_FULL 2'b00
`define WAIT_WRITE_REQ 2'b01
`define CLR_INC_BUFFER_CNT 2'b10
 
// buffer output state machine state codes:
`define WAIT_BUFFER_FULL 2'b00
`define WAIT_LINE_WRITE 2'b01
`define LINE_WRITE 2'b10
 
reg [1:0] bufferInStMachCurrState;
reg [1:0] bufferOutStMachCurrState;
 
// buffer control
always @(posedge clk)
begin
  if (rst == 1'b1)
  begin
    bufferCnt <= 3'b000;
  end
  else
  begin
    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
      bufferCnt <= bufferCnt + 1'b1;
    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
      bufferCnt <= bufferCnt - 1'b1;
  end
end
 
 
//buffer input state machine 
always @(posedge clk) begin
  if (rst == 1'b1) begin
     incBufferCnt <= 1'b0;
    bufferInIndex <= 2'b00;
    buffer0 <= 4'b0000;
    buffer1 <= 4'b0000;
    buffer2 <= 4'b0000;
    buffer3 <= 4'b0000;
    USBWireRdy <= 1'b0;
    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
  end
  else begin
    case (bufferInStMachCurrState)
      `WAIT_BUFFER_NOT_FULL:
      begin
        if (bufferCnt != `BUFFER_FULL)
        begin
          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
          USBWireRdy <= 1'b1;
        end
      end
      `WAIT_WRITE_REQ:
      begin
        if (USBWireWEn == 1'b1)
        begin
          incBufferCnt <= 1'b1;
          USBWireRdy <= 1'b0;
          bufferInIndex <= bufferInIndex + 1'b1;
          case (bufferInIndex)
            2'b00 : buffer0 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
            2'b01 : buffer1 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
            2'b10 : buffer2 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
            2'b11 : buffer3 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
          endcase
          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
        end
      end
      `CLR_INC_BUFFER_CNT:
      begin
        incBufferCnt <= 1'b0;
        if (bufferCnt != (`BUFFER_FULL - 1'b1) )
        begin
          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
          USBWireRdy <= 1'b1;
        end
        else begin
          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
        end
      end
    endcase
  end
end
 
//increment counter used to generate USB bit rate
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    i <= 5'b00000;
    fullSpeedTick <= 1'b0;
    lowSpeedTick <= 1'b0;
  end
  else
  begin
    i <= i + 1'b1;
    if (i[1:0] == 2'b00)
      fullSpeedTick <= 1'b1;
    else
      fullSpeedTick <= 1'b0;
    if (i == 5'b00000)
      lowSpeedTick <= 1'b1;
    else
      lowSpeedTick <= 1'b0;
  end
end
 
//buffer output state machine
//buffer is constantly emptied at either
//the full or low speed rate
//if the buffer is empty, then the output is forced to tri-state
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    bufferOutIndex <= 2'b00;
    decBufferCnt <= 1'b0;
    TxBitsOut <= 2'b00;
    TxCtrlOut <= `TRI_STATE;
    TxDataOutTick <= 1'b0;
    bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
    fullSpeedRate_reg <= 1'b0;
  end
  else
  begin
    case (bufferOutIndex)
      2'b00: fullSpeedRate_reg <= buffer0[3];
      2'b01: fullSpeedRate_reg <= buffer1[3];
      2'b10: fullSpeedRate_reg <= buffer2[3];
      2'b11: fullSpeedRate_reg <= buffer3[3];
    endcase
    case (bufferOutStMachCurrState)
      `WAIT_LINE_WRITE:
      begin
        if ((fullSpeedRate_reg == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate_reg == 1'b0 && lowSpeedTick == 1'b1) )
        begin
          TxDataOutTick <= !TxDataOutTick;
          if (bufferCnt == 0) begin
            TxBitsOut <= 2'b00;
            TxCtrlOut <= `TRI_STATE;
          end
          else begin
            bufferOutStMachCurrState <= `LINE_WRITE;
            decBufferCnt <= 1'b1;
            bufferOutIndex <= bufferOutIndex + 1'b1;
            case (bufferOutIndex)
              2'b00 :
            begin
              TxBitsOut <= buffer0[2:1];
              TxCtrlOut <= buffer0[0];
            end
            2'b01 :
            begin
              TxBitsOut <= buffer1[2:1];
              TxCtrlOut <= buffer1[0];
            end
            2'b10 :
            begin
              TxBitsOut <= buffer2[2:1];
              TxCtrlOut <= buffer2[0];
            end
            2'b11 :
            begin
              TxBitsOut <= buffer3[2:1];
              TxCtrlOut <= buffer3[0];
            end
            endcase
          end
        end
      end
      `LINE_WRITE:
      begin
        decBufferCnt <= 1'b0;
        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
      end
    endcase
  end
end
 
// control 'TxWireActiveDrive' 
always @(TxCtrlOut)
begin
  if (TxCtrlOut == `DRIVE)
    TxWireActiveDrive <= 1'b1;
  else
    TxWireActiveDrive <= 1'b0;
end
 
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [writeUSBWireData.v] - Blame information for rev 43

Line No.	Rev	Author	Line
1	43	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// writeUSBWireData.v ////`
4			`//// ////`
5			`//// This file is part of the usbhostslave opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`////`
10			`//// ////`
11			`//// To Do: ////`
12			`////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Steve Fielding, sfielding@base2designs.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from <http://www.opencores.org/lgpl.shtml> ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`include "timescale.v"
45			`include "usbSerialInterfaceEngine_h.v"
46
47			`define BUFFER_FULL 3'b100
48
49			`module writeUSBWireData (`
50			`TxBitsIn,`
51			`TxBitsOut,`
52			`TxDataOutTick,`
53			`TxCtrlIn,`
54			`TxCtrlOut,`
55			`USBWireRdy,`
56			`USBWireWEn,`
57			`TxWireActiveDrive,`
58			`fullSpeedRate,`
59			`clk,`
60			`rst`
61			`);`
62
63			`input [1:0] TxBitsIn;`
64			`input TxCtrlIn;`
65			`input USBWireWEn;`
66			`input clk;`
67			`input fullSpeedRate;`
68			`input rst;`
69			`output [1:0] TxBitsOut;`
70			`output TxDataOutTick;`
71			`output TxCtrlOut;`
72			`output USBWireRdy;`
73			`output TxWireActiveDrive;`
74
75			`wire [1:0] TxBitsIn;`
76			`reg [1:0] TxBitsOut;`
77			`reg TxDataOutTick;`
78			`wire TxCtrlIn;`
79			`reg TxCtrlOut;`
80			`reg USBWireRdy;`
81			`wire USBWireWEn;`
82			`wire clk;`
83			`wire fullSpeedRate;`
84			`wire rst;`
85			`reg TxWireActiveDrive;`
86
87			`// local registers`
88			`reg [3:0]buffer0;`
89			`reg [3:0]buffer1;`
90			`reg [3:0]buffer2;`
91			`reg [3:0]buffer3;`
92			`reg [2:0]bufferCnt;`
93			`reg [1:0]bufferInIndex;`
94			`reg [1:0]bufferOutIndex;`
95			`reg decBufferCnt;`
96			`reg [4:0]i;`
97			`reg incBufferCnt;`
98			`reg fullSpeedTick;`
99			`reg lowSpeedTick;`
100			`reg fullSpeedRate_reg;`
101
102			`// buffer in state machine state codes:`
103			`define WAIT_BUFFER_NOT_FULL 2'b00
104			`define WAIT_WRITE_REQ 2'b01
105			`define CLR_INC_BUFFER_CNT 2'b10
106
107			`// buffer output state machine state codes:`
108			`define WAIT_BUFFER_FULL 2'b00
109			`define WAIT_LINE_WRITE 2'b01
110			`define LINE_WRITE 2'b10
111
112			`reg [1:0] bufferInStMachCurrState;`
113			`reg [1:0] bufferOutStMachCurrState;`
114
115			`// buffer control`
116			`always @(posedge clk)`
117			`begin`
118			`if (rst == 1'b1)`
119			`begin`
120			`bufferCnt <= 3'b000;`
121			`end`
122			`else`
123			`begin`
124			`if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)`
125			`bufferCnt <= bufferCnt + 1'b1;`
126			`else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)`
127			`bufferCnt <= bufferCnt - 1'b1;`
128			`end`
129			`end`
130
131
132			`//buffer input state machine`
133			`always @(posedge clk) begin`
134			`if (rst == 1'b1) begin`
135			`incBufferCnt <= 1'b0;`
136			`bufferInIndex <= 2'b00;`
137			`buffer0 <= 4'b0000;`
138			`buffer1 <= 4'b0000;`
139			`buffer2 <= 4'b0000;`
140			`buffer3 <= 4'b0000;`
141			`USBWireRdy <= 1'b0;`
142			bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
143			`end`
144			`else begin`
145			`case (bufferInStMachCurrState)`
146			`WAIT_BUFFER_NOT_FULL:
147			`begin`
148			if (bufferCnt != `BUFFER_FULL)
149			`begin`
150			bufferInStMachCurrState <= `WAIT_WRITE_REQ;
151			`USBWireRdy <= 1'b1;`
152			`end`
153			`end`
154			`WAIT_WRITE_REQ:
155			`begin`
156			`if (USBWireWEn == 1'b1)`
157			`begin`
158			`incBufferCnt <= 1'b1;`
159			`USBWireRdy <= 1'b0;`
160			`bufferInIndex <= bufferInIndex + 1'b1;`
161			`case (bufferInIndex)`
162			`2'b00 : buffer0 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};`
163			`2'b01 : buffer1 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};`
164			`2'b10 : buffer2 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};`
165			`2'b11 : buffer3 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};`
166			`endcase`
167			bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
168			`end`
169			`end`
170			`CLR_INC_BUFFER_CNT:
171			`begin`
172			`incBufferCnt <= 1'b0;`
173			if (bufferCnt != (`BUFFER_FULL - 1'b1) )
174			`begin`
175			bufferInStMachCurrState <= `WAIT_WRITE_REQ;
176			`USBWireRdy <= 1'b1;`
177			`end`
178			`else begin`
179			bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
180			`end`
181			`end`
182			`endcase`
183			`end`
184			`end`
185
186			`//increment counter used to generate USB bit rate`
187			`always @(posedge clk) begin`
188			`if (rst == 1'b1)`
189			`begin`
190			`i <= 5'b00000;`
191			`fullSpeedTick <= 1'b0;`
192			`lowSpeedTick <= 1'b0;`
193			`end`
194			`else`
195			`begin`
196			`i <= i + 1'b1;`
197			`if (i[1:0] == 2'b00)`
198			`fullSpeedTick <= 1'b1;`
199			`else`
200			`fullSpeedTick <= 1'b0;`
201			`if (i == 5'b00000)`
202			`lowSpeedTick <= 1'b1;`
203			`else`
204			`lowSpeedTick <= 1'b0;`
205			`end`
206			`end`
207
208			`//buffer output state machine`
209			`//buffer is constantly emptied at either`
210			`//the full or low speed rate`
211			`//if the buffer is empty, then the output is forced to tri-state`
212			`always @(posedge clk) begin`
213			`if (rst == 1'b1)`
214			`begin`
215			`bufferOutIndex <= 2'b00;`
216			`decBufferCnt <= 1'b0;`
217			`TxBitsOut <= 2'b00;`
218			TxCtrlOut <= `TRI_STATE;
219			`TxDataOutTick <= 1'b0;`
220			bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
221			`fullSpeedRate_reg <= 1'b0;`
222			`end`
223			`else`
224			`begin`
225			`case (bufferOutIndex)`
226			`2'b00: fullSpeedRate_reg <= buffer0[3];`
227			`2'b01: fullSpeedRate_reg <= buffer1[3];`
228			`2'b10: fullSpeedRate_reg <= buffer2[3];`
229			`2'b11: fullSpeedRate_reg <= buffer3[3];`
230			`endcase`
231			`case (bufferOutStMachCurrState)`
232			`WAIT_LINE_WRITE:
233			`begin`
234			`if ((fullSpeedRate_reg == 1'b1 && fullSpeedTick == 1'b1) \|\| (fullSpeedRate_reg == 1'b0 && lowSpeedTick == 1'b1) )`
235			`begin`
236			`TxDataOutTick <= !TxDataOutTick;`
237			`if (bufferCnt == 0) begin`
238			`TxBitsOut <= 2'b00;`
239			TxCtrlOut <= `TRI_STATE;
240			`end`
241			`else begin`
242			bufferOutStMachCurrState <= `LINE_WRITE;
243			`decBufferCnt <= 1'b1;`
244			`bufferOutIndex <= bufferOutIndex + 1'b1;`
245			`case (bufferOutIndex)`
246			`2'b00 :`
247			`begin`
248			`TxBitsOut <= buffer0[2:1];`
249			`TxCtrlOut <= buffer0[0];`
250			`end`
251			`2'b01 :`
252			`begin`
253			`TxBitsOut <= buffer1[2:1];`
254			`TxCtrlOut <= buffer1[0];`
255			`end`
256			`2'b10 :`
257			`begin`
258			`TxBitsOut <= buffer2[2:1];`
259			`TxCtrlOut <= buffer2[0];`
260			`end`
261			`2'b11 :`
262			`begin`
263			`TxBitsOut <= buffer3[2:1];`
264			`TxCtrlOut <= buffer3[0];`
265			`end`
266			`endcase`
267			`end`
268			`end`
269			`end`
270			`LINE_WRITE:
271			`begin`
272			`decBufferCnt <= 1'b0;`
273			bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
274			`end`
275			`endcase`
276			`end`
277			`end`
278
279			`// control 'TxWireActiveDrive'`
280			`always @(TxCtrlOut)`
281			`begin`
282			if (TxCtrlOut == `DRIVE)
283			`TxWireActiveDrive <= 1'b1;`
284			`else`
285			`TxWireActiveDrive <= 1'b0;`
286			`end`
287
288
289			`endmodule`