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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [writeUSBWireData.v] - Blame information for rev 7

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// writeUSBWireData.v                                           ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: writeUSBWireData.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2004/10/11 04:01:05  sfielding
// Created
//
//
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
`define BUFFER_FULL  3'b100
 
module writeUSBWireData (
  TxBitsIn,
  TxBitsOut,
   TxDataOutTick,
  TxCtrlIn,
  TxCtrlOut,
  USBWireRdy,
  USBWireWEn,
  disableWireReadOut,
  fullSpeedRate,
  clk,
  rst,
  noActivityTimeOut );
 
input   [1:0] TxBitsIn;
input   TxCtrlIn;
input   USBWireWEn;
input   clk;
input   fullSpeedRate;
input   rst;
output  [1:0] TxBitsOut;
output TxDataOutTick;
output  TxCtrlOut;
output  USBWireRdy;
output  disableWireReadOut;
output noActivityTimeOut;
 
wire    [1:0] TxBitsIn;
reg     [1:0] TxBitsOut;
reg     TxDataOutTick;
wire    TxCtrlIn;
reg     TxCtrlOut;
reg     USBWireRdy;
wire    USBWireWEn;
wire    clk;
wire    fullSpeedRate;
wire    rst;
reg  disableWireReadOut;
reg noActivityTimeOut;
 
// local registers
reg  [2:0]buffer0;
reg  [2:0]buffer1;
reg  [2:0]buffer2;
reg  [2:0]buffer3;
reg  [2:0]bufferCnt;
reg  [1:0]bufferInIndex;
reg  [1:0]bufferOutIndex;
reg decBufferCnt;
reg  [4:0]i;
reg incBufferCnt;
reg fullSpeedTick;
reg lowSpeedTick;
reg [15:0] timeOutCnt;
 
// buffer in state machine state codes:
`define WAIT_BUFFER_NOT_FULL 2'b00
`define WAIT_WRITE_REQ 2'b01
`define CLR_INC_BUFFER_CNT 2'b10
 
// buffer output state machine state codes:
`define WAIT_BUFFER_FULL 2'b00
`define WAIT_LINE_WRITE 2'b01
`define LINE_WRITE 2'b10
 
reg [1:0] bufferInStMachCurrState;
reg [1:0] bufferOutStMachCurrState;
 
// buffer control
always @(posedge clk)
begin
  if (rst == 1'b1)
  begin
    bufferCnt <= 3'b000;
  end
  else
  begin
    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
      bufferCnt <= bufferCnt + 1'b1;
    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
      bufferCnt <= bufferCnt - 1'b1;
  end
end
 
 
//buffer input state machine 
always @(posedge clk) begin
  if (rst == 1'b1) begin
     incBufferCnt <= 1'b0;
    bufferInIndex <= 2'b00;
    buffer0 <= 3'b000;
    buffer1 <= 3'b000;
    buffer2 <= 3'b000;
    buffer3 <= 3'b000;
    USBWireRdy <= 1'b0;
    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
  end
  else begin
    case (bufferInStMachCurrState)
      `WAIT_BUFFER_NOT_FULL:
      begin
        if (bufferCnt != `BUFFER_FULL)
        begin
          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
          USBWireRdy <= 1'b1;
        end
      end
      `WAIT_WRITE_REQ:
      begin
        if (USBWireWEn == 1'b1)
        begin
          incBufferCnt <= 1'b1;
          USBWireRdy <= 1'b0;
          bufferInIndex <= bufferInIndex + 1'b1;
          case (bufferInIndex)
            2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
            2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
            2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
            2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
          endcase
          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
        end
      end
      `CLR_INC_BUFFER_CNT:
      begin
        incBufferCnt <= 1'b0;
        if (bufferCnt != (`BUFFER_FULL - 1'b1) )
        begin
          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
          USBWireRdy <= 1'b1;
        end
        else begin
          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
        end
      end
    endcase
  end
end
 
//increment counter used to generate USB bit rate
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    i <= 5'b00000;
    fullSpeedTick <= 1'b0;
    lowSpeedTick <= 1'b0;
  end
  else
  begin
    i <= i + 1'b1;
    if (i[1:0] == 2'b00)
      fullSpeedTick <= 1'b1;
    else
      fullSpeedTick <= 1'b0;
    if (i == 5'b00000)
      lowSpeedTick <= 1'b1;
    else
      lowSpeedTick <= 1'b0;
  end
end
 
//buffer output state machine
//After reset, waits for the output buffer to become full.
//Once the buffer is full then it is constantly emptied at either
//the full or low speed rate with no under run protection
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    bufferOutIndex <= 2'b00;
    decBufferCnt <= 1'b0;
    TxBitsOut <= 2'b00;
    TxCtrlOut <= `TRI_STATE;
    TxDataOutTick <= 1'b0;
    bufferOutStMachCurrState <= `WAIT_BUFFER_FULL;
  end
  else
  begin
    case (bufferOutStMachCurrState)
      `WAIT_BUFFER_FULL:
      begin
        if (bufferCnt == `BUFFER_FULL)
          bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
      end
      `WAIT_LINE_WRITE:
      begin
        if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
        begin
          TxDataOutTick <= !TxDataOutTick;
          bufferOutStMachCurrState <= `LINE_WRITE;
          decBufferCnt <= 1'b1;
          bufferOutIndex <= bufferOutIndex + 1'b1;
          case (bufferOutIndex)
            2'b00 :
          begin
            TxBitsOut <= buffer0[2:1];
            TxCtrlOut <= buffer0[0];
          end
          2'b01 :
          begin
            TxBitsOut <= buffer1[2:1];
            TxCtrlOut <= buffer1[0];
          end
          2'b10 :
          begin
            TxBitsOut <= buffer2[2:1];
            TxCtrlOut <= buffer2[0];
          end
          2'b11 :
          begin
            TxBitsOut <= buffer3[2:1];
            TxCtrlOut <= buffer3[0];
          end
          endcase
        end
      end
      `LINE_WRITE:
      begin
        decBufferCnt <= 1'b0;
        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
      end
    endcase
  end
end
 
// control 'disableWireReadOut' 
always @(TxCtrlOut)
begin
  if (TxCtrlOut == `DRIVE)
    disableWireReadOut <= 1'b1;
  else
    disableWireReadOut <= 1'b0;
end
 
//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks
always @(posedge clk) begin
  if (rst) begin
    timeOutCnt <= 16'h0000;
    noActivityTimeOut <= 1'b0;
  end
  else begin
    if (TxCtrlOut == `DRIVE)
      timeOutCnt <= 16'h0000;
    else
      timeOutCnt <= timeOutCnt + 1'b1;
    //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
    if (timeOutCnt == 16'h200)  //temporary fix
      noActivityTimeOut <= 1'b1;
    else
      noActivityTimeOut <= 1'b0;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// writeUSBWireData.v ////`
4			`//// ////`
5			`//// This file is part of the usbhostslave opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`////`
10			`//// ////`
11			`//// To Do: ////`
12			`////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Steve Fielding, sfielding@base2designs.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from <http://www.opencores.org/lgpl.shtml> ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44	7	sfielding	`// $Id: writeUSBWireData.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $`
45	2	sfielding	`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	5	sfielding	`// Revision 1.1.1.1 2004/10/11 04:01:05 sfielding`
50			`// Created`
51	2	sfielding	`//`
52	5	sfielding	`//`
53	2	sfielding
54			`timescale 1ns / 1ps
55			`include "usbSerialInterfaceEngine_h.v"
56
57			`define BUFFER_FULL 3'b100
58
59			`module writeUSBWireData (`
60			`TxBitsIn,`
61			`TxBitsOut,`
62	5	sfielding	`TxDataOutTick,`
63	2	sfielding	`TxCtrlIn,`
64			`TxCtrlOut,`
65			`USBWireRdy,`
66			`USBWireWEn,`
67			`disableWireReadOut,`
68			`fullSpeedRate,`
69			`clk,`
70			`rst,`
71			`noActivityTimeOut );`
72
73			`input [1:0] TxBitsIn;`
74			`input TxCtrlIn;`
75			`input USBWireWEn;`
76			`input clk;`
77			`input fullSpeedRate;`
78			`input rst;`
79			`output [1:0] TxBitsOut;`
80			`output TxDataOutTick;`
81			`output TxCtrlOut;`
82			`output USBWireRdy;`
83			`output disableWireReadOut;`
84			`output noActivityTimeOut;`
85
86			`wire [1:0] TxBitsIn;`
87			`reg [1:0] TxBitsOut;`
88			`reg TxDataOutTick;`
89			`wire TxCtrlIn;`
90			`reg TxCtrlOut;`
91			`reg USBWireRdy;`
92			`wire USBWireWEn;`
93			`wire clk;`
94			`wire fullSpeedRate;`
95			`wire rst;`
96			`reg disableWireReadOut;`
97			`reg noActivityTimeOut;`
98
99			`// local registers`
100			`reg [2:0]buffer0;`
101			`reg [2:0]buffer1;`
102			`reg [2:0]buffer2;`
103			`reg [2:0]buffer3;`
104			`reg [2:0]bufferCnt;`
105			`reg [1:0]bufferInIndex;`
106			`reg [1:0]bufferOutIndex;`
107			`reg decBufferCnt;`
108			`reg [4:0]i;`
109			`reg incBufferCnt;`
110			`reg fullSpeedTick;`
111			`reg lowSpeedTick;`
112			`reg [15:0] timeOutCnt;`
113
114			`// buffer in state machine state codes:`
115			`define WAIT_BUFFER_NOT_FULL 2'b00
116			`define WAIT_WRITE_REQ 2'b01
117			`define CLR_INC_BUFFER_CNT 2'b10
118
119			`// buffer output state machine state codes:`
120			`define WAIT_BUFFER_FULL 2'b00
121			`define WAIT_LINE_WRITE 2'b01
122			`define LINE_WRITE 2'b10
123
124			`reg [1:0] bufferInStMachCurrState;`
125			`reg [1:0] bufferOutStMachCurrState;`
126
127			`// buffer control`
128			`always @(posedge clk)`
129			`begin`
130			`if (rst == 1'b1)`
131			`begin`
132			`bufferCnt <= 3'b000;`
133	5	sfielding	`end`
134	2	sfielding	`else`
135			`begin`
136			`if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)`
137			`bufferCnt <= bufferCnt + 1'b1;`
138			`else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)`
139			`bufferCnt <= bufferCnt - 1'b1;`
140			`end`
141			`end`
142
143
144			`//buffer input state machine`
145			`always @(posedge clk) begin`
146			`if (rst == 1'b1) begin`
147	5	sfielding	`incBufferCnt <= 1'b0;`
148			`bufferInIndex <= 2'b00;`
149			`buffer0 <= 3'b000;`
150			`buffer1 <= 3'b000;`
151			`buffer2 <= 3'b000;`
152			`buffer3 <= 3'b000;`
153			`USBWireRdy <= 1'b0;`
154			bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
155			`end`
156	2	sfielding	`else begin`
157	5	sfielding	`case (bufferInStMachCurrState)`
158			`WAIT_BUFFER_NOT_FULL:
159			`begin`
160			if (bufferCnt != `BUFFER_FULL)
161			`begin`
162			bufferInStMachCurrState <= `WAIT_WRITE_REQ;
163			`USBWireRdy <= 1'b1;`
164			`end`
165			`end`
166			`WAIT_WRITE_REQ:
167			`begin`
168			`if (USBWireWEn == 1'b1)`
169			`begin`
170			`incBufferCnt <= 1'b1;`
171			`USBWireRdy <= 1'b0;`
172			`bufferInIndex <= bufferInIndex + 1'b1;`
173			`case (bufferInIndex)`
174			`2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};`
175			`2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};`
176			`2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};`
177			`2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};`
178			`endcase`
179			bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
180			`end`
181			`end`
182			`CLR_INC_BUFFER_CNT:
183			`begin`
184			`incBufferCnt <= 1'b0;`
185			if (bufferCnt != (`BUFFER_FULL - 1'b1) )
186			`begin`
187			bufferInStMachCurrState <= `WAIT_WRITE_REQ;
188			`USBWireRdy <= 1'b1;`
189			`end`
190	2	sfielding	`else begin`
191	5	sfielding	bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
192	2	sfielding	`end`
193	5	sfielding	`end`
194			`endcase`
195	2	sfielding	`end`
196			`end`
197	5	sfielding
198	2	sfielding	`//increment counter used to generate USB bit rate`
199			`always @(posedge clk) begin`
200			`if (rst == 1'b1)`
201			`begin`
202			`i <= 5'b00000;`
203			`fullSpeedTick <= 1'b0;`
204			`lowSpeedTick <= 1'b0;`
205			`end`
206			`else`
207			`begin`
208			`i <= i + 1'b1;`
209			`if (i[1:0] == 2'b00)`
210			`fullSpeedTick <= 1'b1;`
211			`else`
212			`fullSpeedTick <= 1'b0;`
213			`if (i == 5'b00000)`
214			`lowSpeedTick <= 1'b1;`
215			`else`
216			`lowSpeedTick <= 1'b0;`
217			`end`
218			`end`
219
220			`//buffer output state machine`
221			`//After reset, waits for the output buffer to become full.`
222			`//Once the buffer is full then it is constantly emptied at either`
223			`//the full or low speed rate with no under run protection`
224			`always @(posedge clk) begin`
225			`if (rst == 1'b1)`
226			`begin`
227	5	sfielding	`bufferOutIndex <= 2'b00;`
228			`decBufferCnt <= 1'b0;`
229			`TxBitsOut <= 2'b00;`
230			TxCtrlOut <= `TRI_STATE;
231	2	sfielding	`TxDataOutTick <= 1'b0;`
232	5	sfielding	bufferOutStMachCurrState <= `WAIT_BUFFER_FULL;
233			`end`
234	2	sfielding	`else`
235			`begin`
236	5	sfielding	`case (bufferOutStMachCurrState)`
237			`WAIT_BUFFER_FULL:
238			`begin`
239			if (bufferCnt == `BUFFER_FULL)
240			bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
241			`end`
242			`WAIT_LINE_WRITE:
243			`begin`
244			`if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) \|\| (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )`
245			`begin`
246	2	sfielding	`TxDataOutTick <= !TxDataOutTick;`
247	5	sfielding	bufferOutStMachCurrState <= `LINE_WRITE;
248			`decBufferCnt <= 1'b1;`
249			`bufferOutIndex <= bufferOutIndex + 1'b1;`
250			`case (bufferOutIndex)`
251			`2'b00 :`
252			`begin`
253			`TxBitsOut <= buffer0[2:1];`
254			`TxCtrlOut <= buffer0[0];`
255			`end`
256			`2'b01 :`
257			`begin`
258			`TxBitsOut <= buffer1[2:1];`
259			`TxCtrlOut <= buffer1[0];`
260			`end`
261			`2'b10 :`
262			`begin`
263			`TxBitsOut <= buffer2[2:1];`
264			`TxCtrlOut <= buffer2[0];`
265			`end`
266			`2'b11 :`
267			`begin`
268			`TxBitsOut <= buffer3[2:1];`
269			`TxCtrlOut <= buffer3[0];`
270			`end`
271			`endcase`
272			`end`
273			`end`
274			`LINE_WRITE:
275			`begin`
276			`decBufferCnt <= 1'b0;`
277			bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
278			`end`
279			`endcase`
280	2	sfielding	`end`
281			`end`
282
283			`// control 'disableWireReadOut'`
284			`always @(TxCtrlOut)`
285	5	sfielding	`begin`
286			if (TxCtrlOut == `DRIVE)
287			`disableWireReadOut <= 1'b1;`
288			`else`
289			`disableWireReadOut <= 1'b0;`
290	2	sfielding	`end`
291
292			`//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks`
293			`always @(posedge clk) begin`
294			`if (rst) begin`
295			`timeOutCnt <= 16'h0000;`
296			`noActivityTimeOut <= 1'b0;`
297			`end`
298			`else begin`
299			if (TxCtrlOut == `DRIVE)
300			`timeOutCnt <= 16'h0000;`
301			`else`
302			`timeOutCnt <= timeOutCnt + 1'b1;`
303			//if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
304			`if (timeOutCnt == 16'h200) //temporary fix`
305			`noActivityTimeOut <= 1'b1;`
306			`else`
307			`noActivityTimeOut <= 1'b0;`
308			`end`
309			`end`
310
311			`endmodule`

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