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sfielding |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// USBSlaveControlBI.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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sfielding |
////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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44 |
9 |
sfielding |
`timescale 1ns / 1ps
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45 |
2 |
sfielding |
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46 |
9 |
sfielding |
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47 |
2 |
sfielding |
`include "usbSlaveControl_h.v"
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48 |
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49 |
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module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
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50 |
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strobe_i,
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51 |
18 |
sfielding |
busClk,
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52 |
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rstSyncToBusClk,
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53 |
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usbClk,
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54 |
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rstSyncToUsbClk,
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55 |
5 |
sfielding |
SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
|
56 |
2 |
sfielding |
endP0TransTypeReg, endP0NAKTransTypeReg,
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57 |
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endP1TransTypeReg, endP1NAKTransTypeReg,
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58 |
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endP2TransTypeReg, endP2NAKTransTypeReg,
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59 |
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endP3TransTypeReg, endP3NAKTransTypeReg,
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60 |
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endP0ControlReg,
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61 |
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endP1ControlReg,
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62 |
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endP2ControlReg,
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63 |
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endP3ControlReg,
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64 |
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EP0StatusReg,
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65 |
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EP1StatusReg,
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66 |
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EP2StatusReg,
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67 |
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EP3StatusReg,
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68 |
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SCAddrReg, frameNum,
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69 |
5 |
sfielding |
connectStateIn,
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70 |
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SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
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71 |
2 |
sfielding |
slaveControlSelect,
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72 |
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clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
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73 |
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TxLineState,
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74 |
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LineDirectControlEn,
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75 |
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fullSpeedPol,
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76 |
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fullSpeedRate,
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77 |
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SCGlobalEn
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78 |
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);
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79 |
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input [4:0] address;
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80 |
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input [7:0] dataIn;
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81 |
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input writeEn;
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82 |
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input strobe_i;
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83 |
18 |
sfielding |
input busClk;
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84 |
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input rstSyncToBusClk;
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85 |
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input usbClk;
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86 |
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input rstSyncToUsbClk;
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87 |
2 |
sfielding |
output [7:0] dataOut;
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88 |
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output SOFRxedIntOut;
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89 |
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output resetEventIntOut;
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90 |
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output resumeIntOut;
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91 |
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output transDoneIntOut;
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92 |
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output NAKSentIntOut;
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93 |
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94 |
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input [1:0] endP0TransTypeReg;
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95 |
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input [1:0] endP0NAKTransTypeReg;
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96 |
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input [1:0] endP1TransTypeReg;
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97 |
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input [1:0] endP1NAKTransTypeReg;
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98 |
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input [1:0] endP2TransTypeReg;
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99 |
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input [1:0] endP2NAKTransTypeReg;
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100 |
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input [1:0] endP3TransTypeReg;
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101 |
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input [1:0] endP3NAKTransTypeReg;
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102 |
14 |
sfielding |
output [4:0] endP0ControlReg;
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103 |
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output [4:0] endP1ControlReg;
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104 |
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output [4:0] endP2ControlReg;
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105 |
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output [4:0] endP3ControlReg;
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106 |
2 |
sfielding |
input [7:0] EP0StatusReg;
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107 |
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input [7:0] EP1StatusReg;
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108 |
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input [7:0] EP2StatusReg;
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109 |
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input [7:0] EP3StatusReg;
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110 |
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output [6:0] SCAddrReg;
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111 |
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input [10:0] frameNum;
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112 |
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input [1:0] connectStateIn;
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113 |
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input SOFRxedIn;
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114 |
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input resetEventIn;
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115 |
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input resumeIntIn;
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116 |
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input transDoneIn;
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117 |
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input NAKSentIn;
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118 |
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input slaveControlSelect;
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119 |
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input clrEP0Ready;
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120 |
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input clrEP1Ready;
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121 |
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input clrEP2Ready;
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122 |
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input clrEP3Ready;
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123 |
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output [1:0] TxLineState;
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124 |
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output LineDirectControlEn;
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125 |
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output fullSpeedPol;
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126 |
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output fullSpeedRate;
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127 |
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output SCGlobalEn;
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128 |
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129 |
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wire [4:0] address;
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wire [7:0] dataIn;
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131 |
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wire writeEn;
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132 |
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wire strobe_i;
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133 |
18 |
sfielding |
wire busClk;
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134 |
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wire rstSyncToBusClk;
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135 |
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wire usbClk;
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136 |
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wire rstSyncToUsbClk;
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137 |
2 |
sfielding |
reg [7:0] dataOut;
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138 |
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reg SOFRxedIntOut;
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140 |
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reg resetEventIntOut;
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141 |
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reg resumeIntOut;
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142 |
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reg transDoneIntOut;
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143 |
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reg NAKSentIntOut;
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144 |
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145 |
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wire [1:0] endP0TransTypeReg;
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146 |
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wire [1:0] endP0NAKTransTypeReg;
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147 |
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wire [1:0] endP1TransTypeReg;
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148 |
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wire [1:0] endP1NAKTransTypeReg;
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149 |
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wire [1:0] endP2TransTypeReg;
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150 |
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wire [1:0] endP2NAKTransTypeReg;
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151 |
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wire [1:0] endP3TransTypeReg;
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152 |
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wire [1:0] endP3NAKTransTypeReg;
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153 |
14 |
sfielding |
reg [4:0] endP0ControlReg;
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154 |
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reg [4:0] endP1ControlReg;
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155 |
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reg [4:0] endP2ControlReg;
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156 |
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reg [4:0] endP3ControlReg;
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157 |
2 |
sfielding |
wire [7:0] EP0StatusReg;
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158 |
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wire [7:0] EP1StatusReg;
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159 |
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wire [7:0] EP2StatusReg;
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wire [7:0] EP3StatusReg;
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reg [6:0] SCAddrReg;
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162 |
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reg [3:0] TxEndPReg;
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163 |
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wire [10:0] frameNum;
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wire [1:0] connectStateIn;
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wire SOFRxedIn;
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wire resetEventIn;
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wire resumeIntIn;
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wire transDoneIn;
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170 |
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wire NAKSentIn;
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wire slaveControlSelect;
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wire clrEP0Ready;
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wire clrEP1Ready;
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wire clrEP2Ready;
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wire clrEP3Ready;
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reg [1:0] TxLineState;
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reg LineDirectControlEn;
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reg fullSpeedPol;
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reg fullSpeedRate;
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reg SCGlobalEn;
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//internal wire and regs
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reg [5:0] SCControlReg;
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reg clrNAKReq;
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reg clrSOFReq;
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reg clrResetReq;
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reg clrResInReq;
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reg clrTransDoneReq;
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reg SOFRxedInt;
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reg resetEventInt;
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reg resumeInt;
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reg transDoneInt;
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reg NAKSentInt;
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reg [4:0] interruptMaskReg;
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reg EP0SetReady;
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reg EP1SetReady;
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reg EP2SetReady;
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reg EP3SetReady;
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reg EP0SendStall;
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reg EP1SendStall;
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201 |
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reg EP2SendStall;
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reg EP3SendStall;
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203 |
14 |
sfielding |
reg EP0IsoEn;
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204 |
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reg EP1IsoEn;
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205 |
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reg EP2IsoEn;
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reg EP3IsoEn;
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207 |
2 |
sfielding |
reg EP0DataSequence;
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208 |
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reg EP1DataSequence;
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reg EP2DataSequence;
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reg EP3DataSequence;
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reg EP0Enable;
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reg EP1Enable;
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reg EP2Enable;
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reg EP3Enable;
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reg EP0Ready;
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216 |
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reg EP1Ready;
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217 |
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reg EP2Ready;
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218 |
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reg EP3Ready;
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219 |
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220 |
18 |
sfielding |
//clock domain crossing sync registers
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221 |
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//STB = Sync To Busclk
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222 |
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reg [4:0] endP0ControlRegSTB;
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reg [4:0] endP1ControlRegSTB;
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reg [4:0] endP2ControlRegSTB;
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reg [4:0] endP3ControlRegSTB;
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reg NAKSentInSTB;
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reg SOFRxedInSTB;
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reg resetEventInSTB;
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reg resumeIntInSTB;
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reg transDoneInSTB;
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reg clrEP0ReadySTB;
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reg clrEP1ReadySTB;
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reg clrEP2ReadySTB;
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reg clrEP3ReadySTB;
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reg SCGlobalEnSTB;
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reg [1:0] TxLineStateSTB;
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reg LineDirectControlEnSTB;
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reg fullSpeedPolSTB;
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reg fullSpeedRateSTB;
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reg [7:0] EP0StatusRegSTB;
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reg [7:0] EP1StatusRegSTB;
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reg [7:0] EP2StatusRegSTB;
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reg [7:0] EP3StatusRegSTB;
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244 |
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reg [1:0] endP0TransTypeRegSTB;
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245 |
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reg [1:0] endP0NAKTransTypeRegSTB;
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246 |
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reg [1:0] endP1TransTypeRegSTB;
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247 |
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reg [1:0] endP1NAKTransTypeRegSTB;
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248 |
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reg [1:0] endP2TransTypeRegSTB;
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249 |
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reg [1:0] endP2NAKTransTypeRegSTB;
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250 |
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reg [1:0] endP3TransTypeRegSTB;
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251 |
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reg [1:0] endP3NAKTransTypeRegSTB;
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252 |
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reg [10:0] frameNumSTB;
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253 |
2 |
sfielding |
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254 |
18 |
sfielding |
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255 |
2 |
sfielding |
//sync write demux
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256 |
18 |
sfielding |
always @(posedge busClk)
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257 |
14 |
sfielding |
begin
|
258 |
18 |
sfielding |
if (rstSyncToBusClk == 1'b1) begin
|
259 |
14 |
sfielding |
EP0IsoEn <= 1'b0;
|
260 |
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EP0SendStall <= 1'b0;
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261 |
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EP0DataSequence <= 1'b0;
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262 |
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EP0Enable <= 1'b0;
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263 |
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EP1IsoEn <= 1'b0;
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264 |
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EP1SendStall <= 1'b0;
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265 |
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EP1DataSequence <= 1'b0;
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266 |
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EP1Enable <= 1'b0;
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267 |
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EP2IsoEn <= 1'b0;
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268 |
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EP2SendStall <= 1'b0;
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269 |
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EP2DataSequence <= 1'b0;
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270 |
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EP2Enable <= 1'b0;
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271 |
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EP3IsoEn <= 1'b0;
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272 |
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EP3SendStall <= 1'b0;
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273 |
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EP3DataSequence <= 1'b0;
|
274 |
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EP3Enable <= 1'b0;
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275 |
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SCControlReg <= 6'h00;
|
276 |
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SCAddrReg <= 7'h00;
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277 |
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interruptMaskReg <= 5'h00;
|
278 |
5 |
sfielding |
end
|
279 |
14 |
sfielding |
else begin
|
280 |
|
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clrNAKReq <= 1'b0;
|
281 |
|
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clrSOFReq <= 1'b0;
|
282 |
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clrResetReq <= 1'b0;
|
283 |
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clrResInReq <= 1'b0;
|
284 |
|
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clrTransDoneReq <= 1'b0;
|
285 |
|
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EP0SetReady <= 1'b0;
|
286 |
|
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EP1SetReady <= 1'b0;
|
287 |
|
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EP2SetReady <= 1'b0;
|
288 |
|
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EP3SetReady <= 1'b0;
|
289 |
|
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if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
|
290 |
|
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begin
|
291 |
|
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case (address)
|
292 |
|
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`EP0_CTRL_REG : begin
|
293 |
|
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EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
|
294 |
|
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EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
|
295 |
|
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EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
|
296 |
|
|
EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
|
297 |
|
|
EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
|
298 |
|
|
end
|
299 |
|
|
`EP1_CTRL_REG : begin
|
300 |
|
|
EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
|
301 |
|
|
EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
|
302 |
|
|
EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
|
303 |
|
|
EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
|
304 |
|
|
EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
|
305 |
|
|
end
|
306 |
|
|
`EP2_CTRL_REG : begin
|
307 |
|
|
EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
|
308 |
|
|
EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
|
309 |
|
|
EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
|
310 |
|
|
EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
|
311 |
|
|
EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
|
312 |
|
|
end
|
313 |
|
|
`EP3_CTRL_REG : begin
|
314 |
|
|
EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
|
315 |
|
|
EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
|
316 |
|
|
EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
|
317 |
|
|
EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
|
318 |
|
|
EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
|
319 |
|
|
end
|
320 |
|
|
`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
|
321 |
|
|
`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
|
322 |
|
|
`SC_INTERRUPT_STATUS_REG : begin
|
323 |
|
|
clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
|
324 |
|
|
clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
|
325 |
|
|
clrResetReq <= dataIn[`RESET_EVENT_BIT];
|
326 |
|
|
clrResInReq <= dataIn[`RESUME_INT_BIT];
|
327 |
|
|
clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
|
328 |
|
|
end
|
329 |
|
|
`SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
|
330 |
|
|
endcase
|
331 |
|
|
end
|
332 |
|
|
end
|
333 |
2 |
sfielding |
end
|
334 |
|
|
|
335 |
|
|
//interrupt control
|
336 |
18 |
sfielding |
always @(posedge busClk)
|
337 |
2 |
sfielding |
begin
|
338 |
18 |
sfielding |
if (rstSyncToBusClk == 1'b1) begin
|
339 |
14 |
sfielding |
NAKSentInt <= 1'b0;
|
340 |
5 |
sfielding |
SOFRxedInt <= 1'b0;
|
341 |
|
|
resetEventInt <= 1'b0;
|
342 |
14 |
sfielding |
resumeInt <= 1'b0;
|
343 |
|
|
transDoneInt <= 1'b0;
|
344 |
|
|
end
|
345 |
|
|
else begin
|
346 |
18 |
sfielding |
if (NAKSentInSTB == 1'b1)
|
347 |
14 |
sfielding |
NAKSentInt <= 1'b1;
|
348 |
|
|
else if (clrNAKReq == 1'b1)
|
349 |
|
|
NAKSentInt <= 1'b0;
|
350 |
5 |
sfielding |
|
351 |
18 |
sfielding |
if (SOFRxedInSTB == 1'b1)
|
352 |
14 |
sfielding |
SOFRxedInt <= 1'b1;
|
353 |
|
|
else if (clrSOFReq == 1'b1)
|
354 |
|
|
SOFRxedInt <= 1'b0;
|
355 |
|
|
|
356 |
18 |
sfielding |
if (resetEventInSTB == 1'b1)
|
357 |
14 |
sfielding |
resetEventInt <= 1'b1;
|
358 |
|
|
else if (clrResetReq == 1'b1)
|
359 |
|
|
resetEventInt <= 1'b0;
|
360 |
|
|
|
361 |
18 |
sfielding |
if (resumeIntInSTB == 1'b1)
|
362 |
14 |
sfielding |
resumeInt <= 1'b1;
|
363 |
|
|
else if (clrResInReq == 1'b1)
|
364 |
|
|
resumeInt <= 1'b0;
|
365 |
2 |
sfielding |
|
366 |
18 |
sfielding |
if (transDoneInSTB == 1'b1)
|
367 |
14 |
sfielding |
transDoneInt <= 1'b1;
|
368 |
|
|
else if (clrTransDoneReq == 1'b1)
|
369 |
|
|
transDoneInt <= 1'b0;
|
370 |
|
|
end
|
371 |
2 |
sfielding |
end
|
372 |
|
|
|
373 |
|
|
//mask interrupts
|
374 |
|
|
always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
|
375 |
|
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
376 |
|
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
377 |
|
|
resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
|
378 |
|
|
SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
|
379 |
|
|
NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
|
380 |
|
|
end
|
381 |
|
|
|
382 |
|
|
//end point ready, set/clear
|
383 |
18 |
sfielding |
//Since 'busClk' can be a higher freq than 'usbClk',
|
384 |
|
|
//'EP0SetReady' etc must be delayed with respect to other control signals, thus
|
385 |
|
|
//ensuring that control signals have been clocked through to 'usbClk' clock
|
386 |
|
|
//domain before the ready is asserted.
|
387 |
|
|
//Not sure this is required because there is at least two 'usbClk' ticks between
|
388 |
|
|
//detection of 'EP0Ready' and sampling of related control signals.always @(posedge busClk)
|
389 |
|
|
always @(posedge busClk)
|
390 |
2 |
sfielding |
begin
|
391 |
18 |
sfielding |
if (rstSyncToBusClk == 1'b1) begin
|
392 |
5 |
sfielding |
EP0Ready <= 1'b0;
|
393 |
|
|
EP1Ready <= 1'b0;
|
394 |
|
|
EP2Ready <= 1'b0;
|
395 |
14 |
sfielding |
EP3Ready <= 1'b0;
|
396 |
|
|
end
|
397 |
|
|
else begin
|
398 |
|
|
if (EP0SetReady == 1'b1)
|
399 |
|
|
EP0Ready <= 1'b1;
|
400 |
18 |
sfielding |
else if (clrEP0ReadySTB == 1'b1)
|
401 |
14 |
sfielding |
EP0Ready <= 1'b0;
|
402 |
2 |
sfielding |
|
403 |
14 |
sfielding |
if (EP1SetReady == 1'b1)
|
404 |
|
|
EP1Ready <= 1'b1;
|
405 |
18 |
sfielding |
else if (clrEP1ReadySTB == 1'b1)
|
406 |
14 |
sfielding |
EP1Ready <= 1'b0;
|
407 |
|
|
|
408 |
|
|
if (EP2SetReady == 1'b1)
|
409 |
|
|
EP2Ready <= 1'b1;
|
410 |
18 |
sfielding |
else if (clrEP2ReadySTB == 1'b1)
|
411 |
14 |
sfielding |
EP2Ready <= 1'b0;
|
412 |
|
|
|
413 |
|
|
if (EP3SetReady == 1'b1)
|
414 |
|
|
EP3Ready <= 1'b1;
|
415 |
18 |
sfielding |
else if (clrEP3ReadySTB == 1'b1)
|
416 |
14 |
sfielding |
EP3Ready <= 1'b0;
|
417 |
|
|
end
|
418 |
2 |
sfielding |
end
|
419 |
|
|
|
420 |
|
|
//break out control signals
|
421 |
|
|
always @(SCControlReg) begin
|
422 |
18 |
sfielding |
SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
|
423 |
|
|
TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
|
424 |
|
|
LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
|
425 |
|
|
fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
|
426 |
|
|
fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
|
427 |
2 |
sfielding |
end
|
428 |
|
|
|
429 |
|
|
//combine endpoint control signals
|
430 |
14 |
sfielding |
always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
431 |
|
|
EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
432 |
|
|
EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
433 |
|
|
EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
|
434 |
2 |
sfielding |
begin
|
435 |
18 |
sfielding |
endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
|
436 |
|
|
endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
|
437 |
|
|
endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
|
438 |
|
|
endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
|
439 |
2 |
sfielding |
end
|
440 |
|
|
|
441 |
|
|
|
442 |
18 |
sfielding |
// async read mux
|
443 |
|
|
// FIX ME
|
444 |
|
|
// Not sure why 'EP0SendStall' etc are in sensitivity list. May be related to
|
445 |
|
|
// some translation bug
|
446 |
2 |
sfielding |
always @(address or
|
447 |
|
|
EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
448 |
|
|
EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
449 |
|
|
EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
450 |
|
|
EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
|
451 |
18 |
sfielding |
EP0StatusRegSTB or EP1StatusRegSTB or EP2StatusRegSTB or EP3StatusRegSTB or
|
452 |
|
|
endP0ControlRegSTB or endP1ControlRegSTB or endP2ControlRegSTB or endP3ControlRegSTB or
|
453 |
|
|
endP0NAKTransTypeRegSTB or endP1NAKTransTypeRegSTB or endP2NAKTransTypeRegSTB or endP3NAKTransTypeRegSTB or
|
454 |
|
|
endP0TransTypeRegSTB or endP1TransTypeRegSTB or endP2TransTypeRegSTB or endP3TransTypeRegSTB or
|
455 |
2 |
sfielding |
SCControlReg or connectStateIn or
|
456 |
|
|
NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
|
457 |
18 |
sfielding |
interruptMaskReg or SCAddrReg or frameNumSTB)
|
458 |
2 |
sfielding |
begin
|
459 |
5 |
sfielding |
case (address)
|
460 |
18 |
sfielding |
`EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
|
461 |
|
|
`EP0_STS_REG : dataOut <= EP0StatusRegSTB;
|
462 |
|
|
`EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
|
463 |
|
|
`EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
|
464 |
|
|
`EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
|
465 |
|
|
`EP1_STS_REG : dataOut <= EP1StatusRegSTB;
|
466 |
|
|
`EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
|
467 |
|
|
`EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
|
468 |
|
|
`EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
|
469 |
|
|
`EP2_STS_REG : dataOut <= EP2StatusRegSTB;
|
470 |
|
|
`EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
|
471 |
|
|
`EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
|
472 |
|
|
`EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
|
473 |
|
|
`EP3_STS_REG : dataOut <= EP3StatusRegSTB;
|
474 |
|
|
`EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
|
475 |
|
|
`EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
|
476 |
5 |
sfielding |
`SC_CONTROL_REG : dataOut <= SCControlReg;
|
477 |
|
|
`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
|
478 |
|
|
`SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
|
479 |
|
|
`SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
|
480 |
|
|
`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
|
481 |
18 |
sfielding |
`SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
|
482 |
|
|
`SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
|
483 |
2 |
sfielding |
default: dataOut <= 8'h00;
|
484 |
5 |
sfielding |
endcase
|
485 |
2 |
sfielding |
end
|
486 |
|
|
|
487 |
18 |
sfielding |
//re-sync from busClk to usbClk.
|
488 |
|
|
always @(posedge usbClk) begin
|
489 |
|
|
endP0ControlReg <= endP0ControlRegSTB;
|
490 |
|
|
endP1ControlReg <= endP1ControlRegSTB;
|
491 |
|
|
endP2ControlReg <= endP2ControlRegSTB;
|
492 |
|
|
endP3ControlReg <= endP3ControlRegSTB;
|
493 |
|
|
SCGlobalEn <= SCGlobalEnSTB;
|
494 |
|
|
TxLineState <= TxLineStateSTB;
|
495 |
|
|
LineDirectControlEn <= LineDirectControlEnSTB;
|
496 |
|
|
fullSpeedPol <= fullSpeedPolSTB;
|
497 |
|
|
fullSpeedRate <= fullSpeedRateSTB;
|
498 |
|
|
end
|
499 |
2 |
sfielding |
|
500 |
18 |
sfielding |
//re-sync from usbClk to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc are only asserted
|
501 |
|
|
//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
|
502 |
|
|
always @(posedge busClk) begin
|
503 |
|
|
NAKSentInSTB <= NAKSentIn;
|
504 |
|
|
SOFRxedInSTB <= SOFRxedIn;
|
505 |
|
|
resetEventInSTB <= resetEventIn;
|
506 |
|
|
resumeIntInSTB <= resumeIntIn;
|
507 |
|
|
transDoneInSTB <= transDoneIn;
|
508 |
|
|
clrEP0ReadySTB <= clrEP0Ready;
|
509 |
|
|
clrEP1ReadySTB <= clrEP1Ready;
|
510 |
|
|
clrEP2ReadySTB <= clrEP2Ready;
|
511 |
|
|
clrEP3ReadySTB <= clrEP3Ready;
|
512 |
|
|
EP0StatusRegSTB <= EP0StatusReg;
|
513 |
|
|
EP1StatusRegSTB <= EP1StatusReg;
|
514 |
|
|
EP2StatusRegSTB <= EP2StatusReg;
|
515 |
|
|
EP3StatusRegSTB <= EP3StatusReg;
|
516 |
|
|
endP0TransTypeRegSTB <= endP0TransTypeReg;
|
517 |
|
|
endP1TransTypeRegSTB <= endP1TransTypeReg;
|
518 |
|
|
endP2TransTypeRegSTB <= endP2TransTypeReg;
|
519 |
|
|
endP3TransTypeRegSTB <= endP3TransTypeReg;
|
520 |
|
|
endP0NAKTransTypeRegSTB <= endP0NAKTransTypeReg;
|
521 |
|
|
endP1NAKTransTypeRegSTB <= endP1NAKTransTypeReg;
|
522 |
|
|
endP2NAKTransTypeRegSTB <= endP2NAKTransTypeReg;
|
523 |
|
|
endP3NAKTransTypeRegSTB <= endP3NAKTransTypeReg;
|
524 |
|
|
frameNumSTB <= frameNum;
|
525 |
|
|
end
|
526 |
|
|
|
527 |
|
|
endmodule
|