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sfielding |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// USBSlaveControlBI.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: USBSlaveControlBI.v,v 1.1.1.1 2004-10-11 04:01:10 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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`include "usbSlaveControl_h.v"
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module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
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strobe_i,
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clk, rst,
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SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
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endP0TransTypeReg, endP0NAKTransTypeReg,
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endP1TransTypeReg, endP1NAKTransTypeReg,
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endP2TransTypeReg, endP2NAKTransTypeReg,
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endP3TransTypeReg, endP3NAKTransTypeReg,
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endP0ControlReg,
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endP1ControlReg,
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endP2ControlReg,
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endP3ControlReg,
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EP0StatusReg,
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EP1StatusReg,
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EP2StatusReg,
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EP3StatusReg,
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SCAddrReg, frameNum,
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connectStateIn,
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SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
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slaveControlSelect,
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clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
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TxLineState,
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LineDirectControlEn,
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fullSpeedPol,
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fullSpeedRate,
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SCGlobalEn
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);
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input [4:0] address;
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input [7:0] dataIn;
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input writeEn;
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input strobe_i;
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input clk;
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input rst;
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output [7:0] dataOut;
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output SOFRxedIntOut;
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output resetEventIntOut;
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output resumeIntOut;
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output transDoneIntOut;
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output NAKSentIntOut;
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input [1:0] endP0TransTypeReg;
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input [1:0] endP0NAKTransTypeReg;
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input [1:0] endP1TransTypeReg;
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input [1:0] endP1NAKTransTypeReg;
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input [1:0] endP2TransTypeReg;
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input [1:0] endP2NAKTransTypeReg;
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input [1:0] endP3TransTypeReg;
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input [1:0] endP3NAKTransTypeReg;
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output [3:0] endP0ControlReg;
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output [3:0] endP1ControlReg;
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output [3:0] endP2ControlReg;
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output [3:0] endP3ControlReg;
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input [7:0] EP0StatusReg;
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input [7:0] EP1StatusReg;
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input [7:0] EP2StatusReg;
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input [7:0] EP3StatusReg;
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output [6:0] SCAddrReg;
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input [10:0] frameNum;
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input [1:0] connectStateIn;
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input SOFRxedIn;
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input resetEventIn;
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input resumeIntIn;
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input transDoneIn;
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input NAKSentIn;
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input slaveControlSelect;
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input clrEP0Ready;
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input clrEP1Ready;
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input clrEP2Ready;
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input clrEP3Ready;
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output [1:0] TxLineState;
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output LineDirectControlEn;
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output fullSpeedPol;
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output fullSpeedRate;
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output SCGlobalEn;
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wire [4:0] address;
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wire [7:0] dataIn;
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wire writeEn;
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wire strobe_i;
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wire clk;
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wire rst;
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reg [7:0] dataOut;
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reg SOFRxedIntOut;
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reg resetEventIntOut;
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reg resumeIntOut;
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reg transDoneIntOut;
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reg NAKSentIntOut;
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wire [1:0] endP0TransTypeReg;
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wire [1:0] endP0NAKTransTypeReg;
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wire [1:0] endP1TransTypeReg;
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wire [1:0] endP1NAKTransTypeReg;
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wire [1:0] endP2TransTypeReg;
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wire [1:0] endP2NAKTransTypeReg;
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wire [1:0] endP3TransTypeReg;
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wire [1:0] endP3NAKTransTypeReg;
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reg [3:0] endP0ControlReg;
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reg [3:0] endP1ControlReg;
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reg [3:0] endP2ControlReg;
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reg [3:0] endP3ControlReg;
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wire [7:0] EP0StatusReg;
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wire [7:0] EP1StatusReg;
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wire [7:0] EP2StatusReg;
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wire [7:0] EP3StatusReg;
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reg [6:0] SCAddrReg;
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reg [3:0] TxEndPReg;
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wire [10:0] frameNum;
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wire [1:0] connectStateIn;
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wire SOFRxedIn;
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wire resetEventIn;
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wire resumeIntIn;
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wire transDoneIn;
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wire NAKSentIn;
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wire slaveControlSelect;
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wire clrEP0Ready;
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wire clrEP1Ready;
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wire clrEP2Ready;
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wire clrEP3Ready;
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reg [1:0] TxLineState;
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reg LineDirectControlEn;
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reg fullSpeedPol;
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reg fullSpeedRate;
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reg SCGlobalEn;
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//internal wire and regs
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reg [5:0] SCControlReg;
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reg clrNAKReq;
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reg clrSOFReq;
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reg clrResetReq;
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reg clrResInReq;
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reg clrTransDoneReq;
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reg SOFRxedInt;
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reg resetEventInt;
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reg resumeInt;
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reg transDoneInt;
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reg NAKSentInt;
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reg [4:0] interruptMaskReg;
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reg EP0SetReady;
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reg EP1SetReady;
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reg EP2SetReady;
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reg EP3SetReady;
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reg EP0SendStall;
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reg EP1SendStall;
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reg EP2SendStall;
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reg EP3SendStall;
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reg EP0DataSequence;
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reg EP1DataSequence;
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reg EP2DataSequence;
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reg EP3DataSequence;
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reg EP0Enable;
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reg EP1Enable;
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reg EP2Enable;
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reg EP3Enable;
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reg EP0Ready;
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reg EP1Ready;
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reg EP2Ready;
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reg EP3Ready;
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//sync write demux
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always @(posedge clk)
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begin
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clrNAKReq <= 1'b0;
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clrSOFReq <= 1'b0;
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clrResetReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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EP0SetReady <= 1'b0;
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EP1SetReady <= 1'b0;
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EP2SetReady <= 1'b0;
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EP3SetReady <= 1'b0;
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if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
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begin
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case (address)
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`EP0_CTRL_REG : begin
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EP0SendStall <= dataIn[3];
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EP0DataSequence <= dataIn[2];
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EP0SetReady <= dataIn[1];
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EP0Enable <= dataIn[0];
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end
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`EP1_CTRL_REG : begin
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EP1SendStall <= dataIn[3];
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EP1DataSequence <= dataIn[2];
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EP1SetReady <= dataIn[1];
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EP1Enable <= dataIn[0];
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end
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`EP2_CTRL_REG : begin
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EP2SendStall <= dataIn[3];
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EP2DataSequence <= dataIn[2];
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EP2SetReady <= dataIn[1];
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EP2Enable <= dataIn[0];
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end
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`EP3_CTRL_REG : begin
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EP3SendStall <= dataIn[3];
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EP3DataSequence <= dataIn[2];
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EP3SetReady <= dataIn[1];
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EP3Enable <= dataIn[0];
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end
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`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
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`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
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`SC_INTERRUPT_STATUS_REG : begin
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clrNAKReq <= dataIn[4];
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clrSOFReq <= dataIn[3];
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clrResetReq <= dataIn[2];
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clrResInReq <= dataIn[1];
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clrTransDoneReq <= dataIn[0];
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end
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`SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
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endcase
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end
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end
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//interrupt control
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always @(posedge clk)
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begin
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if (NAKSentIn == 1'b1)
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NAKSentInt <= 1'b1;
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else if (clrNAKReq == 1'b1)
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NAKSentInt <= 1'b0;
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if (SOFRxedIn == 1'b1)
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SOFRxedInt <= 1'b1;
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else if (clrSOFReq == 1'b1)
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SOFRxedInt <= 1'b0;
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if (resetEventIn == 1'b1)
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resetEventInt <= 1'b1;
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else if (clrResetReq == 1'b1)
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resetEventInt <= 1'b0;
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if (resumeIntIn == 1'b1)
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resumeInt <= 1'b1;
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else if (clrResInReq == 1'b1)
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resumeInt <= 1'b0;
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if (transDoneIn == 1'b1)
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transDoneInt <= 1'b1;
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else if (clrTransDoneReq == 1'b1)
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transDoneInt <= 1'b0;
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end
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//mask interrupts
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always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
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transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
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resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
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resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
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SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
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NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
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end
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//end point ready, set/clear
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always @(posedge clk)
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begin
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if (EP0SetReady == 1'b1)
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EP0Ready <= 1'b1;
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else if (clrEP0Ready == 1'b1)
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EP0Ready <= 1'b0;
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if (EP1SetReady == 1'b1)
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EP1Ready <= 1'b1;
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else if (clrEP1Ready == 1'b1)
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EP1Ready <= 1'b0;
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if (EP2SetReady == 1'b1)
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EP2Ready <= 1'b1;
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else if (clrEP2Ready == 1'b1)
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EP2Ready <= 1'b0;
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if (EP3SetReady == 1'b1)
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EP3Ready <= 1'b1;
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else if (clrEP3Ready == 1'b1)
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EP3Ready <= 1'b0;
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end
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//break out control signals
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always @(SCControlReg) begin
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SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
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TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
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LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
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fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
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fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
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end
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337 |
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//combine endpoint control signals
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339 |
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always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
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EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
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EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
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EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
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343 |
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begin
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344 |
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endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
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345 |
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endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
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346 |
|
|
endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
|
347 |
|
|
endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
|
348 |
|
|
end
|
349 |
|
|
|
350 |
|
|
|
351 |
|
|
// async read mux
|
352 |
|
|
always @(address or
|
353 |
|
|
EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
354 |
|
|
EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
355 |
|
|
EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
356 |
|
|
EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
|
357 |
|
|
EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
|
358 |
|
|
endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
|
359 |
|
|
endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or
|
360 |
|
|
endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
|
361 |
|
|
SCControlReg or connectStateIn or
|
362 |
|
|
NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
|
363 |
|
|
interruptMaskReg or SCAddrReg or frameNum)
|
364 |
|
|
begin
|
365 |
|
|
case (address)
|
366 |
|
|
`EP0_CTRL_REG : dataOut <= endP0ControlReg;
|
367 |
|
|
`EP0_STS_REG : dataOut <= EP0StatusReg;
|
368 |
|
|
`EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
|
369 |
|
|
`EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
|
370 |
|
|
`EP1_CTRL_REG : dataOut <= endP1ControlReg;
|
371 |
|
|
`EP1_STS_REG : dataOut <= EP1StatusReg;
|
372 |
|
|
`EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
|
373 |
|
|
`EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
|
374 |
|
|
`EP2_CTRL_REG : dataOut <= endP2ControlReg;
|
375 |
|
|
`EP2_STS_REG : dataOut <= EP2StatusReg;
|
376 |
|
|
`EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
|
377 |
|
|
`EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
|
378 |
|
|
`EP3_CTRL_REG : dataOut <= endP3ControlReg;
|
379 |
|
|
`EP3_STS_REG : dataOut <= EP3StatusReg;
|
380 |
|
|
`EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
|
381 |
|
|
`EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
|
382 |
|
|
`SC_CONTROL_REG : dataOut <= SCControlReg;
|
383 |
|
|
`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
|
384 |
|
|
`SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
|
385 |
|
|
`SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
|
386 |
|
|
`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
|
387 |
|
|
`SC_FRAME_NUM_MSP : dataOut <= frameNum[10:3];
|
388 |
|
|
`SC_FRAME_NUM_LSP : dataOut <= {5'b00000, frameNum[2:0]};
|
389 |
|
|
default: dataOut <= 8'h00;
|
390 |
|
|
endcase
|
391 |
|
|
end
|
392 |
|
|
|
393 |
|
|
|
394 |
|
|
endmodule
|