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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [sctxportarbiter.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : Steve
// Company     : Base2Designs
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sctxportarbiter.v
// Generated   : 06/10/04 22:29:55
// From        : c:\projects\USBHostSlave\RTL\slaveController\sctxportarbiter.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
 
module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
input   SCTxPortRdyIn;
input   clk;
input   [7:0] directCntlCntl;
input   [7:0] directCntlData;
input   directCntlReq;
input   directCntlWEn;
input   rst;
input   [7:0] sendPacketCntl;
input   [7:0] sendPacketData;
input   sendPacketReq;
input   sendPacketWEn;
output  [7:0] SCTxPortCntl;
output  [7:0] SCTxPortData;
output  SCTxPortRdyOut;
output  SCTxPortWEnable;
output  directCntlGnt;
output  sendPacketGnt;
 
reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
reg     [7:0] SCTxPortData, next_SCTxPortData;
wire    SCTxPortRdyIn;
reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
reg     SCTxPortWEnable, next_SCTxPortWEnable;
wire    clk;
wire    [7:0] directCntlCntl;
wire    [7:0] directCntlData;
reg     directCntlGnt, next_directCntlGnt;
wire    directCntlReq;
wire    directCntlWEn;
wire    rst;
wire    [7:0] sendPacketCntl;
wire    [7:0] sendPacketData;
reg     sendPacketGnt, next_sendPacketGnt;
wire    sendPacketReq;
wire    sendPacketWEn;
 
// diagram signals declarations
reg muxDCEn, next_muxDCEn;
 
// BINARY ENCODED state machine: SCTxArb
// State codes definitions:
`define SARB1_WAIT_REQ 2'b00
`define SARB_SEND_PACKET 2'b01
`define SARB_DC 2'b10
`define START_SARB 2'b11
 
reg [1:0] CurrState_SCTxArb;
reg [1:0] NextState_SCTxArb;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// SOFController/directContol/sendPacket mux
always @(SCTxPortRdyIn)
begin
    SCTxPortRdyOut = SCTxPortRdyIn;
end
always @(muxDCEn or
                                 directCntlWEn or directCntlData or directCntlCntl or
                  directCntlWEn or directCntlData or directCntlCntl or
                                 sendPacketWEn or sendPacketData or sendPacketCntl)
begin
if (muxDCEn == 1'b1)
    begin
        SCTxPortWEnable <= directCntlWEn;
        SCTxPortData <= directCntlData;
        SCTxPortCntl <= directCntlCntl;
    end
else
    begin
        SCTxPortWEnable <= sendPacketWEn;
        SCTxPortData <= sendPacketData;
        SCTxPortCntl <= sendPacketCntl;
    end
end
 
 
//--------------------------------------------------------------------
// Machine: SCTxArb
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
begin : SCTxArb_NextState
        NextState_SCTxArb <= CurrState_SCTxArb;
        // Set default values for outputs and signals
        next_sendPacketGnt <= sendPacketGnt;
        next_muxDCEn <= muxDCEn;
        next_directCntlGnt <= directCntlGnt;
        case (CurrState_SCTxArb) // synopsys parallel_case full_case
                `SARB1_WAIT_REQ:
                        if (sendPacketReq == 1'b1)
                        begin
                                NextState_SCTxArb <= `SARB_SEND_PACKET;
                                next_sendPacketGnt <= 1'b1;
                                next_muxDCEn <= 1'b0;
                        end
                        else if (directCntlReq == 1'b1)
                        begin
                                NextState_SCTxArb <= `SARB_DC;
                                next_directCntlGnt <= 1'b1;
                                next_muxDCEn <= 1'b1;
                        end
                `SARB_SEND_PACKET:
                        if (sendPacketReq == 1'b0)
                        begin
                                NextState_SCTxArb <= `SARB1_WAIT_REQ;
                                next_sendPacketGnt <= 1'b0;
                        end
                `SARB_DC:
                        if (directCntlReq == 1'b0)
                        begin
                                NextState_SCTxArb <= `SARB1_WAIT_REQ;
                                next_directCntlGnt <= 1'b0;
                        end
                `START_SARB:
                        NextState_SCTxArb <= `SARB1_WAIT_REQ;
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SCTxArb_CurrentState
        if (rst)
                CurrState_SCTxArb <= `START_SARB;
        else
                CurrState_SCTxArb <= NextState_SCTxArb;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SCTxArb_RegOutput
        if (rst)
        begin
                muxDCEn <= 1'b0;
                sendPacketGnt <= 1'b0;
                directCntlGnt <= 1'b0;
        end
        else
        begin
                muxDCEn <= next_muxDCEn;
                sendPacketGnt <= next_sendPacketGnt;
                directCntlGnt <= next_directCntlGnt;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author : Steve`
6			`// Company : Base2Designs`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sctxportarbiter.v`
11			`// Generated : 06/10/04 22:29:55`
12			`// From : c:\projects\USBHostSlave\RTL\slaveController\sctxportarbiter.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22
23			`module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);`
24			`input SCTxPortRdyIn;`
25			`input clk;`
26			`input [7:0] directCntlCntl;`
27			`input [7:0] directCntlData;`
28			`input directCntlReq;`
29			`input directCntlWEn;`
30			`input rst;`
31			`input [7:0] sendPacketCntl;`
32			`input [7:0] sendPacketData;`
33			`input sendPacketReq;`
34			`input sendPacketWEn;`
35			`output [7:0] SCTxPortCntl;`
36			`output [7:0] SCTxPortData;`
37			`output SCTxPortRdyOut;`
38			`output SCTxPortWEnable;`
39			`output directCntlGnt;`
40			`output sendPacketGnt;`
41
42			`reg [7:0] SCTxPortCntl, next_SCTxPortCntl;`
43			`reg [7:0] SCTxPortData, next_SCTxPortData;`
44			`wire SCTxPortRdyIn;`
45			`reg SCTxPortRdyOut, next_SCTxPortRdyOut;`
46			`reg SCTxPortWEnable, next_SCTxPortWEnable;`
47			`wire clk;`
48			`wire [7:0] directCntlCntl;`
49			`wire [7:0] directCntlData;`
50			`reg directCntlGnt, next_directCntlGnt;`
51			`wire directCntlReq;`
52			`wire directCntlWEn;`
53			`wire rst;`
54			`wire [7:0] sendPacketCntl;`
55			`wire [7:0] sendPacketData;`
56			`reg sendPacketGnt, next_sendPacketGnt;`
57			`wire sendPacketReq;`
58			`wire sendPacketWEn;`
59
60			`// diagram signals declarations`
61			`reg muxDCEn, next_muxDCEn;`
62
63			`// BINARY ENCODED state machine: SCTxArb`
64			`// State codes definitions:`
65			`define SARB1_WAIT_REQ 2'b00
66			`define SARB_SEND_PACKET 2'b01
67			`define SARB_DC 2'b10
68			`define START_SARB 2'b11
69
70			`reg [1:0] CurrState_SCTxArb;`
71			`reg [1:0] NextState_SCTxArb;`
72
73			`// Diagram actions (continuous assignments allowed only: assign ...)`
74			`// SOFController/directContol/sendPacket mux`
75			`always @(SCTxPortRdyIn)`
76			`begin`
77			`SCTxPortRdyOut = SCTxPortRdyIn;`
78			`end`
79			`always @(muxDCEn or`
80			`directCntlWEn or directCntlData or directCntlCntl or`
81			`directCntlWEn or directCntlData or directCntlCntl or`
82			`sendPacketWEn or sendPacketData or sendPacketCntl)`
83			`begin`
84			`if (muxDCEn == 1'b1)`
85			`begin`
86			`SCTxPortWEnable <= directCntlWEn;`
87			`SCTxPortData <= directCntlData;`
88			`SCTxPortCntl <= directCntlCntl;`
89			`end`
90			`else`
91			`begin`
92			`SCTxPortWEnable <= sendPacketWEn;`
93			`SCTxPortData <= sendPacketData;`
94			`SCTxPortCntl <= sendPacketCntl;`
95			`end`
96			`end`
97
98
99			`//--------------------------------------------------------------------`
100			`// Machine: SCTxArb`
101			`//--------------------------------------------------------------------`
102			`//----------------------------------`
103			`// NextState logic (combinatorial)`
104			`//----------------------------------`
105			`always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)`
106			`begin : SCTxArb_NextState`
107			`NextState_SCTxArb <= CurrState_SCTxArb;`
108			`// Set default values for outputs and signals`
109			`next_sendPacketGnt <= sendPacketGnt;`
110			`next_muxDCEn <= muxDCEn;`
111			`next_directCntlGnt <= directCntlGnt;`
112			`case (CurrState_SCTxArb) // synopsys parallel_case full_case`
113			`SARB1_WAIT_REQ:
114			`if (sendPacketReq == 1'b1)`
115			`begin`
116			NextState_SCTxArb <= `SARB_SEND_PACKET;
117			`next_sendPacketGnt <= 1'b1;`
118			`next_muxDCEn <= 1'b0;`
119			`end`
120			`else if (directCntlReq == 1'b1)`
121			`begin`
122			NextState_SCTxArb <= `SARB_DC;
123			`next_directCntlGnt <= 1'b1;`
124			`next_muxDCEn <= 1'b1;`
125			`end`
126			`SARB_SEND_PACKET:
127			`if (sendPacketReq == 1'b0)`
128			`begin`
129			NextState_SCTxArb <= `SARB1_WAIT_REQ;
130			`next_sendPacketGnt <= 1'b0;`
131			`end`
132			`SARB_DC:
133			`if (directCntlReq == 1'b0)`
134			`begin`
135			NextState_SCTxArb <= `SARB1_WAIT_REQ;
136			`next_directCntlGnt <= 1'b0;`
137			`end`
138			`START_SARB:
139			NextState_SCTxArb <= `SARB1_WAIT_REQ;
140			`endcase`
141			`end`
142
143			`//----------------------------------`
144			`// Current State Logic (sequential)`
145			`//----------------------------------`
146			`always @ (posedge clk)`
147			`begin : SCTxArb_CurrentState`
148			`if (rst)`
149			CurrState_SCTxArb <= `START_SARB;
150			`else`
151			`CurrState_SCTxArb <= NextState_SCTxArb;`
152			`end`
153
154			`//----------------------------------`
155			`// Registered outputs logic`
156			`//----------------------------------`
157			`always @ (posedge clk)`
158			`begin : SCTxArb_RegOutput`
159			`if (rst)`
160			`begin`
161			`muxDCEn <= 1'b0;`
162			`sendPacketGnt <= 1'b0;`
163			`directCntlGnt <= 1'b0;`
164			`end`
165			`else`
166			`begin`
167			`muxDCEn <= next_muxDCEn;`
168			`sendPacketGnt <= next_sendPacketGnt;`
169			`directCntlGnt <= next_directCntlGnt;`
170			`end`
171			`end`
172
173			`endmodule`

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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [sctxportarbiter.v] - Blame information for rev 2