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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveDirectcontrol.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : Steve
// Company     : Base2Designs
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveDirectcontrol.v
// Generated   : 06/05/04 05:59:19
// From        : c:\projects\USBHostSlave\RTL\slaveController\slaveDirectcontrol.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
input   SCTxPortGnt;
input   SCTxPortRdy;
input   clk;
input   directControlEn;
input   [1:0] directControlLineState;
input   rst;
output  [7:0] SCTxPortCntl;
output  [7:0] SCTxPortData;
output  SCTxPortReq;
output  SCTxPortWEn;
 
reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
reg     [7:0] SCTxPortData, next_SCTxPortData;
wire    SCTxPortGnt;
wire    SCTxPortRdy;
reg     SCTxPortReq, next_SCTxPortReq;
reg     SCTxPortWEn, next_SCTxPortWEn;
wire    clk;
wire    directControlEn;
wire    [1:0] directControlLineState;
wire    rst;
 
// BINARY ENCODED state machine: slvDrctCntl
// State codes definitions:
`define START_SDC 3'b000
`define CHK_DRCT_CNTL 3'b001
`define DRCT_CNTL_WAIT_GNT 3'b010
`define DRCT_CNTL_CHK_LOOP 3'b011
`define DRCT_CNTL_WAIT_RDY 3'b100
`define IDLE_FIN 3'b101
`define IDLE_WAIT_GNT 3'b110
`define IDLE_WAIT_RDY 3'b111
 
reg [2:0] CurrState_slvDrctCntl;
reg [2:0] NextState_slvDrctCntl;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
//--------------------------------------------------------------------
// Machine: slvDrctCntl
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
begin : slvDrctCntl_NextState
        NextState_slvDrctCntl <= CurrState_slvDrctCntl;
        // Set default values for outputs and signals
        next_SCTxPortReq <= SCTxPortReq;
        next_SCTxPortWEn <= SCTxPortWEn;
        next_SCTxPortData <= SCTxPortData;
        next_SCTxPortCntl <= SCTxPortCntl;
        case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
                `START_SDC:
                        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
                `CHK_DRCT_CNTL:
                        if (directControlEn == 1'b1)
                        begin
                                NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
                                next_SCTxPortReq <= 1'b1;
                        end
                        else
                        begin
                                NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
                                next_SCTxPortReq <= 1'b1;
                        end
                `DRCT_CNTL_WAIT_GNT:
                        if (SCTxPortGnt == 1'b1)
                                NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
                `DRCT_CNTL_CHK_LOOP:
                begin
                        next_SCTxPortWEn <= 1'b0;
                        if (directControlEn == 1'b0)
                        begin
                                NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
                                next_SCTxPortReq <= 1'b0;
                        end
                        else
                                NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
                end
                `DRCT_CNTL_WAIT_RDY:
                        if (SCTxPortRdy == 1'b1)
                        begin
                                NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
                                next_SCTxPortWEn <= 1'b1;
                                next_SCTxPortData <= {6'b000000, directControlLineState};
                                next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
                        end
                `IDLE_FIN:
                begin
                        next_SCTxPortWEn <= 1'b0;
                        next_SCTxPortReq <= 1'b0;
                        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
                end
                `IDLE_WAIT_GNT:
                        if (SCTxPortGnt == 1'b1)
                                NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
                `IDLE_WAIT_RDY:
                        if (SCTxPortRdy == 1'b1)
                        begin
                                NextState_slvDrctCntl <= `IDLE_FIN;
                                next_SCTxPortWEn <= 1'b1;
                                next_SCTxPortData <= 8'h00;
                                next_SCTxPortCntl <= `TX_IDLE;
                        end
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : slvDrctCntl_CurrentState
        if (rst)
                CurrState_slvDrctCntl <= `START_SDC;
        else
                CurrState_slvDrctCntl <= NextState_slvDrctCntl;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : slvDrctCntl_RegOutput
        if (rst)
        begin
                SCTxPortCntl <= 8'h00;
                SCTxPortData <= 8'h00;
                SCTxPortWEn <= 1'b0;
                SCTxPortReq <= 1'b0;
        end
        else
        begin
                SCTxPortCntl <= next_SCTxPortCntl;
                SCTxPortData <= next_SCTxPortData;
                SCTxPortWEn <= next_SCTxPortWEn;
                SCTxPortReq <= next_SCTxPortReq;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author : Steve`
6			`// Company : Base2Designs`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveDirectcontrol.v`
11			`// Generated : 06/05/04 05:59:19`
12			`// From : c:\projects\USBHostSlave\RTL\slaveController\slaveDirectcontrol.asf`
13			`// By : FSM2VHDL ver. 4.0.3.8`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`timescale 1ns / 1ps
22			`include "usbSerialInterfaceEngine_h.v"
23
24			`module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);`
25			`input SCTxPortGnt;`
26			`input SCTxPortRdy;`
27			`input clk;`
28			`input directControlEn;`
29			`input [1:0] directControlLineState;`
30			`input rst;`
31			`output [7:0] SCTxPortCntl;`
32			`output [7:0] SCTxPortData;`
33			`output SCTxPortReq;`
34			`output SCTxPortWEn;`
35
36			`reg [7:0] SCTxPortCntl, next_SCTxPortCntl;`
37			`reg [7:0] SCTxPortData, next_SCTxPortData;`
38			`wire SCTxPortGnt;`
39			`wire SCTxPortRdy;`
40			`reg SCTxPortReq, next_SCTxPortReq;`
41			`reg SCTxPortWEn, next_SCTxPortWEn;`
42			`wire clk;`
43			`wire directControlEn;`
44			`wire [1:0] directControlLineState;`
45			`wire rst;`
46
47			`// BINARY ENCODED state machine: slvDrctCntl`
48			`// State codes definitions:`
49			`define START_SDC 3'b000
50			`define CHK_DRCT_CNTL 3'b001
51			`define DRCT_CNTL_WAIT_GNT 3'b010
52			`define DRCT_CNTL_CHK_LOOP 3'b011
53			`define DRCT_CNTL_WAIT_RDY 3'b100
54			`define IDLE_FIN 3'b101
55			`define IDLE_WAIT_GNT 3'b110
56			`define IDLE_WAIT_RDY 3'b111
57
58			`reg [2:0] CurrState_slvDrctCntl;`
59			`reg [2:0] NextState_slvDrctCntl;`
60
61			`// Diagram actions (continuous assignments allowed only: assign ...)`
62			`// diagram ACTION`
63
64
65			`//--------------------------------------------------------------------`
66			`// Machine: slvDrctCntl`
67			`//--------------------------------------------------------------------`
68			`//----------------------------------`
69			`// NextState logic (combinatorial)`
70			`//----------------------------------`
71			`always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)`
72			`begin : slvDrctCntl_NextState`
73			`NextState_slvDrctCntl <= CurrState_slvDrctCntl;`
74			`// Set default values for outputs and signals`
75			`next_SCTxPortReq <= SCTxPortReq;`
76			`next_SCTxPortWEn <= SCTxPortWEn;`
77			`next_SCTxPortData <= SCTxPortData;`
78			`next_SCTxPortCntl <= SCTxPortCntl;`
79			`case (CurrState_slvDrctCntl) // synopsys parallel_case full_case`
80			`START_SDC:
81			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
82			`CHK_DRCT_CNTL:
83			`if (directControlEn == 1'b1)`
84			`begin`
85			NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
86			`next_SCTxPortReq <= 1'b1;`
87			`end`
88			`else`
89			`begin`
90			NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
91			`next_SCTxPortReq <= 1'b1;`
92			`end`
93			`DRCT_CNTL_WAIT_GNT:
94			`if (SCTxPortGnt == 1'b1)`
95			NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
96			`DRCT_CNTL_CHK_LOOP:
97			`begin`
98			`next_SCTxPortWEn <= 1'b0;`
99			`if (directControlEn == 1'b0)`
100			`begin`
101			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
102			`next_SCTxPortReq <= 1'b0;`
103			`end`
104			`else`
105			NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
106			`end`
107			`DRCT_CNTL_WAIT_RDY:
108			`if (SCTxPortRdy == 1'b1)`
109			`begin`
110			NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
111			`next_SCTxPortWEn <= 1'b1;`
112			`next_SCTxPortData <= {6'b000000, directControlLineState};`
113			next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
114			`end`
115			`IDLE_FIN:
116			`begin`
117			`next_SCTxPortWEn <= 1'b0;`
118			`next_SCTxPortReq <= 1'b0;`
119			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
120			`end`
121			`IDLE_WAIT_GNT:
122			`if (SCTxPortGnt == 1'b1)`
123			NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
124			`IDLE_WAIT_RDY:
125			`if (SCTxPortRdy == 1'b1)`
126			`begin`
127			NextState_slvDrctCntl <= `IDLE_FIN;
128			`next_SCTxPortWEn <= 1'b1;`
129			`next_SCTxPortData <= 8'h00;`
130			next_SCTxPortCntl <= `TX_IDLE;
131			`end`
132			`endcase`
133			`end`
134
135			`//----------------------------------`
136			`// Current State Logic (sequential)`
137			`//----------------------------------`
138			`always @ (posedge clk)`
139			`begin : slvDrctCntl_CurrentState`
140			`if (rst)`
141			CurrState_slvDrctCntl <= `START_SDC;
142			`else`
143			`CurrState_slvDrctCntl <= NextState_slvDrctCntl;`
144			`end`
145
146			`//----------------------------------`
147			`// Registered outputs logic`
148			`//----------------------------------`
149			`always @ (posedge clk)`
150			`begin : slvDrctCntl_RegOutput`
151			`if (rst)`
152			`begin`
153			`SCTxPortCntl <= 8'h00;`
154			`SCTxPortData <= 8'h00;`
155			`SCTxPortWEn <= 1'b0;`
156			`SCTxPortReq <= 1'b0;`
157			`end`
158			`else`
159			`begin`
160			`SCTxPortCntl <= next_SCTxPortCntl;`
161			`SCTxPortData <= next_SCTxPortData;`
162			`SCTxPortWEn <= next_SCTxPortWEn;`
163			`SCTxPortReq <= next_SCTxPortReq;`
164			`end`
165			`end`
166
167			`endmodule`

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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveDirectcontrol.v] - Blame information for rev 2