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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveDirectcontrol.v] - Blame information for rev 9

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveDirectControl
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
 
module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
input   clk;
input   directControlEn;
input   [1:0]directControlLineState;
input   rst;
input   SCTxPortGnt;
input   SCTxPortRdy;
output  [7:0]SCTxPortCntl;
output  [7:0]SCTxPortData;
output  SCTxPortReq;
output  SCTxPortWEn;
 
wire    clk;
wire    directControlEn;
wire    [1:0]directControlLineState;
wire    rst;
reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
reg     [7:0]SCTxPortData, next_SCTxPortData;
wire    SCTxPortGnt;
wire    SCTxPortRdy;
reg     SCTxPortReq, next_SCTxPortReq;
reg     SCTxPortWEn, next_SCTxPortWEn;
 
// BINARY ENCODED state machine: slvDrctCntl
// State codes definitions:
`define START_SDC 3'b000
`define CHK_DRCT_CNTL 3'b001
`define DRCT_CNTL_WAIT_GNT 3'b010
`define DRCT_CNTL_CHK_LOOP 3'b011
`define DRCT_CNTL_WAIT_RDY 3'b100
`define IDLE_FIN 3'b101
`define IDLE_WAIT_GNT 3'b110
`define IDLE_WAIT_RDY 3'b111
 
reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: slvDrctCntl
 
// NextState logic (combinatorial)
always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
begin
  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
  // Set default values for outputs and signals
  next_SCTxPortCntl <= SCTxPortCntl;
  next_SCTxPortData <= SCTxPortData;
  next_SCTxPortWEn <= SCTxPortWEn;
  next_SCTxPortReq <= SCTxPortReq;
  case (CurrState_slvDrctCntl)  // synopsys parallel_case full_case
    `START_SDC:
    begin
      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
    end
    `CHK_DRCT_CNTL:
    begin
      if (directControlEn == 1'b1)
      begin
        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
        next_SCTxPortReq <= 1'b1;
      end
      else
      begin
        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
        next_SCTxPortReq <= 1'b1;
      end
    end
    `DRCT_CNTL_WAIT_GNT:
    begin
      if (SCTxPortGnt == 1'b1)
      begin
        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
      end
    end
    `DRCT_CNTL_CHK_LOOP:
    begin
      next_SCTxPortWEn <= 1'b0;
      if (directControlEn == 1'b0)
      begin
        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
        next_SCTxPortReq <= 1'b0;
      end
      else
      begin
        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
      end
    end
    `DRCT_CNTL_WAIT_RDY:
    begin
      if (SCTxPortRdy == 1'b1)
      begin
        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
        next_SCTxPortWEn <= 1'b1;
        next_SCTxPortData <= {6'b000000, directControlLineState};
        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
      end
    end
    `IDLE_FIN:
    begin
      next_SCTxPortWEn <= 1'b0;
      next_SCTxPortReq <= 1'b0;
      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
    end
    `IDLE_WAIT_GNT:
    begin
      if (SCTxPortGnt == 1'b1)
      begin
        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
      end
    end
    `IDLE_WAIT_RDY:
    begin
      if (SCTxPortRdy == 1'b1)
      begin
        NextState_slvDrctCntl <= `IDLE_FIN;
        next_SCTxPortWEn <= 1'b1;
        next_SCTxPortData <= 8'h00;
        next_SCTxPortCntl <= `TX_IDLE;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvDrctCntl <= `START_SDC;
  else
    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    SCTxPortCntl <= 8'h00;
    SCTxPortData <= 8'h00;
    SCTxPortWEn <= 1'b0;
    SCTxPortReq <= 1'b0;
  end
  else
  begin
    SCTxPortCntl <= next_SCTxPortCntl;
    SCTxPortData <= next_SCTxPortData;
    SCTxPortWEn <= next_SCTxPortWEn;
    SCTxPortReq <= next_SCTxPortReq;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveDirectcontrol.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveDirectControl`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`//`
46			`timescale 1ns / 1ps
47			`include "usbSerialInterfaceEngine_h.v"
48
49			`module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);`
50			`input clk;`
51			`input directControlEn;`
52			`input [1:0]directControlLineState;`
53			`input rst;`
54			`input SCTxPortGnt;`
55			`input SCTxPortRdy;`
56			`output [7:0]SCTxPortCntl;`
57			`output [7:0]SCTxPortData;`
58			`output SCTxPortReq;`
59			`output SCTxPortWEn;`
60
61			`wire clk;`
62			`wire directControlEn;`
63			`wire [1:0]directControlLineState;`
64			`wire rst;`
65			`reg [7:0]SCTxPortCntl, next_SCTxPortCntl;`
66			`reg [7:0]SCTxPortData, next_SCTxPortData;`
67			`wire SCTxPortGnt;`
68			`wire SCTxPortRdy;`
69			`reg SCTxPortReq, next_SCTxPortReq;`
70			`reg SCTxPortWEn, next_SCTxPortWEn;`
71
72			`// BINARY ENCODED state machine: slvDrctCntl`
73			`// State codes definitions:`
74			`define START_SDC 3'b000
75			`define CHK_DRCT_CNTL 3'b001
76			`define DRCT_CNTL_WAIT_GNT 3'b010
77			`define DRCT_CNTL_CHK_LOOP 3'b011
78			`define DRCT_CNTL_WAIT_RDY 3'b100
79			`define IDLE_FIN 3'b101
80			`define IDLE_WAIT_GNT 3'b110
81			`define IDLE_WAIT_RDY 3'b111
82
83			`reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;`
84
85			`// Diagram actions (continuous assignments allowed only: assign ...)`
86			`// diagram ACTION`
87
88
89			`// Machine: slvDrctCntl`
90
91			`// NextState logic (combinatorial)`
92			`always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)`
93			`begin`
94			`NextState_slvDrctCntl <= CurrState_slvDrctCntl;`
95			`// Set default values for outputs and signals`
96			`next_SCTxPortCntl <= SCTxPortCntl;`
97			`next_SCTxPortData <= SCTxPortData;`
98			`next_SCTxPortWEn <= SCTxPortWEn;`
99			`next_SCTxPortReq <= SCTxPortReq;`
100			`case (CurrState_slvDrctCntl) // synopsys parallel_case full_case`
101			`START_SDC:
102			`begin`
103			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
104			`end`
105			`CHK_DRCT_CNTL:
106			`begin`
107			`if (directControlEn == 1'b1)`
108			`begin`
109			NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
110			`next_SCTxPortReq <= 1'b1;`
111			`end`
112			`else`
113			`begin`
114			NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
115			`next_SCTxPortReq <= 1'b1;`
116			`end`
117			`end`
118			`DRCT_CNTL_WAIT_GNT:
119			`begin`
120			`if (SCTxPortGnt == 1'b1)`
121			`begin`
122			NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
123			`end`
124			`end`
125			`DRCT_CNTL_CHK_LOOP:
126			`begin`
127			`next_SCTxPortWEn <= 1'b0;`
128			`if (directControlEn == 1'b0)`
129			`begin`
130			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
131			`next_SCTxPortReq <= 1'b0;`
132			`end`
133			`else`
134			`begin`
135			NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
136			`end`
137			`end`
138			`DRCT_CNTL_WAIT_RDY:
139			`begin`
140			`if (SCTxPortRdy == 1'b1)`
141			`begin`
142			NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
143			`next_SCTxPortWEn <= 1'b1;`
144			`next_SCTxPortData <= {6'b000000, directControlLineState};`
145			next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
146			`end`
147			`end`
148			`IDLE_FIN:
149			`begin`
150			`next_SCTxPortWEn <= 1'b0;`
151			`next_SCTxPortReq <= 1'b0;`
152			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
153			`end`
154			`IDLE_WAIT_GNT:
155			`begin`
156			`if (SCTxPortGnt == 1'b1)`
157			`begin`
158			NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
159			`end`
160			`end`
161			`IDLE_WAIT_RDY:
162			`begin`
163			`if (SCTxPortRdy == 1'b1)`
164			`begin`
165			NextState_slvDrctCntl <= `IDLE_FIN;
166			`next_SCTxPortWEn <= 1'b1;`
167			`next_SCTxPortData <= 8'h00;`
168			next_SCTxPortCntl <= `TX_IDLE;
169			`end`
170			`end`
171			`endcase`
172			`end`
173
174			`// Current State Logic (sequential)`
175			`always @ (posedge clk)`
176			`begin`
177			`if (rst)`
178			CurrState_slvDrctCntl <= `START_SDC;
179			`else`
180			`CurrState_slvDrctCntl <= NextState_slvDrctCntl;`
181			`end`
182
183			`// Registered outputs logic`
184			`always @ (posedge clk)`
185			`begin`
186			`if (rst)`
187			`begin`
188			`SCTxPortCntl <= 8'h00;`
189			`SCTxPortData <= 8'h00;`
190			`SCTxPortWEn <= 1'b0;`
191			`SCTxPortReq <= 1'b0;`
192			`end`
193			`else`
194			`begin`
195			`SCTxPortCntl <= next_SCTxPortCntl;`
196			`SCTxPortData <= next_SCTxPortData;`
197			`SCTxPortWEn <= next_SCTxPortWEn;`
198			`SCTxPortReq <= next_SCTxPortReq;`
199			`end`
200			`end`
201
202	2	sfielding	`endmodule`