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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveGetpacket.v] - Blame information for rev 18

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveGetPacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
input   clk;
input   endPointReady;
input   getPacketEn;
input   rst;
input   [7:0]RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0]RXStreamStatusIn;
input   SIERxTimeOut;    // Single cycle pulse
output  ACKRxed;
output  bitStuffError;
output  CRCError;
output  dataSequence;
output  [7:0]RXFifoData;
output  RXFifoWEn;
output  RXOverflow;
output  RXPacketRdy;
output  [3:0]RxPID;
output  RXTimeOut;
 
reg     ACKRxed, next_ACKRxed;
reg     bitStuffError, next_bitStuffError;
wire    clk;
reg     CRCError, next_CRCError;
reg     dataSequence, next_dataSequence;
wire    endPointReady;
wire    getPacketEn;
wire    rst;
wire    [7:0]RXDataIn;
wire    RXDataValid;
reg     [7:0]RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXOverflow, next_RXOverflow;
reg     RXPacketRdy, next_RXPacketRdy;
reg     [3:0]RxPID, next_RxPID;
wire    [7:0]RXStreamStatusIn;
reg     RXTimeOut, next_RXTimeOut;
wire    SIERxTimeOut;
 
// diagram signals declarations
reg  [7:0]RXByte, next_RXByte;
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
 
// BINARY ENCODED state machine: slvGetPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
 
reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
 
 
// Machine: slvGetPkt
 
// NextState logic (combinatorial)
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
begin
  NextState_slvGetPkt <= CurrState_slvGetPkt;
  // Set default values for outputs and signals
  next_RXOverflow <= RXOverflow;
  next_ACKRxed <= ACKRxed;
  next_RXByte <= RXByte;
  next_RXStreamStatus <= RXStreamStatus;
  next_RXByteOldest <= RXByteOldest;
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_dataSequence <= dataSequence;
  next_RXByteOld <= RXByteOld;
  next_RXFifoWEn <= RXFifoWEn;
  next_RXFifoData <= RXFifoData;
  next_RXPacketRdy <= RXPacketRdy;
  next_RXTimeOut <= RXTimeOut;
  next_RxPID <= RxPID;
  case (CurrState_slvGetPkt)  // synopsys parallel_case full_case
    `START_GP:
    begin
      NextState_slvGetPkt <= `WAIT_EN;
    end
    `WAIT_PKT:
    begin
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RXOverflow <= 1'b0;
      next_RXTimeOut <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `CHK_PKT_START;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
      else if (SIERxTimeOut == 1'b1)
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `CHK_PKT_START:
    begin
      if (RXStreamStatus == `RX_PACKET_START)
      begin
        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
        next_RxPID <= RXByte[3:0];
      end
      else
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `WAIT_EN:
    begin
      next_RXPacketRdy <= 1'b0;
      if (getPacketEn == 1'b1)
      begin
        NextState_slvGetPkt <= `WAIT_PKT;
      end
    end
    `PKT_RDY:
    begin
      next_RXPacketRdy <= 1'b1;
      NextState_slvGetPkt <= `WAIT_EN;
    end
    `PROC_PKT_CHK_PID:
    begin
      if (RXByte[1:0] == `HANDSHAKE)
      begin
        NextState_slvGetPkt <= `PROC_PKT_HS;
      end
      else if (RXByte[1:0] == `DATA)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
      end
      else
      begin
        NextState_slvGetPkt <= `PKT_RDY;
      end
    end
    `PROC_PKT_HS:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
      end
    end
    `PROC_PKT_DATA_W_D1:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D1:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
        next_RXByteOldest <= RXByte;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D2:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_FIN:
    begin
      next_CRCError <= RXByte[`CRC_ERROR_BIT];
      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
      NextState_slvGetPkt <= `PKT_RDY;
    end
    `PROC_PKT_DATA_CHK_D2:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
        next_RXByteOld <= RXByte;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D3:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D3:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_LOOP_CHK_FIFO:
    begin
      if (endPointReady == 1'b0)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
      end
      else if (RXFifoFull == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
        next_RXOverflow <= 1'b1;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
        next_RXFifoWEn <= 1'b1;
        next_RXFifoData <= RXByteOldest;
        next_RXByteOldest <= RXByteOld;
        next_RXByteOld <= RXByte;
      end
    end
    `PROC_PKT_DATA_LOOP_FIFO_FULL:
    begin
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
    end
    `PROC_PKT_DATA_LOOP_W_D:
    begin
      next_RXFifoWEn <= 1'b0;
      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
        next_RXByte <= RXDataIn;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
        next_RXByte <= RXDataIn;
      end
    end
    `PROC_PKT_DATA_LOOP_DELAY:
    begin
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
    end
    `PROC_PKT_DATA_LOOP_EP_N_RDY:    // Discard data
    begin
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvGetPkt <= `START_GP;
  else
    CurrState_slvGetPkt <= NextState_slvGetPkt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    RXOverflow <= 1'b0;
    ACKRxed <= 1'b0;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    dataSequence <= 1'b0;
    RXFifoWEn <= 1'b0;
    RXFifoData <= 8'h00;
    RXPacketRdy <= 1'b0;
    RXTimeOut <= 1'b0;
    RxPID <= 4'h0;
    RXByte <= 8'h00;
    RXStreamStatus <= 8'h00;
    RXByteOldest <= 8'h00;
    RXByteOld <= 8'h00;
  end
  else
  begin
    RXOverflow <= next_RXOverflow;
    ACKRxed <= next_ACKRxed;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    dataSequence <= next_dataSequence;
    RXFifoWEn <= next_RXFifoWEn;
    RXFifoData <= next_RXFifoData;
    RXPacketRdy <= next_RXPacketRdy;
    RXTimeOut <= next_RXTimeOut;
    RxPID <= next_RxPID;
    RXByte <= next_RXByte;
    RXStreamStatus <= next_RXStreamStatus;
    RXByteOldest <= next_RXByteOldest;
    RXByteOld <= next_RXByteOld;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveGetPacket`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	9	sfielding	`timescale 1ns / 1ps
46	5	sfielding	`include "usbSerialInterfaceEngine_h.v"
47			`include "usbConstants_h.v"
48
49	18	sfielding	`module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);`
50	5	sfielding	`input clk;`
51	18	sfielding	`input endPointReady;`
52	5	sfielding	`input getPacketEn;`
53			`input rst;`
54			`input [7:0]RXDataIn;`
55			`input RXDataValid;`
56			`input RXFifoFull;`
57			`input [7:0]RXStreamStatusIn;`
58			`input SIERxTimeOut; // Single cycle pulse`
59			`output ACKRxed;`
60			`output bitStuffError;`
61			`output CRCError;`
62			`output dataSequence;`
63			`output [7:0]RXFifoData;`
64			`output RXFifoWEn;`
65			`output RXOverflow;`
66			`output RXPacketRdy;`
67			`output [3:0]RxPID;`
68			`output RXTimeOut;`
69
70			`reg ACKRxed, next_ACKRxed;`
71			`reg bitStuffError, next_bitStuffError;`
72			`wire clk;`
73			`reg CRCError, next_CRCError;`
74			`reg dataSequence, next_dataSequence;`
75	18	sfielding	`wire endPointReady;`
76	5	sfielding	`wire getPacketEn;`
77			`wire rst;`
78			`wire [7:0]RXDataIn;`
79			`wire RXDataValid;`
80			`reg [7:0]RXFifoData, next_RXFifoData;`
81			`wire RXFifoFull;`
82			`reg RXFifoWEn, next_RXFifoWEn;`
83			`reg RXOverflow, next_RXOverflow;`
84			`reg RXPacketRdy, next_RXPacketRdy;`
85			`reg [3:0]RxPID, next_RxPID;`
86			`wire [7:0]RXStreamStatusIn;`
87			`reg RXTimeOut, next_RXTimeOut;`
88			`wire SIERxTimeOut;`
89
90			`// diagram signals declarations`
91			`reg [7:0]RXByte, next_RXByte;`
92			`reg [7:0]RXByteOld, next_RXByteOld;`
93			`reg [7:0]RXByteOldest, next_RXByteOldest;`
94			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
95
96			`// BINARY ENCODED state machine: slvGetPkt`
97			`// State codes definitions:`
98			`define PROC_PKT_CHK_PID 5'b00000
99			`define PROC_PKT_HS 5'b00001
100			`define PROC_PKT_DATA_W_D1 5'b00010
101			`define PROC_PKT_DATA_CHK_D1 5'b00011
102			`define PROC_PKT_DATA_W_D2 5'b00100
103			`define PROC_PKT_DATA_FIN 5'b00101
104			`define PROC_PKT_DATA_CHK_D2 5'b00110
105			`define PROC_PKT_DATA_W_D3 5'b00111
106			`define PROC_PKT_DATA_CHK_D3 5'b01000
107			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
108			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
109			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
110			`define START_GP 5'b01100
111			`define WAIT_PKT 5'b01101
112			`define CHK_PKT_START 5'b01110
113			`define WAIT_EN 5'b01111
114			`define PKT_RDY 5'b10000
115			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
116	18	sfielding	`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
117	5	sfielding
118			`reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;`
119
120
121			`// Machine: slvGetPkt`
122
123			`// NextState logic (combinatorial)`
124	18	sfielding	`always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)`
125	5	sfielding	`begin`
126			`NextState_slvGetPkt <= CurrState_slvGetPkt;`
127			`// Set default values for outputs and signals`
128			`next_RXOverflow <= RXOverflow;`
129			`next_ACKRxed <= ACKRxed;`
130			`next_RXByte <= RXByte;`
131			`next_RXStreamStatus <= RXStreamStatus;`
132			`next_RXByteOldest <= RXByteOldest;`
133			`next_CRCError <= CRCError;`
134			`next_bitStuffError <= bitStuffError;`
135			`next_dataSequence <= dataSequence;`
136			`next_RXByteOld <= RXByteOld;`
137			`next_RXFifoWEn <= RXFifoWEn;`
138			`next_RXFifoData <= RXFifoData;`
139			`next_RXPacketRdy <= RXPacketRdy;`
140			`next_RXTimeOut <= RXTimeOut;`
141			`next_RxPID <= RxPID;`
142			`case (CurrState_slvGetPkt) // synopsys parallel_case full_case`
143			`START_GP:
144			`begin`
145			NextState_slvGetPkt <= `WAIT_EN;
146			`end`
147			`WAIT_PKT:
148			`begin`
149			`next_CRCError <= 1'b0;`
150			`next_bitStuffError <= 1'b0;`
151			`next_RXOverflow <= 1'b0;`
152			`next_RXTimeOut <= 1'b0;`
153			`next_ACKRxed <= 1'b0;`
154			`next_dataSequence <= 1'b0;`
155			`if (RXDataValid == 1'b1)`
156			`begin`
157			NextState_slvGetPkt <= `CHK_PKT_START;
158			`next_RXByte <= RXDataIn;`
159			`next_RXStreamStatus <= RXStreamStatusIn;`
160			`end`
161	9	sfielding	`else if (SIERxTimeOut == 1'b1)`
162			`begin`
163			NextState_slvGetPkt <= `PKT_RDY;
164			`next_RXTimeOut <= 1'b1;`
165			`end`
166	5	sfielding	`end`
167			`CHK_PKT_START:
168			`begin`
169			if (RXStreamStatus == `RX_PACKET_START)
170			`begin`
171			NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
172			`next_RxPID <= RXByte[3:0];`
173			`end`
174			`else`
175			`begin`
176			NextState_slvGetPkt <= `PKT_RDY;
177			`next_RXTimeOut <= 1'b1;`
178			`end`
179			`end`
180			`WAIT_EN:
181			`begin`
182			`next_RXPacketRdy <= 1'b0;`
183			`if (getPacketEn == 1'b1)`
184			`begin`
185			NextState_slvGetPkt <= `WAIT_PKT;
186			`end`
187			`end`
188			`PKT_RDY:
189			`begin`
190			`next_RXPacketRdy <= 1'b1;`
191			NextState_slvGetPkt <= `WAIT_EN;
192			`end`
193			`PROC_PKT_CHK_PID:
194			`begin`
195			if (RXByte[1:0] == `HANDSHAKE)
196			`begin`
197			NextState_slvGetPkt <= `PROC_PKT_HS;
198			`end`
199			else if (RXByte[1:0] == `DATA)
200			`begin`
201			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
202			`end`
203			`else`
204			`begin`
205			NextState_slvGetPkt <= `PKT_RDY;
206			`end`
207			`end`
208			`PROC_PKT_HS:
209			`begin`
210			`if (RXDataValid == 1'b1)`
211			`begin`
212			NextState_slvGetPkt <= `PKT_RDY;
213			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
214			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
215			`end`
216			`end`
217			`PROC_PKT_DATA_W_D1:
218			`begin`
219			`if (RXDataValid == 1'b1)`
220			`begin`
221			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
222			`next_RXByte <= RXDataIn;`
223			`next_RXStreamStatus <= RXStreamStatusIn;`
224			`end`
225			`end`
226			`PROC_PKT_DATA_CHK_D1:
227			`begin`
228			if (RXStreamStatus == `RX_PACKET_STREAM)
229			`begin`
230			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
231			`next_RXByteOldest <= RXByte;`
232			`end`
233			`else`
234			`begin`
235			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
236			`end`
237			`end`
238			`PROC_PKT_DATA_W_D2:
239			`begin`
240			`if (RXDataValid == 1'b1)`
241			`begin`
242			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
243			`next_RXByte <= RXDataIn;`
244			`next_RXStreamStatus <= RXStreamStatusIn;`
245			`end`
246			`end`
247			`PROC_PKT_DATA_FIN:
248			`begin`
249			next_CRCError <= RXByte[`CRC_ERROR_BIT];
250			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
251			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
252			NextState_slvGetPkt <= `PKT_RDY;
253			`end`
254			`PROC_PKT_DATA_CHK_D2:
255			`begin`
256			if (RXStreamStatus == `RX_PACKET_STREAM)
257			`begin`
258			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
259			`next_RXByteOld <= RXByte;`
260			`end`
261			`else`
262			`begin`
263			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
264			`end`
265			`end`
266			`PROC_PKT_DATA_W_D3:
267			`begin`
268			`if (RXDataValid == 1'b1)`
269			`begin`
270			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
271			`next_RXByte <= RXDataIn;`
272			`next_RXStreamStatus <= RXStreamStatusIn;`
273			`end`
274			`end`
275			`PROC_PKT_DATA_CHK_D3:
276			`begin`
277			if (RXStreamStatus == `RX_PACKET_STREAM)
278			`begin`
279			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
280			`end`
281			`else`
282			`begin`
283			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
284			`end`
285			`end`
286			`PROC_PKT_DATA_LOOP_CHK_FIFO:
287			`begin`
288	18	sfielding	`if (endPointReady == 1'b0)`
289	5	sfielding	`begin`
290	18	sfielding	NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
291			`end`
292			`else if (RXFifoFull == 1'b1)`
293			`begin`
294	5	sfielding	NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
295			`next_RXOverflow <= 1'b1;`
296			`end`
297			`else`
298			`begin`
299			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
300			`next_RXFifoWEn <= 1'b1;`
301			`next_RXFifoData <= RXByteOldest;`
302			`next_RXByteOldest <= RXByteOld;`
303			`next_RXByteOld <= RXByte;`
304			`end`
305			`end`
306			`PROC_PKT_DATA_LOOP_FIFO_FULL:
307			`begin`
308			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
309			`end`
310			`PROC_PKT_DATA_LOOP_W_D:
311			`begin`
312			`next_RXFifoWEn <= 1'b0;`
313			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
314			`begin`
315			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
316			`next_RXByte <= RXDataIn;`
317			`end`
318			`else if (RXDataValid == 1'b1)`
319			`begin`
320			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
321			`next_RXByte <= RXDataIn;`
322			`end`
323			`end`
324			`PROC_PKT_DATA_LOOP_DELAY:
325			`begin`
326			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
327			`end`
328	18	sfielding	`PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
329			`begin`
330			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
331			`end`
332	5	sfielding	`endcase`
333			`end`
334
335			`// Current State Logic (sequential)`
336			`always @ (posedge clk)`
337			`begin`
338			`if (rst)`
339			CurrState_slvGetPkt <= `START_GP;
340			`else`
341			`CurrState_slvGetPkt <= NextState_slvGetPkt;`
342			`end`
343
344			`// Registered outputs logic`
345			`always @ (posedge clk)`
346			`begin`
347			`if (rst)`
348			`begin`
349			`RXOverflow <= 1'b0;`
350			`ACKRxed <= 1'b0;`
351			`CRCError <= 1'b0;`
352			`bitStuffError <= 1'b0;`
353			`dataSequence <= 1'b0;`
354			`RXFifoWEn <= 1'b0;`
355			`RXFifoData <= 8'h00;`
356			`RXPacketRdy <= 1'b0;`
357			`RXTimeOut <= 1'b0;`
358			`RxPID <= 4'h0;`
359			`RXByte <= 8'h00;`
360			`RXStreamStatus <= 8'h00;`
361			`RXByteOldest <= 8'h00;`
362			`RXByteOld <= 8'h00;`
363			`end`
364			`else`
365			`begin`
366			`RXOverflow <= next_RXOverflow;`
367			`ACKRxed <= next_ACKRxed;`
368			`CRCError <= next_CRCError;`
369			`bitStuffError <= next_bitStuffError;`
370			`dataSequence <= next_dataSequence;`
371			`RXFifoWEn <= next_RXFifoWEn;`
372			`RXFifoData <= next_RXFifoData;`
373			`RXPacketRdy <= next_RXPacketRdy;`
374			`RXTimeOut <= next_RXTimeOut;`
375			`RxPID <= next_RxPID;`
376			`RXByte <= next_RXByte;`
377			`RXStreamStatus <= next_RXStreamStatus;`
378			`RXByteOldest <= next_RXByteOldest;`
379			`RXByteOld <= next_RXByteOld;`
380			`end`
381			`end`
382
383	2	sfielding	`endmodule`

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