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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveGetpacket.v] - Blame information for rev 2

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//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : usbhostslave
// Author      : Steve
// Company     : Base2Designs
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveGetpacket.v
// Generated   : 09/22/04 06:01:23
// From        : c:\projects\USBHostSlave\RTL\slaveController\slaveGetpacket.asf
// By          : FSM2VHDL ver. 4.0.5.2
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
 
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, bitStuffError, clk, dataSequence, getPacketEn, rst);
input   [7:0] RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0] RXStreamStatusIn;
input   SIERxTimeOut;           // Single cycle pulse
input   clk;
input   getPacketEn;
input   rst;
output  ACKRxed;
output  CRCError;
output  [7:0] RXFifoData;
output  RXFifoWEn;
output  RXOverflow;
output  RXPacketRdy;
output  RXTimeOut;
output  [3:0] RxPID;
output  bitStuffError;
output  dataSequence;
 
reg     ACKRxed, next_ACKRxed;
reg     CRCError, next_CRCError;
wire    [7:0] RXDataIn;
wire    RXDataValid;
reg     [7:0] RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXOverflow, next_RXOverflow;
reg     RXPacketRdy, next_RXPacketRdy;
wire    [7:0] RXStreamStatusIn;
reg     RXTimeOut, next_RXTimeOut;
reg     [3:0] RxPID, next_RxPID;
wire    SIERxTimeOut;
reg     bitStuffError, next_bitStuffError;
wire    clk;
reg     dataSequence, next_dataSequence;
wire    getPacketEn;
wire    rst;
 
// diagram signals declarations
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg  [7:0]RXByte, next_RXByte;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
 
// BINARY ENCODED state machine: slvGetPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
 
reg [4:0] CurrState_slvGetPkt;
reg [4:0] NextState_slvGetPkt;
 
 
//--------------------------------------------------------------------
// Machine: slvGetPkt
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
begin : slvGetPkt_NextState
        NextState_slvGetPkt <= CurrState_slvGetPkt;
        // Set default values for outputs and signals
        next_CRCError <= CRCError;
        next_bitStuffError <= bitStuffError;
        next_RXOverflow <= RXOverflow;
        next_RXTimeOut <= RXTimeOut;
        next_ACKRxed <= ACKRxed;
        next_dataSequence <= dataSequence;
        next_RXByte <= RXByte;
        next_RXStreamStatus <= RXStreamStatus;
        next_RxPID <= RxPID;
        next_RXPacketRdy <= RXPacketRdy;
        next_RXByteOldest <= RXByteOldest;
        next_RXByteOld <= RXByteOld;
        next_RXFifoWEn <= RXFifoWEn;
        next_RXFifoData <= RXFifoData;
        case (CurrState_slvGetPkt) // synopsys parallel_case full_case
                `START_GP:
                        NextState_slvGetPkt <= `WAIT_EN;
                `WAIT_PKT:
                begin
                        next_CRCError <= 1'b0;
                        next_bitStuffError <= 1'b0;
                        next_RXOverflow <= 1'b0;
                        next_RXTimeOut <= 1'b0;
                        next_ACKRxed <= 1'b0;
                        next_dataSequence <= 1'b0;
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_slvGetPkt <= `CHK_PKT_START;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                end
                `CHK_PKT_START:
                        if (RXStreamStatus == `RX_PACKET_START)
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
                                next_RxPID <= RXByte[3:0];
                        end
                        else
                        begin
                                NextState_slvGetPkt <= `PKT_RDY;
                                next_RXTimeOut <= 1'b1;
                        end
                `WAIT_EN:
                begin
                        next_RXPacketRdy <= 1'b0;
                        if (getPacketEn == 1'b1)
                                NextState_slvGetPkt <= `WAIT_PKT;
                end
                `PKT_RDY:
                begin
                        next_RXPacketRdy <= 1'b1;
                        NextState_slvGetPkt <= `WAIT_EN;
                end
                `PROC_PKT_CHK_PID:
                        if (RXByte[1:0] == `HANDSHAKE)
                                NextState_slvGetPkt <= `PROC_PKT_HS;
                        else if (RXByte[1:0] == `DATA)
                                NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
                        else
                                NextState_slvGetPkt <= `PKT_RDY;
                `PROC_PKT_HS:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_slvGetPkt <= `PKT_RDY;
                                next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
                                next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
                        end
                `PROC_PKT_DATA_W_D1:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_CHK_D1:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
                                next_RXByteOldest <= RXByte;
                        end
                        else
                                NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_W_D2:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_FIN:
                begin
                        next_CRCError <= RXByte[`CRC_ERROR_BIT];
                        next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
                        next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
                        NextState_slvGetPkt <= `PKT_RDY;
                end
                `PROC_PKT_DATA_CHK_D2:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
                                next_RXByteOld <= RXByte;
                        end
                        else
                                NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_W_D3:
                        if (RXDataValid == 1'b1)
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
                                next_RXByte <= RXDataIn;
                                next_RXStreamStatus <= RXStreamStatusIn;
                        end
                `PROC_PKT_DATA_CHK_D3:
                        if (RXStreamStatus == `RX_PACKET_STREAM)
                                NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
                        else
                                NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
                `PROC_PKT_DATA_LOOP_CHK_FIFO:
                        if (RXFifoFull == 1'b1)
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
                                next_RXOverflow <= 1'b1;
                        end
                        else
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
                                next_RXFifoWEn <= 1'b1;
                                next_RXFifoData <= RXByteOldest;
                                next_RXByteOldest <= RXByteOld;
                                next_RXByteOld <= RXByte;
                        end
                `PROC_PKT_DATA_LOOP_FIFO_FULL:
                        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
                `PROC_PKT_DATA_LOOP_W_D:
                begin
                        next_RXFifoWEn <= 1'b0;
                        if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
                                next_RXByte <= RXDataIn;
                        end
                        else if (RXDataValid == 1'b1)
                        begin
                                NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
                                next_RXByte <= RXDataIn;
                        end
                end
                `PROC_PKT_DATA_LOOP_DELAY:
                        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
        endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : slvGetPkt_CurrentState
        if (rst)
                CurrState_slvGetPkt <= `START_GP;
        else
                CurrState_slvGetPkt <= NextState_slvGetPkt;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : slvGetPkt_RegOutput
        if (rst)
        begin
                RXByteOld <= 8'h00;
                RXByteOldest <= 8'h00;
                RXByte <= 8'h00;
                RXStreamStatus <= 8'h00;
                RXPacketRdy <= 1'b0;
                RXFifoWEn <= 1'b0;
                RXFifoData <= 8'h00;
                CRCError <= 1'b0;
                bitStuffError <= 1'b0;
                RXOverflow <= 1'b0;
                RXTimeOut <= 1'b0;
                ACKRxed <= 1'b0;
                dataSequence <= 1'b0;
                RxPID <= 4'h0;
        end
        else
        begin
                RXByteOld <= next_RXByteOld;
                RXByteOldest <= next_RXByteOldest;
                RXByte <= next_RXByte;
                RXStreamStatus <= next_RXStreamStatus;
                RXPacketRdy <= next_RXPacketRdy;
                RXFifoWEn <= next_RXFifoWEn;
                RXFifoData <= next_RXFifoData;
                CRCError <= next_CRCError;
                bitStuffError <= next_bitStuffError;
                RXOverflow <= next_RXOverflow;
                RXTimeOut <= next_RXTimeOut;
                ACKRxed <= next_ACKRxed;
                dataSequence <= next_dataSequence;
                RxPID <= next_RxPID;
        end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveGetpacket.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	sfielding	`//--------------------------------------------------------------------------------------------------`
2			`//`
3			`// Title : No Title`
4			`// Design : usbhostslave`
5			`// Author : Steve`
6			`// Company : Base2Designs`
7			`//`
8			`//-------------------------------------------------------------------------------------------------`
9			`//`
10			`// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveGetpacket.v`
11			`// Generated : 09/22/04 06:01:23`
12			`// From : c:\projects\USBHostSlave\RTL\slaveController\slaveGetpacket.asf`
13			`// By : FSM2VHDL ver. 4.0.5.2`
14			`//`
15			`//-------------------------------------------------------------------------------------------------`
16			`//`
17			`// Description :`
18			`//`
19			`//-------------------------------------------------------------------------------------------------`
20
21			`include "usbSerialInterfaceEngine_h.v"
22			`include "usbConstants_h.v"
23
24			`module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, bitStuffError, clk, dataSequence, getPacketEn, rst);`
25			`input [7:0] RXDataIn;`
26			`input RXDataValid;`
27			`input RXFifoFull;`
28			`input [7:0] RXStreamStatusIn;`
29			`input SIERxTimeOut; // Single cycle pulse`
30			`input clk;`
31			`input getPacketEn;`
32			`input rst;`
33			`output ACKRxed;`
34			`output CRCError;`
35			`output [7:0] RXFifoData;`
36			`output RXFifoWEn;`
37			`output RXOverflow;`
38			`output RXPacketRdy;`
39			`output RXTimeOut;`
40			`output [3:0] RxPID;`
41			`output bitStuffError;`
42			`output dataSequence;`
43
44			`reg ACKRxed, next_ACKRxed;`
45			`reg CRCError, next_CRCError;`
46			`wire [7:0] RXDataIn;`
47			`wire RXDataValid;`
48			`reg [7:0] RXFifoData, next_RXFifoData;`
49			`wire RXFifoFull;`
50			`reg RXFifoWEn, next_RXFifoWEn;`
51			`reg RXOverflow, next_RXOverflow;`
52			`reg RXPacketRdy, next_RXPacketRdy;`
53			`wire [7:0] RXStreamStatusIn;`
54			`reg RXTimeOut, next_RXTimeOut;`
55			`reg [3:0] RxPID, next_RxPID;`
56			`wire SIERxTimeOut;`
57			`reg bitStuffError, next_bitStuffError;`
58			`wire clk;`
59			`reg dataSequence, next_dataSequence;`
60			`wire getPacketEn;`
61			`wire rst;`
62
63			`// diagram signals declarations`
64			`reg [7:0]RXByteOld, next_RXByteOld;`
65			`reg [7:0]RXByteOldest, next_RXByteOldest;`
66			`reg [7:0]RXByte, next_RXByte;`
67			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
68
69			`// BINARY ENCODED state machine: slvGetPkt`
70			`// State codes definitions:`
71			`define PROC_PKT_CHK_PID 5'b00000
72			`define PROC_PKT_HS 5'b00001
73			`define PROC_PKT_DATA_W_D1 5'b00010
74			`define PROC_PKT_DATA_CHK_D1 5'b00011
75			`define PROC_PKT_DATA_W_D2 5'b00100
76			`define PROC_PKT_DATA_FIN 5'b00101
77			`define PROC_PKT_DATA_CHK_D2 5'b00110
78			`define PROC_PKT_DATA_W_D3 5'b00111
79			`define PROC_PKT_DATA_CHK_D3 5'b01000
80			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
81			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
82			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
83			`define START_GP 5'b01100
84			`define WAIT_PKT 5'b01101
85			`define CHK_PKT_START 5'b01110
86			`define WAIT_EN 5'b01111
87			`define PKT_RDY 5'b10000
88			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
89
90			`reg [4:0] CurrState_slvGetPkt;`
91			`reg [4:0] NextState_slvGetPkt;`
92
93
94			`//--------------------------------------------------------------------`
95			`// Machine: slvGetPkt`
96			`//--------------------------------------------------------------------`
97			`//----------------------------------`
98			`// NextState logic (combinatorial)`
99			`//----------------------------------`
100			`always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)`
101			`begin : slvGetPkt_NextState`
102			`NextState_slvGetPkt <= CurrState_slvGetPkt;`
103			`// Set default values for outputs and signals`
104			`next_CRCError <= CRCError;`
105			`next_bitStuffError <= bitStuffError;`
106			`next_RXOverflow <= RXOverflow;`
107			`next_RXTimeOut <= RXTimeOut;`
108			`next_ACKRxed <= ACKRxed;`
109			`next_dataSequence <= dataSequence;`
110			`next_RXByte <= RXByte;`
111			`next_RXStreamStatus <= RXStreamStatus;`
112			`next_RxPID <= RxPID;`
113			`next_RXPacketRdy <= RXPacketRdy;`
114			`next_RXByteOldest <= RXByteOldest;`
115			`next_RXByteOld <= RXByteOld;`
116			`next_RXFifoWEn <= RXFifoWEn;`
117			`next_RXFifoData <= RXFifoData;`
118			`case (CurrState_slvGetPkt) // synopsys parallel_case full_case`
119			`START_GP:
120			NextState_slvGetPkt <= `WAIT_EN;
121			`WAIT_PKT:
122			`begin`
123			`next_CRCError <= 1'b0;`
124			`next_bitStuffError <= 1'b0;`
125			`next_RXOverflow <= 1'b0;`
126			`next_RXTimeOut <= 1'b0;`
127			`next_ACKRxed <= 1'b0;`
128			`next_dataSequence <= 1'b0;`
129			`if (RXDataValid == 1'b1)`
130			`begin`
131			NextState_slvGetPkt <= `CHK_PKT_START;
132			`next_RXByte <= RXDataIn;`
133			`next_RXStreamStatus <= RXStreamStatusIn;`
134			`end`
135			`end`
136			`CHK_PKT_START:
137			if (RXStreamStatus == `RX_PACKET_START)
138			`begin`
139			NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
140			`next_RxPID <= RXByte[3:0];`
141			`end`
142			`else`
143			`begin`
144			NextState_slvGetPkt <= `PKT_RDY;
145			`next_RXTimeOut <= 1'b1;`
146			`end`
147			`WAIT_EN:
148			`begin`
149			`next_RXPacketRdy <= 1'b0;`
150			`if (getPacketEn == 1'b1)`
151			NextState_slvGetPkt <= `WAIT_PKT;
152			`end`
153			`PKT_RDY:
154			`begin`
155			`next_RXPacketRdy <= 1'b1;`
156			NextState_slvGetPkt <= `WAIT_EN;
157			`end`
158			`PROC_PKT_CHK_PID:
159			if (RXByte[1:0] == `HANDSHAKE)
160			NextState_slvGetPkt <= `PROC_PKT_HS;
161			else if (RXByte[1:0] == `DATA)
162			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
163			`else`
164			NextState_slvGetPkt <= `PKT_RDY;
165			`PROC_PKT_HS:
166			`if (RXDataValid == 1'b1)`
167			`begin`
168			NextState_slvGetPkt <= `PKT_RDY;
169			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
170			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
171			`end`
172			`PROC_PKT_DATA_W_D1:
173			`if (RXDataValid == 1'b1)`
174			`begin`
175			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
176			`next_RXByte <= RXDataIn;`
177			`next_RXStreamStatus <= RXStreamStatusIn;`
178			`end`
179			`PROC_PKT_DATA_CHK_D1:
180			if (RXStreamStatus == `RX_PACKET_STREAM)
181			`begin`
182			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
183			`next_RXByteOldest <= RXByte;`
184			`end`
185			`else`
186			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
187			`PROC_PKT_DATA_W_D2:
188			`if (RXDataValid == 1'b1)`
189			`begin`
190			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
191			`next_RXByte <= RXDataIn;`
192			`next_RXStreamStatus <= RXStreamStatusIn;`
193			`end`
194			`PROC_PKT_DATA_FIN:
195			`begin`
196			next_CRCError <= RXByte[`CRC_ERROR_BIT];
197			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
198			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
199			NextState_slvGetPkt <= `PKT_RDY;
200			`end`
201			`PROC_PKT_DATA_CHK_D2:
202			if (RXStreamStatus == `RX_PACKET_STREAM)
203			`begin`
204			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
205			`next_RXByteOld <= RXByte;`
206			`end`
207			`else`
208			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
209			`PROC_PKT_DATA_W_D3:
210			`if (RXDataValid == 1'b1)`
211			`begin`
212			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
213			`next_RXByte <= RXDataIn;`
214			`next_RXStreamStatus <= RXStreamStatusIn;`
215			`end`
216			`PROC_PKT_DATA_CHK_D3:
217			if (RXStreamStatus == `RX_PACKET_STREAM)
218			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
219			`else`
220			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
221			`PROC_PKT_DATA_LOOP_CHK_FIFO:
222			`if (RXFifoFull == 1'b1)`
223			`begin`
224			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
225			`next_RXOverflow <= 1'b1;`
226			`end`
227			`else`
228			`begin`
229			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
230			`next_RXFifoWEn <= 1'b1;`
231			`next_RXFifoData <= RXByteOldest;`
232			`next_RXByteOldest <= RXByteOld;`
233			`next_RXByteOld <= RXByte;`
234			`end`
235			`PROC_PKT_DATA_LOOP_FIFO_FULL:
236			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
237			`PROC_PKT_DATA_LOOP_W_D:
238			`begin`
239			`next_RXFifoWEn <= 1'b0;`
240			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
241			`begin`
242			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
243			`next_RXByte <= RXDataIn;`
244			`end`
245			`else if (RXDataValid == 1'b1)`
246			`begin`
247			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
248			`next_RXByte <= RXDataIn;`
249			`end`
250			`end`
251			`PROC_PKT_DATA_LOOP_DELAY:
252			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
253			`endcase`
254			`end`
255
256			`//----------------------------------`
257			`// Current State Logic (sequential)`
258			`//----------------------------------`
259			`always @ (posedge clk)`
260			`begin : slvGetPkt_CurrentState`
261			`if (rst)`
262			CurrState_slvGetPkt <= `START_GP;
263			`else`
264			`CurrState_slvGetPkt <= NextState_slvGetPkt;`
265			`end`
266
267			`//----------------------------------`
268			`// Registered outputs logic`
269			`//----------------------------------`
270			`always @ (posedge clk)`
271			`begin : slvGetPkt_RegOutput`
272			`if (rst)`
273			`begin`
274			`RXByteOld <= 8'h00;`
275			`RXByteOldest <= 8'h00;`
276			`RXByte <= 8'h00;`
277			`RXStreamStatus <= 8'h00;`
278			`RXPacketRdy <= 1'b0;`
279			`RXFifoWEn <= 1'b0;`
280			`RXFifoData <= 8'h00;`
281			`CRCError <= 1'b0;`
282			`bitStuffError <= 1'b0;`
283			`RXOverflow <= 1'b0;`
284			`RXTimeOut <= 1'b0;`
285			`ACKRxed <= 1'b0;`
286			`dataSequence <= 1'b0;`
287			`RxPID <= 4'h0;`
288			`end`
289			`else`
290			`begin`
291			`RXByteOld <= next_RXByteOld;`
292			`RXByteOldest <= next_RXByteOldest;`
293			`RXByte <= next_RXByte;`
294			`RXStreamStatus <= next_RXStreamStatus;`
295			`RXPacketRdy <= next_RXPacketRdy;`
296			`RXFifoWEn <= next_RXFifoWEn;`
297			`RXFifoData <= next_RXFifoData;`
298			`CRCError <= next_CRCError;`
299			`bitStuffError <= next_bitStuffError;`
300			`RXOverflow <= next_RXOverflow;`
301			`RXTimeOut <= next_RXTimeOut;`
302			`ACKRxed <= next_ACKRxed;`
303			`dataSequence <= next_dataSequence;`
304			`RxPID <= next_RxPID;`
305			`end`
306			`end`
307
308			`endmodule`