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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveGetpacket.v] - Blame information for rev 20

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveGetPacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut, SIERxTimeOutEn);
input   clk;
input   endPointReady;
input   getPacketEn;
input   rst;
input   [7:0]RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0]RXStreamStatusIn;
input   SIERxTimeOut;    // Single cycle pulse
output  ACKRxed;
output  bitStuffError;
output  CRCError;
output  dataSequence;
output  [7:0]RXFifoData;
output  RXFifoWEn;
output  RXOverflow;
output  RXPacketRdy;
output  [3:0]RxPID;
output  RXTimeOut;
output  SIERxTimeOutEn;
 
reg     ACKRxed, next_ACKRxed;
reg     bitStuffError, next_bitStuffError;
wire    clk;
reg     CRCError, next_CRCError;
reg     dataSequence, next_dataSequence;
wire    endPointReady;
wire    getPacketEn;
wire    rst;
wire    [7:0]RXDataIn;
wire    RXDataValid;
reg     [7:0]RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXOverflow, next_RXOverflow;
reg     RXPacketRdy, next_RXPacketRdy;
reg     [3:0]RxPID, next_RxPID;
wire    [7:0]RXStreamStatusIn;
reg     RXTimeOut, next_RXTimeOut;
wire    SIERxTimeOut;
reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
 
// diagram signals declarations
reg  [7:0]RXByte, next_RXByte;
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
 
// BINARY ENCODED state machine: slvGetPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
 
reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
 
 
// Machine: slvGetPkt
 
// NextState logic (combinatorial)
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_slvGetPkt)
begin
  NextState_slvGetPkt <= CurrState_slvGetPkt;
  // Set default values for outputs and signals
  next_RXOverflow <= RXOverflow;
  next_ACKRxed <= ACKRxed;
  next_RXByte <= RXByte;
  next_RXStreamStatus <= RXStreamStatus;
  next_RXByteOldest <= RXByteOldest;
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_dataSequence <= dataSequence;
  next_RXByteOld <= RXByteOld;
  next_RXFifoWEn <= RXFifoWEn;
  next_RXFifoData <= RXFifoData;
  next_RXPacketRdy <= RXPacketRdy;
  next_RXTimeOut <= RXTimeOut;
  next_RxPID <= RxPID;
  next_SIERxTimeOutEn <= SIERxTimeOutEn;
  case (CurrState_slvGetPkt)  // synopsys parallel_case full_case
    `START_GP:
    begin
      NextState_slvGetPkt <= `WAIT_EN;
    end
    `WAIT_PKT:
    begin
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RXOverflow <= 1'b0;
      next_RXTimeOut <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      next_SIERxTimeOutEn <= 1'b1;
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `CHK_PKT_START;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
      else if (SIERxTimeOut == 1'b1)
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `CHK_PKT_START:
    begin
      if (RXStreamStatus == `RX_PACKET_START)
      begin
        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
        next_RxPID <= RXByte[3:0];
      end
      else
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `WAIT_EN:
    begin
      next_RXPacketRdy <= 1'b0;
      next_SIERxTimeOutEn <= 1'b0;
      if (getPacketEn == 1'b1)
      begin
        NextState_slvGetPkt <= `WAIT_PKT;
      end
    end
    `PKT_RDY:
    begin
      next_RXPacketRdy <= 1'b1;
      NextState_slvGetPkt <= `WAIT_EN;
    end
    `PROC_PKT_CHK_PID:
    begin
      if (RXByte[1:0] == `HANDSHAKE)
      begin
        NextState_slvGetPkt <= `PROC_PKT_HS;
      end
      else if (RXByte[1:0] == `DATA)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
      end
      else
      begin
        NextState_slvGetPkt <= `PKT_RDY;
      end
    end
    `PROC_PKT_HS:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
      end
    end
    `PROC_PKT_DATA_W_D1:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D1:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
        next_RXByteOldest <= RXByte;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D2:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_FIN:
    begin
      next_CRCError <= RXByte[`CRC_ERROR_BIT];
      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
      NextState_slvGetPkt <= `PKT_RDY;
    end
    `PROC_PKT_DATA_CHK_D2:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
        next_RXByteOld <= RXByte;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D3:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D3:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_LOOP_CHK_FIFO:
    begin
      if (endPointReady == 1'b0)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
      end
      else if (RXFifoFull == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
        next_RXOverflow <= 1'b1;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
        next_RXFifoWEn <= 1'b1;
        next_RXFifoData <= RXByteOldest;
        next_RXByteOldest <= RXByteOld;
        next_RXByteOld <= RXByte;
      end
    end
    `PROC_PKT_DATA_LOOP_FIFO_FULL:
    begin
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
    end
    `PROC_PKT_DATA_LOOP_W_D:
    begin
      next_RXFifoWEn <= 1'b0;
      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
        next_RXByte <= RXDataIn;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
        next_RXByte <= RXDataIn;
      end
    end
    `PROC_PKT_DATA_LOOP_DELAY:
    begin
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
    end
    `PROC_PKT_DATA_LOOP_EP_N_RDY:    // Discard data
    begin
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvGetPkt <= `START_GP;
  else
    CurrState_slvGetPkt <= NextState_slvGetPkt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    RXOverflow <= 1'b0;
    ACKRxed <= 1'b0;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    dataSequence <= 1'b0;
    RXFifoWEn <= 1'b0;
    RXFifoData <= 8'h00;
    RXPacketRdy <= 1'b0;
    RXTimeOut <= 1'b0;
    RxPID <= 4'h0;
    SIERxTimeOutEn <= 1'b0;
    RXByte <= 8'h00;
    RXStreamStatus <= 8'h00;
    RXByteOldest <= 8'h00;
    RXByteOld <= 8'h00;
  end
  else
  begin
    RXOverflow <= next_RXOverflow;
    ACKRxed <= next_ACKRxed;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    dataSequence <= next_dataSequence;
    RXFifoWEn <= next_RXFifoWEn;
    RXFifoData <= next_RXFifoData;
    RXPacketRdy <= next_RXPacketRdy;
    RXTimeOut <= next_RXTimeOut;
    RxPID <= next_RxPID;
    SIERxTimeOutEn <= next_SIERxTimeOutEn;
    RXByte <= next_RXByte;
    RXStreamStatus <= next_RXStreamStatus;
    RXByteOldest <= next_RXByteOldest;
    RXByteOld <= next_RXByteOld;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveGetPacket`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45	9	sfielding	`timescale 1ns / 1ps
46	5	sfielding	`include "usbSerialInterfaceEngine_h.v"
47			`include "usbConstants_h.v"
48
49	20	sfielding	`module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut, SIERxTimeOutEn);`
50	5	sfielding	`input clk;`
51	18	sfielding	`input endPointReady;`
52	5	sfielding	`input getPacketEn;`
53			`input rst;`
54			`input [7:0]RXDataIn;`
55			`input RXDataValid;`
56			`input RXFifoFull;`
57			`input [7:0]RXStreamStatusIn;`
58			`input SIERxTimeOut; // Single cycle pulse`
59			`output ACKRxed;`
60			`output bitStuffError;`
61			`output CRCError;`
62			`output dataSequence;`
63			`output [7:0]RXFifoData;`
64			`output RXFifoWEn;`
65			`output RXOverflow;`
66			`output RXPacketRdy;`
67			`output [3:0]RxPID;`
68			`output RXTimeOut;`
69	20	sfielding	`output SIERxTimeOutEn;`
70	5	sfielding
71			`reg ACKRxed, next_ACKRxed;`
72			`reg bitStuffError, next_bitStuffError;`
73			`wire clk;`
74			`reg CRCError, next_CRCError;`
75			`reg dataSequence, next_dataSequence;`
76	18	sfielding	`wire endPointReady;`
77	5	sfielding	`wire getPacketEn;`
78			`wire rst;`
79			`wire [7:0]RXDataIn;`
80			`wire RXDataValid;`
81			`reg [7:0]RXFifoData, next_RXFifoData;`
82			`wire RXFifoFull;`
83			`reg RXFifoWEn, next_RXFifoWEn;`
84			`reg RXOverflow, next_RXOverflow;`
85			`reg RXPacketRdy, next_RXPacketRdy;`
86			`reg [3:0]RxPID, next_RxPID;`
87			`wire [7:0]RXStreamStatusIn;`
88			`reg RXTimeOut, next_RXTimeOut;`
89			`wire SIERxTimeOut;`
90	20	sfielding	`reg SIERxTimeOutEn, next_SIERxTimeOutEn;`
91	5	sfielding
92			`// diagram signals declarations`
93			`reg [7:0]RXByte, next_RXByte;`
94			`reg [7:0]RXByteOld, next_RXByteOld;`
95			`reg [7:0]RXByteOldest, next_RXByteOldest;`
96			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
97
98			`// BINARY ENCODED state machine: slvGetPkt`
99			`// State codes definitions:`
100			`define PROC_PKT_CHK_PID 5'b00000
101			`define PROC_PKT_HS 5'b00001
102			`define PROC_PKT_DATA_W_D1 5'b00010
103			`define PROC_PKT_DATA_CHK_D1 5'b00011
104			`define PROC_PKT_DATA_W_D2 5'b00100
105			`define PROC_PKT_DATA_FIN 5'b00101
106			`define PROC_PKT_DATA_CHK_D2 5'b00110
107			`define PROC_PKT_DATA_W_D3 5'b00111
108			`define PROC_PKT_DATA_CHK_D3 5'b01000
109			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
110			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
111			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
112			`define START_GP 5'b01100
113			`define WAIT_PKT 5'b01101
114			`define CHK_PKT_START 5'b01110
115			`define WAIT_EN 5'b01111
116			`define PKT_RDY 5'b10000
117			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
118	18	sfielding	`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
119	5	sfielding
120			`reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;`
121
122
123			`// Machine: slvGetPkt`
124
125			`// NextState logic (combinatorial)`
126	20	sfielding	`always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_slvGetPkt)`
127	5	sfielding	`begin`
128			`NextState_slvGetPkt <= CurrState_slvGetPkt;`
129			`// Set default values for outputs and signals`
130			`next_RXOverflow <= RXOverflow;`
131			`next_ACKRxed <= ACKRxed;`
132			`next_RXByte <= RXByte;`
133			`next_RXStreamStatus <= RXStreamStatus;`
134			`next_RXByteOldest <= RXByteOldest;`
135			`next_CRCError <= CRCError;`
136			`next_bitStuffError <= bitStuffError;`
137			`next_dataSequence <= dataSequence;`
138			`next_RXByteOld <= RXByteOld;`
139			`next_RXFifoWEn <= RXFifoWEn;`
140			`next_RXFifoData <= RXFifoData;`
141			`next_RXPacketRdy <= RXPacketRdy;`
142			`next_RXTimeOut <= RXTimeOut;`
143			`next_RxPID <= RxPID;`
144	20	sfielding	`next_SIERxTimeOutEn <= SIERxTimeOutEn;`
145	5	sfielding	`case (CurrState_slvGetPkt) // synopsys parallel_case full_case`
146			`START_GP:
147			`begin`
148			NextState_slvGetPkt <= `WAIT_EN;
149			`end`
150			`WAIT_PKT:
151			`begin`
152			`next_CRCError <= 1'b0;`
153			`next_bitStuffError <= 1'b0;`
154			`next_RXOverflow <= 1'b0;`
155			`next_RXTimeOut <= 1'b0;`
156			`next_ACKRxed <= 1'b0;`
157			`next_dataSequence <= 1'b0;`
158	20	sfielding	`next_SIERxTimeOutEn <= 1'b1;`
159	5	sfielding	`if (RXDataValid == 1'b1)`
160			`begin`
161			NextState_slvGetPkt <= `CHK_PKT_START;
162			`next_RXByte <= RXDataIn;`
163			`next_RXStreamStatus <= RXStreamStatusIn;`
164			`end`
165	9	sfielding	`else if (SIERxTimeOut == 1'b1)`
166			`begin`
167			NextState_slvGetPkt <= `PKT_RDY;
168			`next_RXTimeOut <= 1'b1;`
169			`end`
170	5	sfielding	`end`
171			`CHK_PKT_START:
172			`begin`
173			if (RXStreamStatus == `RX_PACKET_START)
174			`begin`
175			NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
176			`next_RxPID <= RXByte[3:0];`
177			`end`
178			`else`
179			`begin`
180			NextState_slvGetPkt <= `PKT_RDY;
181			`next_RXTimeOut <= 1'b1;`
182			`end`
183			`end`
184			`WAIT_EN:
185			`begin`
186			`next_RXPacketRdy <= 1'b0;`
187	20	sfielding	`next_SIERxTimeOutEn <= 1'b0;`
188	5	sfielding	`if (getPacketEn == 1'b1)`
189			`begin`
190			NextState_slvGetPkt <= `WAIT_PKT;
191			`end`
192			`end`
193			`PKT_RDY:
194			`begin`
195			`next_RXPacketRdy <= 1'b1;`
196			NextState_slvGetPkt <= `WAIT_EN;
197			`end`
198			`PROC_PKT_CHK_PID:
199			`begin`
200			if (RXByte[1:0] == `HANDSHAKE)
201			`begin`
202			NextState_slvGetPkt <= `PROC_PKT_HS;
203			`end`
204			else if (RXByte[1:0] == `DATA)
205			`begin`
206			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
207			`end`
208			`else`
209			`begin`
210			NextState_slvGetPkt <= `PKT_RDY;
211			`end`
212			`end`
213			`PROC_PKT_HS:
214			`begin`
215			`if (RXDataValid == 1'b1)`
216			`begin`
217			NextState_slvGetPkt <= `PKT_RDY;
218			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
219			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
220			`end`
221			`end`
222			`PROC_PKT_DATA_W_D1:
223			`begin`
224			`if (RXDataValid == 1'b1)`
225			`begin`
226			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
227			`next_RXByte <= RXDataIn;`
228			`next_RXStreamStatus <= RXStreamStatusIn;`
229			`end`
230			`end`
231			`PROC_PKT_DATA_CHK_D1:
232			`begin`
233			if (RXStreamStatus == `RX_PACKET_STREAM)
234			`begin`
235			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
236			`next_RXByteOldest <= RXByte;`
237			`end`
238			`else`
239			`begin`
240			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
241			`end`
242			`end`
243			`PROC_PKT_DATA_W_D2:
244			`begin`
245			`if (RXDataValid == 1'b1)`
246			`begin`
247			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
248			`next_RXByte <= RXDataIn;`
249			`next_RXStreamStatus <= RXStreamStatusIn;`
250			`end`
251			`end`
252			`PROC_PKT_DATA_FIN:
253			`begin`
254			next_CRCError <= RXByte[`CRC_ERROR_BIT];
255			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
256			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
257			NextState_slvGetPkt <= `PKT_RDY;
258			`end`
259			`PROC_PKT_DATA_CHK_D2:
260			`begin`
261			if (RXStreamStatus == `RX_PACKET_STREAM)
262			`begin`
263			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
264			`next_RXByteOld <= RXByte;`
265			`end`
266			`else`
267			`begin`
268			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
269			`end`
270			`end`
271			`PROC_PKT_DATA_W_D3:
272			`begin`
273			`if (RXDataValid == 1'b1)`
274			`begin`
275			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
276			`next_RXByte <= RXDataIn;`
277			`next_RXStreamStatus <= RXStreamStatusIn;`
278			`end`
279			`end`
280			`PROC_PKT_DATA_CHK_D3:
281			`begin`
282			if (RXStreamStatus == `RX_PACKET_STREAM)
283			`begin`
284			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
285			`end`
286			`else`
287			`begin`
288			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
289			`end`
290			`end`
291			`PROC_PKT_DATA_LOOP_CHK_FIFO:
292			`begin`
293	18	sfielding	`if (endPointReady == 1'b0)`
294	5	sfielding	`begin`
295	18	sfielding	NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
296			`end`
297			`else if (RXFifoFull == 1'b1)`
298			`begin`
299	5	sfielding	NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
300			`next_RXOverflow <= 1'b1;`
301			`end`
302			`else`
303			`begin`
304			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
305			`next_RXFifoWEn <= 1'b1;`
306			`next_RXFifoData <= RXByteOldest;`
307			`next_RXByteOldest <= RXByteOld;`
308			`next_RXByteOld <= RXByte;`
309			`end`
310			`end`
311			`PROC_PKT_DATA_LOOP_FIFO_FULL:
312			`begin`
313			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
314			`end`
315			`PROC_PKT_DATA_LOOP_W_D:
316			`begin`
317			`next_RXFifoWEn <= 1'b0;`
318			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
319			`begin`
320			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
321			`next_RXByte <= RXDataIn;`
322			`end`
323			`else if (RXDataValid == 1'b1)`
324			`begin`
325			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
326			`next_RXByte <= RXDataIn;`
327			`end`
328			`end`
329			`PROC_PKT_DATA_LOOP_DELAY:
330			`begin`
331			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
332			`end`
333	18	sfielding	`PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
334			`begin`
335			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
336			`end`
337	5	sfielding	`endcase`
338			`end`
339
340			`// Current State Logic (sequential)`
341			`always @ (posedge clk)`
342			`begin`
343			`if (rst)`
344			CurrState_slvGetPkt <= `START_GP;
345			`else`
346			`CurrState_slvGetPkt <= NextState_slvGetPkt;`
347			`end`
348
349			`// Registered outputs logic`
350			`always @ (posedge clk)`
351			`begin`
352			`if (rst)`
353			`begin`
354			`RXOverflow <= 1'b0;`
355			`ACKRxed <= 1'b0;`
356			`CRCError <= 1'b0;`
357			`bitStuffError <= 1'b0;`
358			`dataSequence <= 1'b0;`
359			`RXFifoWEn <= 1'b0;`
360			`RXFifoData <= 8'h00;`
361			`RXPacketRdy <= 1'b0;`
362			`RXTimeOut <= 1'b0;`
363			`RxPID <= 4'h0;`
364	20	sfielding	`SIERxTimeOutEn <= 1'b0;`
365	5	sfielding	`RXByte <= 8'h00;`
366			`RXStreamStatus <= 8'h00;`
367			`RXByteOldest <= 8'h00;`
368			`RXByteOld <= 8'h00;`
369			`end`
370			`else`
371			`begin`
372			`RXOverflow <= next_RXOverflow;`
373			`ACKRxed <= next_ACKRxed;`
374			`CRCError <= next_CRCError;`
375			`bitStuffError <= next_bitStuffError;`
376			`dataSequence <= next_dataSequence;`
377			`RXFifoWEn <= next_RXFifoWEn;`
378			`RXFifoData <= next_RXFifoData;`
379			`RXPacketRdy <= next_RXPacketRdy;`
380			`RXTimeOut <= next_RXTimeOut;`
381			`RxPID <= next_RxPID;`
382	20	sfielding	`SIERxTimeOutEn <= next_SIERxTimeOutEn;`
383	5	sfielding	`RXByte <= next_RXByte;`
384			`RXStreamStatus <= next_RXStreamStatus;`
385			`RXByteOldest <= next_RXByteOldest;`
386			`RXByteOld <= next_RXByteOld;`
387			`end`
388			`end`
389
390	2	sfielding	`endmodule`

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