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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveGetpacket.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveGetPacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: slaveGetpacket.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
input   clk;
input   getPacketEn;
input   rst;
input   [7:0]RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0]RXStreamStatusIn;
input   SIERxTimeOut;    // Single cycle pulse
output  ACKRxed;
output  bitStuffError;
output  CRCError;
output  dataSequence;
output  [7:0]RXFifoData;
output  RXFifoWEn;
output  RXOverflow;
output  RXPacketRdy;
output  [3:0]RxPID;
output  RXTimeOut;
 
reg     ACKRxed, next_ACKRxed;
reg     bitStuffError, next_bitStuffError;
wire    clk;
reg     CRCError, next_CRCError;
reg     dataSequence, next_dataSequence;
wire    getPacketEn;
wire    rst;
wire    [7:0]RXDataIn;
wire    RXDataValid;
reg     [7:0]RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXOverflow, next_RXOverflow;
reg     RXPacketRdy, next_RXPacketRdy;
reg     [3:0]RxPID, next_RxPID;
wire    [7:0]RXStreamStatusIn;
reg     RXTimeOut, next_RXTimeOut;
wire    SIERxTimeOut;
 
// diagram signals declarations
reg  [7:0]RXByte, next_RXByte;
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
 
// BINARY ENCODED state machine: slvGetPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
 
reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
 
 
// Machine: slvGetPkt
 
// NextState logic (combinatorial)
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
begin
  NextState_slvGetPkt <= CurrState_slvGetPkt;
  // Set default values for outputs and signals
  next_RXOverflow <= RXOverflow;
  next_ACKRxed <= ACKRxed;
  next_RXByte <= RXByte;
  next_RXStreamStatus <= RXStreamStatus;
  next_RXByteOldest <= RXByteOldest;
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_dataSequence <= dataSequence;
  next_RXByteOld <= RXByteOld;
  next_RXFifoWEn <= RXFifoWEn;
  next_RXFifoData <= RXFifoData;
  next_RXPacketRdy <= RXPacketRdy;
  next_RXTimeOut <= RXTimeOut;
  next_RxPID <= RxPID;
  case (CurrState_slvGetPkt)  // synopsys parallel_case full_case
    `START_GP:
    begin
      NextState_slvGetPkt <= `WAIT_EN;
    end
    `WAIT_PKT:
    begin
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RXOverflow <= 1'b0;
      next_RXTimeOut <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `CHK_PKT_START;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `CHK_PKT_START:
    begin
      if (RXStreamStatus == `RX_PACKET_START)
      begin
        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
        next_RxPID <= RXByte[3:0];
      end
      else
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `WAIT_EN:
    begin
      next_RXPacketRdy <= 1'b0;
      if (getPacketEn == 1'b1)
      begin
        NextState_slvGetPkt <= `WAIT_PKT;
      end
    end
    `PKT_RDY:
    begin
      next_RXPacketRdy <= 1'b1;
      NextState_slvGetPkt <= `WAIT_EN;
    end
    `PROC_PKT_CHK_PID:
    begin
      if (RXByte[1:0] == `HANDSHAKE)
      begin
        NextState_slvGetPkt <= `PROC_PKT_HS;
      end
      else if (RXByte[1:0] == `DATA)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
      end
      else
      begin
        NextState_slvGetPkt <= `PKT_RDY;
      end
    end
    `PROC_PKT_HS:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
      end
    end
    `PROC_PKT_DATA_W_D1:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D1:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
        next_RXByteOldest <= RXByte;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D2:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_FIN:
    begin
      next_CRCError <= RXByte[`CRC_ERROR_BIT];
      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
      NextState_slvGetPkt <= `PKT_RDY;
    end
    `PROC_PKT_DATA_CHK_D2:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
        next_RXByteOld <= RXByte;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_W_D3:
    begin
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    end
    `PROC_PKT_DATA_CHK_D3:
    begin
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
      end
    end
    `PROC_PKT_DATA_LOOP_CHK_FIFO:
    begin
      if (RXFifoFull == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
        next_RXOverflow <= 1'b1;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
        next_RXFifoWEn <= 1'b1;
        next_RXFifoData <= RXByteOldest;
        next_RXByteOldest <= RXByteOld;
        next_RXByteOld <= RXByte;
      end
    end
    `PROC_PKT_DATA_LOOP_FIFO_FULL:
    begin
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
    end
    `PROC_PKT_DATA_LOOP_W_D:
    begin
      next_RXFifoWEn <= 1'b0;
      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
        next_RXByte <= RXDataIn;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
        next_RXByte <= RXDataIn;
      end
    end
    `PROC_PKT_DATA_LOOP_DELAY:
    begin
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvGetPkt <= `START_GP;
  else
    CurrState_slvGetPkt <= NextState_slvGetPkt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    RXOverflow <= 1'b0;
    ACKRxed <= 1'b0;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    dataSequence <= 1'b0;
    RXFifoWEn <= 1'b0;
    RXFifoData <= 8'h00;
    RXPacketRdy <= 1'b0;
    RXTimeOut <= 1'b0;
    RxPID <= 4'h0;
    RXByte <= 8'h00;
    RXStreamStatus <= 8'h00;
    RXByteOldest <= 8'h00;
    RXByteOld <= 8'h00;
  end
  else
  begin
    RXOverflow <= next_RXOverflow;
    ACKRxed <= next_ACKRxed;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    dataSequence <= next_dataSequence;
    RXFifoWEn <= next_RXFifoWEn;
    RXFifoData <= next_RXFifoData;
    RXPacketRdy <= next_RXPacketRdy;
    RXTimeOut <= next_RXTimeOut;
    RxPID <= next_RxPID;
    RXByte <= next_RXByte;
    RXStreamStatus <= next_RXStreamStatus;
    RXByteOldest <= next_RXByteOldest;
    RXByteOld <= next_RXByteOld;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveGetpacket.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveGetPacket`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// $Id: slaveGetpacket.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`include "usbSerialInterfaceEngine_h.v"
52			`include "usbConstants_h.v"
53
54			`module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);`
55			`input clk;`
56			`input getPacketEn;`
57			`input rst;`
58			`input [7:0]RXDataIn;`
59			`input RXDataValid;`
60			`input RXFifoFull;`
61			`input [7:0]RXStreamStatusIn;`
62			`input SIERxTimeOut; // Single cycle pulse`
63			`output ACKRxed;`
64			`output bitStuffError;`
65			`output CRCError;`
66			`output dataSequence;`
67			`output [7:0]RXFifoData;`
68			`output RXFifoWEn;`
69			`output RXOverflow;`
70			`output RXPacketRdy;`
71			`output [3:0]RxPID;`
72			`output RXTimeOut;`
73
74			`reg ACKRxed, next_ACKRxed;`
75			`reg bitStuffError, next_bitStuffError;`
76			`wire clk;`
77			`reg CRCError, next_CRCError;`
78			`reg dataSequence, next_dataSequence;`
79			`wire getPacketEn;`
80			`wire rst;`
81			`wire [7:0]RXDataIn;`
82			`wire RXDataValid;`
83			`reg [7:0]RXFifoData, next_RXFifoData;`
84			`wire RXFifoFull;`
85			`reg RXFifoWEn, next_RXFifoWEn;`
86			`reg RXOverflow, next_RXOverflow;`
87			`reg RXPacketRdy, next_RXPacketRdy;`
88			`reg [3:0]RxPID, next_RxPID;`
89			`wire [7:0]RXStreamStatusIn;`
90			`reg RXTimeOut, next_RXTimeOut;`
91			`wire SIERxTimeOut;`
92
93			`// diagram signals declarations`
94			`reg [7:0]RXByte, next_RXByte;`
95			`reg [7:0]RXByteOld, next_RXByteOld;`
96			`reg [7:0]RXByteOldest, next_RXByteOldest;`
97			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
98
99			`// BINARY ENCODED state machine: slvGetPkt`
100			`// State codes definitions:`
101			`define PROC_PKT_CHK_PID 5'b00000
102			`define PROC_PKT_HS 5'b00001
103			`define PROC_PKT_DATA_W_D1 5'b00010
104			`define PROC_PKT_DATA_CHK_D1 5'b00011
105			`define PROC_PKT_DATA_W_D2 5'b00100
106			`define PROC_PKT_DATA_FIN 5'b00101
107			`define PROC_PKT_DATA_CHK_D2 5'b00110
108			`define PROC_PKT_DATA_W_D3 5'b00111
109			`define PROC_PKT_DATA_CHK_D3 5'b01000
110			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
111			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
112			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
113			`define START_GP 5'b01100
114			`define WAIT_PKT 5'b01101
115			`define CHK_PKT_START 5'b01110
116			`define WAIT_EN 5'b01111
117			`define PKT_RDY 5'b10000
118			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
119
120			`reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;`
121
122
123			`// Machine: slvGetPkt`
124
125			`// NextState logic (combinatorial)`
126			`always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)`
127			`begin`
128			`NextState_slvGetPkt <= CurrState_slvGetPkt;`
129			`// Set default values for outputs and signals`
130			`next_RXOverflow <= RXOverflow;`
131			`next_ACKRxed <= ACKRxed;`
132			`next_RXByte <= RXByte;`
133			`next_RXStreamStatus <= RXStreamStatus;`
134			`next_RXByteOldest <= RXByteOldest;`
135			`next_CRCError <= CRCError;`
136			`next_bitStuffError <= bitStuffError;`
137			`next_dataSequence <= dataSequence;`
138			`next_RXByteOld <= RXByteOld;`
139			`next_RXFifoWEn <= RXFifoWEn;`
140			`next_RXFifoData <= RXFifoData;`
141			`next_RXPacketRdy <= RXPacketRdy;`
142			`next_RXTimeOut <= RXTimeOut;`
143			`next_RxPID <= RxPID;`
144			`case (CurrState_slvGetPkt) // synopsys parallel_case full_case`
145			`START_GP:
146			`begin`
147			NextState_slvGetPkt <= `WAIT_EN;
148			`end`
149			`WAIT_PKT:
150			`begin`
151			`next_CRCError <= 1'b0;`
152			`next_bitStuffError <= 1'b0;`
153			`next_RXOverflow <= 1'b0;`
154			`next_RXTimeOut <= 1'b0;`
155			`next_ACKRxed <= 1'b0;`
156			`next_dataSequence <= 1'b0;`
157			`if (RXDataValid == 1'b1)`
158			`begin`
159			NextState_slvGetPkt <= `CHK_PKT_START;
160			`next_RXByte <= RXDataIn;`
161			`next_RXStreamStatus <= RXStreamStatusIn;`
162			`end`
163			`end`
164			`CHK_PKT_START:
165			`begin`
166			if (RXStreamStatus == `RX_PACKET_START)
167			`begin`
168			NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
169			`next_RxPID <= RXByte[3:0];`
170			`end`
171			`else`
172			`begin`
173			NextState_slvGetPkt <= `PKT_RDY;
174			`next_RXTimeOut <= 1'b1;`
175			`end`
176			`end`
177			`WAIT_EN:
178			`begin`
179			`next_RXPacketRdy <= 1'b0;`
180			`if (getPacketEn == 1'b1)`
181			`begin`
182			NextState_slvGetPkt <= `WAIT_PKT;
183			`end`
184			`end`
185			`PKT_RDY:
186			`begin`
187			`next_RXPacketRdy <= 1'b1;`
188			NextState_slvGetPkt <= `WAIT_EN;
189			`end`
190			`PROC_PKT_CHK_PID:
191			`begin`
192			if (RXByte[1:0] == `HANDSHAKE)
193			`begin`
194			NextState_slvGetPkt <= `PROC_PKT_HS;
195			`end`
196			else if (RXByte[1:0] == `DATA)
197			`begin`
198			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
199			`end`
200			`else`
201			`begin`
202			NextState_slvGetPkt <= `PKT_RDY;
203			`end`
204			`end`
205			`PROC_PKT_HS:
206			`begin`
207			`if (RXDataValid == 1'b1)`
208			`begin`
209			NextState_slvGetPkt <= `PKT_RDY;
210			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
211			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
212			`end`
213			`end`
214			`PROC_PKT_DATA_W_D1:
215			`begin`
216			`if (RXDataValid == 1'b1)`
217			`begin`
218			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
219			`next_RXByte <= RXDataIn;`
220			`next_RXStreamStatus <= RXStreamStatusIn;`
221			`end`
222			`end`
223			`PROC_PKT_DATA_CHK_D1:
224			`begin`
225			if (RXStreamStatus == `RX_PACKET_STREAM)
226			`begin`
227			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
228			`next_RXByteOldest <= RXByte;`
229			`end`
230			`else`
231			`begin`
232			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
233			`end`
234			`end`
235			`PROC_PKT_DATA_W_D2:
236			`begin`
237			`if (RXDataValid == 1'b1)`
238			`begin`
239			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
240			`next_RXByte <= RXDataIn;`
241			`next_RXStreamStatus <= RXStreamStatusIn;`
242			`end`
243			`end`
244			`PROC_PKT_DATA_FIN:
245			`begin`
246			next_CRCError <= RXByte[`CRC_ERROR_BIT];
247			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
248			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
249			NextState_slvGetPkt <= `PKT_RDY;
250			`end`
251			`PROC_PKT_DATA_CHK_D2:
252			`begin`
253			if (RXStreamStatus == `RX_PACKET_STREAM)
254			`begin`
255			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
256			`next_RXByteOld <= RXByte;`
257			`end`
258			`else`
259			`begin`
260			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
261			`end`
262			`end`
263			`PROC_PKT_DATA_W_D3:
264			`begin`
265			`if (RXDataValid == 1'b1)`
266			`begin`
267			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
268			`next_RXByte <= RXDataIn;`
269			`next_RXStreamStatus <= RXStreamStatusIn;`
270			`end`
271			`end`
272			`PROC_PKT_DATA_CHK_D3:
273			`begin`
274			if (RXStreamStatus == `RX_PACKET_STREAM)
275			`begin`
276			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
277			`end`
278			`else`
279			`begin`
280			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
281			`end`
282			`end`
283			`PROC_PKT_DATA_LOOP_CHK_FIFO:
284			`begin`
285			`if (RXFifoFull == 1'b1)`
286			`begin`
287			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
288			`next_RXOverflow <= 1'b1;`
289			`end`
290			`else`
291			`begin`
292			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
293			`next_RXFifoWEn <= 1'b1;`
294			`next_RXFifoData <= RXByteOldest;`
295			`next_RXByteOldest <= RXByteOld;`
296			`next_RXByteOld <= RXByte;`
297			`end`
298			`end`
299			`PROC_PKT_DATA_LOOP_FIFO_FULL:
300			`begin`
301			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
302			`end`
303			`PROC_PKT_DATA_LOOP_W_D:
304			`begin`
305			`next_RXFifoWEn <= 1'b0;`
306			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
307			`begin`
308			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
309			`next_RXByte <= RXDataIn;`
310			`end`
311			`else if (RXDataValid == 1'b1)`
312			`begin`
313			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
314			`next_RXByte <= RXDataIn;`
315			`end`
316			`end`
317			`PROC_PKT_DATA_LOOP_DELAY:
318			`begin`
319			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
320			`end`
321			`endcase`
322			`end`
323
324			`// Current State Logic (sequential)`
325			`always @ (posedge clk)`
326			`begin`
327			`if (rst)`
328			CurrState_slvGetPkt <= `START_GP;
329			`else`
330			`CurrState_slvGetPkt <= NextState_slvGetPkt;`
331			`end`
332
333			`// Registered outputs logic`
334			`always @ (posedge clk)`
335			`begin`
336			`if (rst)`
337			`begin`
338			`RXOverflow <= 1'b0;`
339			`ACKRxed <= 1'b0;`
340			`CRCError <= 1'b0;`
341			`bitStuffError <= 1'b0;`
342			`dataSequence <= 1'b0;`
343			`RXFifoWEn <= 1'b0;`
344			`RXFifoData <= 8'h00;`
345			`RXPacketRdy <= 1'b0;`
346			`RXTimeOut <= 1'b0;`
347			`RxPID <= 4'h0;`
348			`RXByte <= 8'h00;`
349			`RXStreamStatus <= 8'h00;`
350			`RXByteOldest <= 8'h00;`
351			`RXByteOld <= 8'h00;`
352			`end`
353			`else`
354			`begin`
355			`RXOverflow <= next_RXOverflow;`
356			`ACKRxed <= next_ACKRxed;`
357			`CRCError <= next_CRCError;`
358			`bitStuffError <= next_bitStuffError;`
359			`dataSequence <= next_dataSequence;`
360			`RXFifoWEn <= next_RXFifoWEn;`
361			`RXFifoData <= next_RXFifoData;`
362			`RXPacketRdy <= next_RXPacketRdy;`
363			`RXTimeOut <= next_RXTimeOut;`
364			`RxPID <= next_RxPID;`
365			`RXByte <= next_RXByte;`
366			`RXStreamStatus <= next_RXStreamStatus;`
367			`RXByteOldest <= next_RXByteOldest;`
368			`RXByteOld <= next_RXByteOld;`
369			`end`
370			`end`
371
372	2	sfielding	`endmodule`