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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveSendpacket.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveSendPacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: slaveSendpacket.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
input   clk;
input   [7:0]fifoData;
input   fifoEmpty;
input   [3:0]PID;
input   rst;
input   SCTxPortGnt;
input   SCTxPortRdy;
input   sendPacketWEn;
output  fifoReadEn;
output  [7:0]SCTxPortCntl;
output  [7:0]SCTxPortData;
output  SCTxPortReq;
output  SCTxPortWEn;
output  sendPacketRdy;
 
wire    clk;
wire    [7:0]fifoData;
wire    fifoEmpty;
reg     fifoReadEn, next_fifoReadEn;
wire    [3:0]PID;
wire    rst;
reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
reg     [7:0]SCTxPortData, next_SCTxPortData;
wire    SCTxPortGnt;
wire    SCTxPortRdy;
reg     SCTxPortReq, next_SCTxPortReq;
reg     SCTxPortWEn, next_SCTxPortWEn;
reg     sendPacketRdy, next_sendPacketRdy;
wire    sendPacketWEn;
 
// diagram signals declarations
reg  [7:0]PIDNotPID;
 
// BINARY ENCODED state machine: slvSndPkt
// State codes definitions:
`define START_SP1 4'b0000
`define SP_WAIT_ENABLE 4'b0001
`define SP1_WAIT_GNT 4'b0010
`define SP_SEND_PID_WAIT_RDY 4'b0011
`define SP_SEND_PID_FIN 4'b0100
`define FIN_SP1 4'b0101
`define SP_D0_D1_READ_FIFO 4'b0110
`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
`define SP_D0_D1_FIFO_EMPTY 4'b1000
`define SP_D0_D1_FIN 4'b1001
`define SP_D0_D1_TERM_BYTE 4'b1010
`define SP_NOT_DATA 4'b1011
`define SP_D0_D1_CLR_WEN 4'b1100
`define SP_D0_D1_CLR_REN 4'b1101
 
reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
always @(PID)
begin
PIDNotPID <=  { (PID ^ 4'hf), PID };
end
 
 
// Machine: slvSndPkt
 
// NextState logic (combinatorial)
always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
begin
  NextState_slvSndPkt <= CurrState_slvSndPkt;
  // Set default values for outputs and signals
  next_sendPacketRdy <= sendPacketRdy;
  next_fifoReadEn <= fifoReadEn;
  next_SCTxPortData <= SCTxPortData;
  next_SCTxPortCntl <= SCTxPortCntl;
  next_SCTxPortWEn <= SCTxPortWEn;
  next_SCTxPortReq <= SCTxPortReq;
  case (CurrState_slvSndPkt)  // synopsys parallel_case full_case
    `START_SP1:
    begin
      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
    end
    `SP_WAIT_ENABLE:
    begin
      if (sendPacketWEn == 1'b1)
      begin
        NextState_slvSndPkt <= `SP1_WAIT_GNT;
        next_sendPacketRdy <= 1'b0;
        next_SCTxPortReq <= 1'b1;
      end
    end
    `SP1_WAIT_GNT:
    begin
      if (SCTxPortGnt == 1'b1)
      begin
        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
      end
    end
    `FIN_SP1:
    begin
      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
      next_sendPacketRdy <= 1'b1;
      next_SCTxPortReq <= 1'b0;
    end
    `SP_NOT_DATA:
    begin
      NextState_slvSndPkt <= `FIN_SP1;
    end
    `SP_SEND_PID_WAIT_RDY:
    begin
      if (SCTxPortRdy == 1'b1)
      begin
        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
        next_SCTxPortWEn <= 1'b1;
        next_SCTxPortData <= PIDNotPID;
        next_SCTxPortCntl <= `TX_PACKET_START;
      end
    end
    `SP_SEND_PID_FIN:
    begin
      next_SCTxPortWEn <= 1'b0;
      if (PID == `DATA0 || PID == `DATA1)
      begin
        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
      end
      else
      begin
        NextState_slvSndPkt <= `SP_NOT_DATA;
      end
    end
    `SP_D0_D1_READ_FIFO:
    begin
      next_SCTxPortWEn <= 1'b1;
      next_SCTxPortData <= fifoData;
      next_SCTxPortCntl <= `TX_PACKET_STREAM;
      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
    end
    `SP_D0_D1_WAIT_READ_FIFO:
    begin
      if (SCTxPortRdy == 1'b1)
      begin
        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
        next_fifoReadEn <= 1'b1;
      end
    end
    `SP_D0_D1_FIFO_EMPTY:
    begin
      if (fifoEmpty == 1'b0)
      begin
        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
      end
      else
      begin
        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
      end
    end
    `SP_D0_D1_FIN:
    begin
      next_SCTxPortWEn <= 1'b0;
      NextState_slvSndPkt <= `FIN_SP1;
    end
    `SP_D0_D1_TERM_BYTE:
    begin
      if (SCTxPortRdy == 1'b1)
      begin
        NextState_slvSndPkt <= `SP_D0_D1_FIN;
        //Last byte is not valid data,
        //but the 'TX_PACKET_STOP' flag is required
        //by the SIE state machine to detect end of data packet
        next_SCTxPortWEn <= 1'b1;
        next_SCTxPortData <= 8'h00;
        next_SCTxPortCntl <= `TX_PACKET_STOP;
      end
    end
    `SP_D0_D1_CLR_WEN:
    begin
      next_SCTxPortWEn <= 1'b0;
      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
    end
    `SP_D0_D1_CLR_REN:
    begin
      next_fifoReadEn <= 1'b0;
      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvSndPkt <= `START_SP1;
  else
    CurrState_slvSndPkt <= NextState_slvSndPkt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    sendPacketRdy <= 1'b1;
    fifoReadEn <= 1'b0;
    SCTxPortData <= 8'h00;
    SCTxPortCntl <= 8'h00;
    SCTxPortWEn <= 1'b0;
    SCTxPortReq <= 1'b0;
  end
  else
  begin
    sendPacketRdy <= next_sendPacketRdy;
    fifoReadEn <= next_fifoReadEn;
    SCTxPortData <= next_SCTxPortData;
    SCTxPortCntl <= next_SCTxPortCntl;
    SCTxPortWEn <= next_SCTxPortWEn;
    SCTxPortReq <= next_SCTxPortReq;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveSendpacket.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveSendPacket`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// $Id: slaveSendpacket.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`timescale 1ns / 1ps
52			`include "usbSerialInterfaceEngine_h.v"
53			`include "usbConstants_h.v"
54
55			`module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);`
56			`input clk;`
57			`input [7:0]fifoData;`
58			`input fifoEmpty;`
59			`input [3:0]PID;`
60			`input rst;`
61			`input SCTxPortGnt;`
62			`input SCTxPortRdy;`
63			`input sendPacketWEn;`
64			`output fifoReadEn;`
65			`output [7:0]SCTxPortCntl;`
66			`output [7:0]SCTxPortData;`
67			`output SCTxPortReq;`
68			`output SCTxPortWEn;`
69			`output sendPacketRdy;`
70
71			`wire clk;`
72			`wire [7:0]fifoData;`
73			`wire fifoEmpty;`
74			`reg fifoReadEn, next_fifoReadEn;`
75			`wire [3:0]PID;`
76			`wire rst;`
77			`reg [7:0]SCTxPortCntl, next_SCTxPortCntl;`
78			`reg [7:0]SCTxPortData, next_SCTxPortData;`
79			`wire SCTxPortGnt;`
80			`wire SCTxPortRdy;`
81			`reg SCTxPortReq, next_SCTxPortReq;`
82			`reg SCTxPortWEn, next_SCTxPortWEn;`
83			`reg sendPacketRdy, next_sendPacketRdy;`
84			`wire sendPacketWEn;`
85
86			`// diagram signals declarations`
87			`reg [7:0]PIDNotPID;`
88
89			`// BINARY ENCODED state machine: slvSndPkt`
90			`// State codes definitions:`
91			`define START_SP1 4'b0000
92			`define SP_WAIT_ENABLE 4'b0001
93			`define SP1_WAIT_GNT 4'b0010
94			`define SP_SEND_PID_WAIT_RDY 4'b0011
95			`define SP_SEND_PID_FIN 4'b0100
96			`define FIN_SP1 4'b0101
97			`define SP_D0_D1_READ_FIFO 4'b0110
98			`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
99			`define SP_D0_D1_FIFO_EMPTY 4'b1000
100			`define SP_D0_D1_FIN 4'b1001
101			`define SP_D0_D1_TERM_BYTE 4'b1010
102			`define SP_NOT_DATA 4'b1011
103			`define SP_D0_D1_CLR_WEN 4'b1100
104			`define SP_D0_D1_CLR_REN 4'b1101
105
106			`reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;`
107
108			`// Diagram actions (continuous assignments allowed only: assign ...)`
109			`always @(PID)`
110			`begin`
111			`PIDNotPID <= { (PID ^ 4'hf), PID };`
112			`end`
113
114
115			`// Machine: slvSndPkt`
116
117			`// NextState logic (combinatorial)`
118			`always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)`
119			`begin`
120			`NextState_slvSndPkt <= CurrState_slvSndPkt;`
121			`// Set default values for outputs and signals`
122			`next_sendPacketRdy <= sendPacketRdy;`
123			`next_fifoReadEn <= fifoReadEn;`
124			`next_SCTxPortData <= SCTxPortData;`
125			`next_SCTxPortCntl <= SCTxPortCntl;`
126			`next_SCTxPortWEn <= SCTxPortWEn;`
127			`next_SCTxPortReq <= SCTxPortReq;`
128			`case (CurrState_slvSndPkt) // synopsys parallel_case full_case`
129			`START_SP1:
130			`begin`
131			NextState_slvSndPkt <= `SP_WAIT_ENABLE;
132			`end`
133			`SP_WAIT_ENABLE:
134			`begin`
135			`if (sendPacketWEn == 1'b1)`
136			`begin`
137			NextState_slvSndPkt <= `SP1_WAIT_GNT;
138			`next_sendPacketRdy <= 1'b0;`
139			`next_SCTxPortReq <= 1'b1;`
140			`end`
141			`end`
142			`SP1_WAIT_GNT:
143			`begin`
144			`if (SCTxPortGnt == 1'b1)`
145			`begin`
146			NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
147			`end`
148			`end`
149			`FIN_SP1:
150			`begin`
151			NextState_slvSndPkt <= `SP_WAIT_ENABLE;
152			`next_sendPacketRdy <= 1'b1;`
153			`next_SCTxPortReq <= 1'b0;`
154			`end`
155			`SP_NOT_DATA:
156			`begin`
157			NextState_slvSndPkt <= `FIN_SP1;
158			`end`
159			`SP_SEND_PID_WAIT_RDY:
160			`begin`
161			`if (SCTxPortRdy == 1'b1)`
162			`begin`
163			NextState_slvSndPkt <= `SP_SEND_PID_FIN;
164			`next_SCTxPortWEn <= 1'b1;`
165			`next_SCTxPortData <= PIDNotPID;`
166			next_SCTxPortCntl <= `TX_PACKET_START;
167			`end`
168			`end`
169			`SP_SEND_PID_FIN:
170			`begin`
171			`next_SCTxPortWEn <= 1'b0;`
172			if (PID == `DATA0 \|\| PID == `DATA1)
173			`begin`
174			NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
175			`end`
176			`else`
177			`begin`
178			NextState_slvSndPkt <= `SP_NOT_DATA;
179			`end`
180			`end`
181			`SP_D0_D1_READ_FIFO:
182			`begin`
183			`next_SCTxPortWEn <= 1'b1;`
184			`next_SCTxPortData <= fifoData;`
185			next_SCTxPortCntl <= `TX_PACKET_STREAM;
186			NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
187			`end`
188			`SP_D0_D1_WAIT_READ_FIFO:
189			`begin`
190			`if (SCTxPortRdy == 1'b1)`
191			`begin`
192			NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
193			`next_fifoReadEn <= 1'b1;`
194			`end`
195			`end`
196			`SP_D0_D1_FIFO_EMPTY:
197			`begin`
198			`if (fifoEmpty == 1'b0)`
199			`begin`
200			NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
201			`end`
202			`else`
203			`begin`
204			NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
205			`end`
206			`end`
207			`SP_D0_D1_FIN:
208			`begin`
209			`next_SCTxPortWEn <= 1'b0;`
210			NextState_slvSndPkt <= `FIN_SP1;
211			`end`
212			`SP_D0_D1_TERM_BYTE:
213			`begin`
214			`if (SCTxPortRdy == 1'b1)`
215			`begin`
216			NextState_slvSndPkt <= `SP_D0_D1_FIN;
217			`//Last byte is not valid data,`
218			`//but the 'TX_PACKET_STOP' flag is required`
219			`//by the SIE state machine to detect end of data packet`
220			`next_SCTxPortWEn <= 1'b1;`
221			`next_SCTxPortData <= 8'h00;`
222			next_SCTxPortCntl <= `TX_PACKET_STOP;
223			`end`
224			`end`
225			`SP_D0_D1_CLR_WEN:
226			`begin`
227			`next_SCTxPortWEn <= 1'b0;`
228			NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
229			`end`
230			`SP_D0_D1_CLR_REN:
231			`begin`
232			`next_fifoReadEn <= 1'b0;`
233			NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
234			`end`
235			`endcase`
236			`end`
237
238			`// Current State Logic (sequential)`
239			`always @ (posedge clk)`
240			`begin`
241			`if (rst)`
242			CurrState_slvSndPkt <= `START_SP1;
243			`else`
244			`CurrState_slvSndPkt <= NextState_slvSndPkt;`
245			`end`
246
247			`// Registered outputs logic`
248			`always @ (posedge clk)`
249			`begin`
250			`if (rst)`
251			`begin`
252			`sendPacketRdy <= 1'b1;`
253			`fifoReadEn <= 1'b0;`
254			`SCTxPortData <= 8'h00;`
255			`SCTxPortCntl <= 8'h00;`
256			`SCTxPortWEn <= 1'b0;`
257			`SCTxPortReq <= 1'b0;`
258			`end`
259			`else`
260			`begin`
261			`sendPacketRdy <= next_sendPacketRdy;`
262			`fifoReadEn <= next_fifoReadEn;`
263			`SCTxPortData <= next_SCTxPortData;`
264			`SCTxPortCntl <= next_SCTxPortCntl;`
265			`SCTxPortWEn <= next_SCTxPortWEn;`
266			`SCTxPortReq <= next_SCTxPortReq;`
267			`end`
268			`end`
269
270	2	sfielding	`endmodule`