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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slavecontroller.v] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbSlaveControl_h.v"
`include "usbConstants_h.v"
 
 
module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
input   bitStuffError;
input   clk;
input   CRCError;
input   getPacketRdy;
input   rst;
input   [7:0]RxByte;
input   RxDataWEn;
input   RxOverflow;
input   [7:0]RxStatus;
input   RxTimeOut;
input   SCGlobalEn;
input   sendPacketRdy;
input   [4:0]USBEndPControlReg;
input   [6:0]USBTgtAddress;
output  clrEPRdy;
output  endPMuxErrorsWEn;
output  [10:0]frameNum;
output  getPacketREn;
output  NAKSent;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
output  SOFRxed;
output  stallSent;
output  transDone;
output  [3:0]USBEndP;
output  [1:0]USBEndPNakTransTypeReg;
output  [1:0]USBEndPTransTypeReg;
 
wire    bitStuffError;
wire    clk;
reg     clrEPRdy, next_clrEPRdy;
wire    CRCError;
reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
reg     [10:0]frameNum, next_frameNum;
wire    getPacketRdy;
reg     getPacketREn, next_getPacketREn;
reg     NAKSent, next_NAKSent;
wire    rst;
wire    [7:0]RxByte;
wire    RxDataWEn;
wire    RxOverflow;
wire    [7:0]RxStatus;
wire    RxTimeOut;
wire    SCGlobalEn;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     SOFRxed, next_SOFRxed;
reg     stallSent, next_stallSent;
reg     transDone, next_transDone;
reg     [3:0]USBEndP, next_USBEndP;
wire    [4:0]USBEndPControlReg;
reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
wire    [6:0]USBTgtAddress;
 
// diagram signals declarations
reg  [7:0]addrEndPTemp, next_addrEndPTemp;
reg  [7:0]endpCRCTemp, next_endpCRCTemp;
reg  [7:0]PIDByte, next_PIDByte;
reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
reg  [6:0]USBAddress, next_USBAddress;
 
// BINARY ENCODED state machine: slvCntrl
// State codes definitions:
`define WAIT_RX1 5'b00000
`define FIN_SC 5'b00001
`define GET_TOKEN_WAIT_CRC 5'b00010
`define GET_TOKEN_WAIT_ADDR 5'b00011
`define GET_TOKEN_WAIT_STOP 5'b00100
`define CHK_PID 5'b00101
`define GET_TOKEN_CHK_SOF 5'b00110
`define PID_ERROR 5'b00111
`define CHK_RDY 5'b01000
`define IN_NAK_STALL 5'b01001
`define IN_CHK_RDY 5'b01010
`define SETUP_OUT_CHK 5'b01011
`define SETUP_OUT_SEND 5'b01100
`define SETUP_OUT_GET_PKT 5'b01101
`define START_S1 5'b01110
`define GET_TOKEN_DELAY 5'b01111
`define GET_TOKEN_CHK_ADDR 5'b10000
`define IN_RESP_GET_RESP 5'b10001
`define IN_RESP_DATA 5'b10010
`define IN_RESP_CHK_ISO 5'b10011
 
reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
 
 
// Machine: slvCntrl
 
// NextState logic (combinatorial)
always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
begin
  NextState_slvCntrl <= CurrState_slvCntrl;
  // Set default values for outputs and signals
  next_stallSent <= stallSent;
  next_NAKSent <= NAKSent;
  next_SOFRxed <= SOFRxed;
  next_PIDByte <= PIDByte;
  next_transDone <= transDone;
  next_clrEPRdy <= clrEPRdy;
  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
  next_endpCRCTemp <= endpCRCTemp;
  next_addrEndPTemp <= addrEndPTemp;
  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
  next_frameNum <= frameNum;
  next_USBAddress <= USBAddress;
  next_USBEndP <= USBEndP;
  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketPID <= sendPacketPID;
  next_getPacketREn <= getPacketREn;
  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
    `WAIT_RX1:
    begin
      next_stallSent <= 1'b0;
      next_NAKSent <= 1'b0;
      next_SOFRxed <= 1'b0;
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_START &&
        RxByte[1:0] == `TOKEN)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
        next_PIDByte <= RxByte;
      end
    end
    `FIN_SC:
    begin
      next_transDone <= 1'b0;
      next_clrEPRdy <= 1'b0;
      next_endPMuxErrorsWEn <= 1'b0;
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_PID:
    begin
      if (PIDByte[3:0] == `SETUP)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if (PIDByte[3:0] == `OUT)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `IN_CHK_RDY;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
      end
      else if (((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
      else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1))
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
      else if (PIDByte[3:0] == `IN)
      begin
        NextState_slvCntrl <= `CHK_RDY;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
      end
      else
      begin
        NextState_slvCntrl <= `PID_ERROR;
      end
    end
    `PID_ERROR:
    begin
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_RDY:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_transDone <= 1'b1;
        next_clrEPRdy <= 1'b1;
        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else if (NAKSent == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `FIN_SC;
      end
    end
    `SETUP_OUT_CHK:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    end
    `SETUP_OUT_SEND:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `SETUP_OUT_GET_PKT:
    begin
      next_getPacketREn <= 1'b0;
      if ((getPacketRdy == 1'b1) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
      else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
        bitStuffError == 1'b0 &&
        RxOverflow == 1'b0 &&
        RxTimeOut == 1'b0))
      begin
        NextState_slvCntrl <= `SETUP_OUT_CHK;
      end
      else if (getPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_NAK_STALL:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_CHK_RDY:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
      else
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    end
    `IN_RESP_GET_RESP:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_RESP_DATA:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `IN_RESP_CHK_ISO;
      end
    end
    `IN_RESP_CHK_ISO:
    begin
      if (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
      else
      begin
        NextState_slvCntrl <= `IN_RESP_GET_RESP;
        next_getPacketREn <= 1'b1;
      end
    end
    `START_S1:
    begin
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `GET_TOKEN_WAIT_CRC:
    begin
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
        next_endpCRCTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_WAIT_ADDR:
    begin
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
        next_addrEndPTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_WAIT_STOP:
    begin
      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
      end
      else if (RxDataWEn == 1'b1)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_CHK_SOF:
    begin
      if (PIDByte[3:0] == `SOF)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
        next_SOFRxed <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `GET_TOKEN_DELAY;
        next_USBAddress <= addrEndPTemp[6:0];
        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
      end
    end
    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndPControlReg to update
    begin
      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
    end
    `GET_TOKEN_CHK_ADDR:
    begin
      if (USBEndP < `NUM_OF_ENDPOINTS  &&
        USBAddress == USBTgtAddress &&
        SCGlobalEn == 1'b1 &&
        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_PID;
      end
      else
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvCntrl <= `START_S1;
  else
    CurrState_slvCntrl <= NextState_slvCntrl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    stallSent <= 1'b0;
    NAKSent <= 1'b0;
    SOFRxed <= 1'b0;
    transDone <= 1'b0;
    clrEPRdy <= 1'b0;
    endPMuxErrorsWEn <= 1'b0;
    frameNum <= 11'b00000000000;
    USBEndP <= 4'h0;
    USBEndPTransTypeReg <= 2'b00;
    USBEndPNakTransTypeReg <= 2'b00;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
    getPacketREn <= 1'b0;
    PIDByte <= 8'h00;
    endpCRCTemp <= 8'h00;
    addrEndPTemp <= 8'h00;
    tempUSBEndPTransTypeReg <= 2'b00;
    USBAddress <= 7'b0000000;
  end
  else
  begin
    stallSent <= next_stallSent;
    NAKSent <= next_NAKSent;
    SOFRxed <= next_SOFRxed;
    transDone <= next_transDone;
    clrEPRdy <= next_clrEPRdy;
    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
    frameNum <= next_frameNum;
    USBEndP <= next_USBEndP;
    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
    getPacketREn <= next_getPacketREn;
    PIDByte <= next_PIDByte;
    endpCRCTemp <= next_endpCRCTemp;
    addrEndPTemp <= next_addrEndPTemp;
    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
    USBAddress <= next_USBAddress;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveController`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbSlaveControl_h.v"
48			`include "usbConstants_h.v"
49
50
51			`module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);`
52			`input bitStuffError;`
53			`input clk;`
54			`input CRCError;`
55			`input getPacketRdy;`
56			`input rst;`
57			`input [7:0]RxByte;`
58			`input RxDataWEn;`
59			`input RxOverflow;`
60			`input [7:0]RxStatus;`
61			`input RxTimeOut;`
62			`input SCGlobalEn;`
63			`input sendPacketRdy;`
64	14	sfielding	`input [4:0]USBEndPControlReg;`
65	5	sfielding	`input [6:0]USBTgtAddress;`
66			`output clrEPRdy;`
67			`output endPMuxErrorsWEn;`
68			`output [10:0]frameNum;`
69			`output getPacketREn;`
70			`output NAKSent;`
71			`output [3:0]sendPacketPID;`
72			`output sendPacketWEn;`
73			`output SOFRxed;`
74			`output stallSent;`
75			`output transDone;`
76			`output [3:0]USBEndP;`
77			`output [1:0]USBEndPNakTransTypeReg;`
78			`output [1:0]USBEndPTransTypeReg;`
79
80			`wire bitStuffError;`
81			`wire clk;`
82			`reg clrEPRdy, next_clrEPRdy;`
83			`wire CRCError;`
84			`reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;`
85			`reg [10:0]frameNum, next_frameNum;`
86			`wire getPacketRdy;`
87			`reg getPacketREn, next_getPacketREn;`
88			`reg NAKSent, next_NAKSent;`
89			`wire rst;`
90			`wire [7:0]RxByte;`
91			`wire RxDataWEn;`
92			`wire RxOverflow;`
93			`wire [7:0]RxStatus;`
94			`wire RxTimeOut;`
95			`wire SCGlobalEn;`
96			`reg [3:0]sendPacketPID, next_sendPacketPID;`
97			`wire sendPacketRdy;`
98			`reg sendPacketWEn, next_sendPacketWEn;`
99			`reg SOFRxed, next_SOFRxed;`
100			`reg stallSent, next_stallSent;`
101			`reg transDone, next_transDone;`
102			`reg [3:0]USBEndP, next_USBEndP;`
103	14	sfielding	`wire [4:0]USBEndPControlReg;`
104	5	sfielding	`reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;`
105			`reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;`
106			`wire [6:0]USBTgtAddress;`
107
108			`// diagram signals declarations`
109			`reg [7:0]addrEndPTemp, next_addrEndPTemp;`
110			`reg [7:0]endpCRCTemp, next_endpCRCTemp;`
111			`reg [7:0]PIDByte, next_PIDByte;`
112			`reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;`
113			`reg [6:0]USBAddress, next_USBAddress;`
114
115			`// BINARY ENCODED state machine: slvCntrl`
116			`// State codes definitions:`
117			`define WAIT_RX1 5'b00000
118			`define FIN_SC 5'b00001
119			`define GET_TOKEN_WAIT_CRC 5'b00010
120			`define GET_TOKEN_WAIT_ADDR 5'b00011
121			`define GET_TOKEN_WAIT_STOP 5'b00100
122			`define CHK_PID 5'b00101
123			`define GET_TOKEN_CHK_SOF 5'b00110
124			`define PID_ERROR 5'b00111
125			`define CHK_RDY 5'b01000
126			`define IN_NAK_STALL 5'b01001
127			`define IN_CHK_RDY 5'b01010
128	14	sfielding	`define SETUP_OUT_CHK 5'b01011
129			`define SETUP_OUT_SEND 5'b01100
130			`define SETUP_OUT_GET_PKT 5'b01101
131			`define START_S1 5'b01110
132			`define GET_TOKEN_DELAY 5'b01111
133			`define GET_TOKEN_CHK_ADDR 5'b10000
134			`define IN_RESP_GET_RESP 5'b10001
135			`define IN_RESP_DATA 5'b10010
136			`define IN_RESP_CHK_ISO 5'b10011
137	5	sfielding
138			`reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;`
139
140
141			`// Machine: slvCntrl`
142
143			`// NextState logic (combinatorial)`
144			`always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)`
145			`begin`
146			`NextState_slvCntrl <= CurrState_slvCntrl;`
147			`// Set default values for outputs and signals`
148			`next_stallSent <= stallSent;`
149			`next_NAKSent <= NAKSent;`
150			`next_SOFRxed <= SOFRxed;`
151			`next_PIDByte <= PIDByte;`
152			`next_transDone <= transDone;`
153			`next_clrEPRdy <= clrEPRdy;`
154			`next_endPMuxErrorsWEn <= endPMuxErrorsWEn;`
155			`next_endpCRCTemp <= endpCRCTemp;`
156			`next_addrEndPTemp <= addrEndPTemp;`
157			`next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
158			`next_frameNum <= frameNum;`
159			`next_USBAddress <= USBAddress;`
160			`next_USBEndP <= USBEndP;`
161			`next_USBEndPTransTypeReg <= USBEndPTransTypeReg;`
162			`next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;`
163			`next_sendPacketWEn <= sendPacketWEn;`
164			`next_sendPacketPID <= sendPacketPID;`
165			`next_getPacketREn <= getPacketREn;`
166			`case (CurrState_slvCntrl) // synopsys parallel_case full_case`
167			`WAIT_RX1:
168			`begin`
169			`next_stallSent <= 1'b0;`
170			`next_NAKSent <= 1'b0;`
171			`next_SOFRxed <= 1'b0;`
172			`if (RxDataWEn == 1'b1 &&`
173			RxStatus == `RX_PACKET_START &&
174			RxByte[1:0] == `TOKEN)
175			`begin`
176			NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
177			`next_PIDByte <= RxByte;`
178			`end`
179			`end`
180			`FIN_SC:
181			`begin`
182			`next_transDone <= 1'b0;`
183			`next_clrEPRdy <= 1'b0;`
184			`next_endPMuxErrorsWEn <= 1'b0;`
185			NextState_slvCntrl <= `WAIT_RX1;
186			`end`
187			`CHK_PID:
188			`begin`
189			if (PIDByte[3:0] == `SETUP)
190			`begin`
191			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
192			next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
193			`next_getPacketREn <= 1'b1;`
194			`end`
195			else if (PIDByte[3:0] == `OUT)
196			`begin`
197			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
198			next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
199			`next_getPacketREn <= 1'b1;`
200			`end`
201	14	sfielding	else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
202	5	sfielding	`begin`
203			NextState_slvCntrl <= `IN_CHK_RDY;
204			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
205			`end`
206	14	sfielding	else if (((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
207			`begin`
208			NextState_slvCntrl <= `IN_RESP_DATA;
209			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
210			`next_sendPacketWEn <= 1'b1;`
211			next_sendPacketPID <= `DATA0;
212			`end`
213			else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1))
214			`begin`
215			NextState_slvCntrl <= `IN_RESP_DATA;
216			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
217			`next_sendPacketWEn <= 1'b1;`
218			next_sendPacketPID <= `DATA1;
219			`end`
220			else if (PIDByte[3:0] == `IN)
221			`begin`
222			NextState_slvCntrl <= `CHK_RDY;
223			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
224			`end`
225	5	sfielding	`else`
226			`begin`
227			NextState_slvCntrl <= `PID_ERROR;
228			`end`
229			`end`
230			`PID_ERROR:
231			`begin`
232			NextState_slvCntrl <= `WAIT_RX1;
233			`end`
234			`CHK_RDY:
235			`begin`
236			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
237			`begin`
238			NextState_slvCntrl <= `FIN_SC;
239			`next_transDone <= 1'b1;`
240			`next_clrEPRdy <= 1'b1;`
241			`next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
242			`next_endPMuxErrorsWEn <= 1'b1;`
243			`end`
244			`else if (NAKSent == 1'b1)`
245			`begin`
246			NextState_slvCntrl <= `FIN_SC;
247			`next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;`
248			`next_endPMuxErrorsWEn <= 1'b1;`
249			`end`
250			`else`
251			`begin`
252			NextState_slvCntrl <= `FIN_SC;
253			`end`
254			`end`
255			`SETUP_OUT_CHK:
256			`begin`
257			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
258			`begin`
259			NextState_slvCntrl <= `SETUP_OUT_SEND;
260			`next_sendPacketWEn <= 1'b1;`
261			next_sendPacketPID <= `NAK;
262			`next_NAKSent <= 1'b1;`
263			`end`
264			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
265			`begin`
266			NextState_slvCntrl <= `SETUP_OUT_SEND;
267			`next_sendPacketWEn <= 1'b1;`
268			next_sendPacketPID <= `STALL;
269			`next_stallSent <= 1'b1;`
270			`end`
271			`else`
272			`begin`
273			NextState_slvCntrl <= `SETUP_OUT_SEND;
274			`next_sendPacketWEn <= 1'b1;`
275			next_sendPacketPID <= `ACK;
276			`end`
277			`end`
278			`SETUP_OUT_SEND:
279			`begin`
280			`next_sendPacketWEn <= 1'b0;`
281			`if (sendPacketRdy == 1'b1)`
282			`begin`
283			NextState_slvCntrl <= `CHK_RDY;
284			`end`
285			`end`
286			`SETUP_OUT_GET_PKT:
287			`begin`
288			`next_getPacketREn <= 1'b0;`
289	14	sfielding	if ((getPacketRdy == 1'b1) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
290			`begin`
291			NextState_slvCntrl <= `CHK_RDY;
292			`end`
293			`else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&`
294	5	sfielding	`bitStuffError == 1'b0 &&`
295			`RxOverflow == 1'b0 &&`
296			`RxTimeOut == 1'b0))`
297			`begin`
298			NextState_slvCntrl <= `SETUP_OUT_CHK;
299			`end`
300			`else if (getPacketRdy == 1'b1)`
301			`begin`
302			NextState_slvCntrl <= `CHK_RDY;
303			`end`
304			`end`
305			`IN_NAK_STALL:
306			`begin`
307			`next_sendPacketWEn <= 1'b0;`
308			`if (sendPacketRdy == 1'b1)`
309			`begin`
310			NextState_slvCntrl <= `CHK_RDY;
311			`end`
312			`end`
313			`IN_CHK_RDY:
314			`begin`
315			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
316			`begin`
317			NextState_slvCntrl <= `IN_NAK_STALL;
318			`next_sendPacketWEn <= 1'b1;`
319			next_sendPacketPID <= `NAK;
320			`next_NAKSent <= 1'b1;`
321			`end`
322			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
323			`begin`
324			NextState_slvCntrl <= `IN_NAK_STALL;
325			`next_sendPacketWEn <= 1'b1;`
326			next_sendPacketPID <= `STALL;
327			`next_stallSent <= 1'b1;`
328			`end`
329			else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
330			`begin`
331	14	sfielding	NextState_slvCntrl <= `IN_RESP_DATA;
332	5	sfielding	`next_sendPacketWEn <= 1'b1;`
333			next_sendPacketPID <= `DATA0;
334			`end`
335			`else`
336			`begin`
337	14	sfielding	NextState_slvCntrl <= `IN_RESP_DATA;
338	5	sfielding	`next_sendPacketWEn <= 1'b1;`
339			next_sendPacketPID <= `DATA1;
340			`end`
341			`end`
342	14	sfielding	`IN_RESP_GET_RESP:
343	5	sfielding	`begin`
344	14	sfielding	`next_getPacketREn <= 1'b0;`
345			`if (getPacketRdy == 1'b1)`
346			`begin`
347			NextState_slvCntrl <= `CHK_RDY;
348			`end`
349			`end`
350			`IN_RESP_DATA:
351			`begin`
352	5	sfielding	`next_sendPacketWEn <= 1'b0;`
353			`if (sendPacketRdy == 1'b1)`
354			`begin`
355	14	sfielding	NextState_slvCntrl <= `IN_RESP_CHK_ISO;
356	5	sfielding	`end`
357			`end`
358	14	sfielding	`IN_RESP_CHK_ISO:
359	5	sfielding	`begin`
360	14	sfielding	if (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
361	5	sfielding	`begin`
362			NextState_slvCntrl <= `CHK_RDY;
363			`end`
364	14	sfielding	`else`
365			`begin`
366			NextState_slvCntrl <= `IN_RESP_GET_RESP;
367			`next_getPacketREn <= 1'b1;`
368			`end`
369	5	sfielding	`end`
370			`START_S1:
371			`begin`
372			NextState_slvCntrl <= `WAIT_RX1;
373			`end`
374			`GET_TOKEN_WAIT_CRC:
375			`begin`
376			`if (RxDataWEn == 1'b1 &&`
377			RxStatus == `RX_PACKET_STREAM)
378			`begin`
379			NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
380			`next_endpCRCTemp <= RxByte;`
381			`end`
382			`else if (RxDataWEn == 1'b1 &&`
383			RxStatus != `RX_PACKET_STREAM)
384			`begin`
385			NextState_slvCntrl <= `WAIT_RX1;
386			`end`
387			`end`
388			`GET_TOKEN_WAIT_ADDR:
389			`begin`
390			`if (RxDataWEn == 1'b1 &&`
391			RxStatus == `RX_PACKET_STREAM)
392			`begin`
393			NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
394			`next_addrEndPTemp <= RxByte;`
395			`end`
396			`else if (RxDataWEn == 1'b1 &&`
397			RxStatus != `RX_PACKET_STREAM)
398			`begin`
399			NextState_slvCntrl <= `WAIT_RX1;
400			`end`
401			`end`
402			`GET_TOKEN_WAIT_STOP:
403			`begin`
404			if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
405			RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
406			RxByte [`RX_OVERFLOW_BIT] == 1'b0))
407			`begin`
408			NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
409			`end`
410			`else if (RxDataWEn == 1'b1)`
411			`begin`
412			NextState_slvCntrl <= `WAIT_RX1;
413			`end`
414			`end`
415			`GET_TOKEN_CHK_SOF:
416			`begin`
417			if (PIDByte[3:0] == `SOF)
418			`begin`
419			NextState_slvCntrl <= `WAIT_RX1;
420			`next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};`
421			`next_SOFRxed <= 1'b1;`
422			`end`
423			`else`
424			`begin`
425			NextState_slvCntrl <= `GET_TOKEN_DELAY;
426			`next_USBAddress <= addrEndPTemp[6:0];`
427			`next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};`
428			`end`
429			`end`
430			`GET_TOKEN_DELAY: // Insert delay to allow USBEndPControlReg to update
431			`begin`
432			NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
433			`end`
434			`GET_TOKEN_CHK_ADDR:
435			`begin`
436			if (USBEndP < `NUM_OF_ENDPOINTS &&
437			`USBAddress == USBTgtAddress &&`
438			`SCGlobalEn == 1'b1 &&`
439			USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
440			`begin`
441			NextState_slvCntrl <= `CHK_PID;
442			`end`
443			`else`
444			`begin`
445			NextState_slvCntrl <= `WAIT_RX1;
446			`end`
447			`end`
448			`endcase`
449			`end`
450
451			`// Current State Logic (sequential)`
452			`always @ (posedge clk)`
453			`begin`
454			`if (rst)`
455			CurrState_slvCntrl <= `START_S1;
456			`else`
457			`CurrState_slvCntrl <= NextState_slvCntrl;`
458			`end`
459
460			`// Registered outputs logic`
461			`always @ (posedge clk)`
462			`begin`
463			`if (rst)`
464			`begin`
465			`stallSent <= 1'b0;`
466			`NAKSent <= 1'b0;`
467			`SOFRxed <= 1'b0;`
468			`transDone <= 1'b0;`
469			`clrEPRdy <= 1'b0;`
470			`endPMuxErrorsWEn <= 1'b0;`
471			`frameNum <= 11'b00000000000;`
472			`USBEndP <= 4'h0;`
473			`USBEndPTransTypeReg <= 2'b00;`
474			`USBEndPNakTransTypeReg <= 2'b00;`
475			`sendPacketWEn <= 1'b0;`
476			`sendPacketPID <= 4'b0;`
477			`getPacketREn <= 1'b0;`
478			`PIDByte <= 8'h00;`
479			`endpCRCTemp <= 8'h00;`
480			`addrEndPTemp <= 8'h00;`
481			`tempUSBEndPTransTypeReg <= 2'b00;`
482			`USBAddress <= 7'b0000000;`
483			`end`
484			`else`
485			`begin`
486			`stallSent <= next_stallSent;`
487			`NAKSent <= next_NAKSent;`
488			`SOFRxed <= next_SOFRxed;`
489			`transDone <= next_transDone;`
490			`clrEPRdy <= next_clrEPRdy;`
491			`endPMuxErrorsWEn <= next_endPMuxErrorsWEn;`
492			`frameNum <= next_frameNum;`
493			`USBEndP <= next_USBEndP;`
494			`USBEndPTransTypeReg <= next_USBEndPTransTypeReg;`
495			`USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;`
496			`sendPacketWEn <= next_sendPacketWEn;`
497			`sendPacketPID <= next_sendPacketPID;`
498			`getPacketREn <= next_getPacketREn;`
499			`PIDByte <= next_PIDByte;`
500			`endpCRCTemp <= next_endpCRCTemp;`

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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slavecontroller.v] - Blame information for rev 14