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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slavecontroller.v] - Blame information for rev 18

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbSlaveControl_h.v"
`include "usbConstants_h.v"
 
 
module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
input   bitStuffError;
input   clk;
input   CRCError;
input   getPacketRdy;
input   rst;
input   [7:0]RxByte;
input   RxDataWEn;
input   RxOverflow;
input   [7:0]RxStatus;
input   RxTimeOut;
input   SCGlobalEn;
input   sendPacketRdy;
input   [4:0]USBEndPControlReg;
input   [6:0]USBTgtAddress;
output  clrEPRdy;
output  endPMuxErrorsWEn;
output  endPointReadyToGetPkt;
output  [10:0]frameNum;
output  getPacketREn;
output  NAKSent;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
output  SOFRxed;
output  stallSent;
output  transDone;
output  [3:0]USBEndP;
output  [1:0]USBEndPNakTransTypeReg;
output  [1:0]USBEndPTransTypeReg;
 
wire    bitStuffError;
wire    clk;
reg     clrEPRdy, next_clrEPRdy;
wire    CRCError;
reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
reg     endPointReadyToGetPkt, next_endPointReadyToGetPkt;
reg     [10:0]frameNum, next_frameNum;
wire    getPacketRdy;
reg     getPacketREn, next_getPacketREn;
reg     NAKSent, next_NAKSent;
wire    rst;
wire    [7:0]RxByte;
wire    RxDataWEn;
wire    RxOverflow;
wire    [7:0]RxStatus;
wire    RxTimeOut;
wire    SCGlobalEn;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     SOFRxed, next_SOFRxed;
reg     stallSent, next_stallSent;
reg     transDone, next_transDone;
reg     [3:0]USBEndP, next_USBEndP;
wire    [4:0]USBEndPControlReg;
reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
wire    [6:0]USBTgtAddress;
 
// diagram signals declarations
reg  [7:0]addrEndPTemp, next_addrEndPTemp;
reg  [7:0]endpCRCTemp, next_endpCRCTemp;
reg  [7:0]PIDByte, next_PIDByte;
reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
reg  [6:0]USBAddress, next_USBAddress;
reg  [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
 
// BINARY ENCODED state machine: slvCntrl
// State codes definitions:
`define WAIT_RX1 5'b00000
`define FIN_SC 5'b00001
`define GET_TOKEN_WAIT_CRC 5'b00010
`define GET_TOKEN_WAIT_ADDR 5'b00011
`define GET_TOKEN_WAIT_STOP 5'b00100
`define CHK_PID 5'b00101
`define GET_TOKEN_CHK_SOF 5'b00110
`define PID_ERROR 5'b00111
`define CHK_RDY 5'b01000
`define IN_NAK_STALL 5'b01001
`define IN_CHK_RDY 5'b01010
`define SETUP_OUT_CHK 5'b01011
`define SETUP_OUT_SEND 5'b01100
`define SETUP_OUT_GET_PKT 5'b01101
`define START_S1 5'b01110
`define GET_TOKEN_DELAY 5'b01111
`define GET_TOKEN_CHK_ADDR 5'b10000
`define IN_RESP_GET_RESP 5'b10001
`define IN_RESP_DATA 5'b10010
`define IN_RESP_CHK_ISO 5'b10011
 
reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
 
 
// Machine: slvCntrl
 
// NextState logic (combinatorial)
always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlRegCopy or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or USBEndPControlReg or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or endPointReadyToGetPkt or CurrState_slvCntrl)
begin
  NextState_slvCntrl <= CurrState_slvCntrl;
  // Set default values for outputs and signals
  next_stallSent <= stallSent;
  next_NAKSent <= NAKSent;
  next_SOFRxed <= SOFRxed;
  next_PIDByte <= PIDByte;
  next_transDone <= transDone;
  next_clrEPRdy <= clrEPRdy;
  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
  next_endpCRCTemp <= endpCRCTemp;
  next_addrEndPTemp <= addrEndPTemp;
  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
  next_frameNum <= frameNum;
  next_USBAddress <= USBAddress;
  next_USBEndP <= USBEndP;
  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketPID <= sendPacketPID;
  next_getPacketREn <= getPacketREn;
  next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
  next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
    `WAIT_RX1:
    begin
      next_stallSent <= 1'b0;
      next_NAKSent <= 1'b0;
      next_SOFRxed <= 1'b0;
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_START &&
        RxByte[1:0] == `TOKEN)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
        next_PIDByte <= RxByte;
      end
    end
    `FIN_SC:
    begin
      next_transDone <= 1'b0;
      next_clrEPRdy <= 1'b0;
      next_endPMuxErrorsWEn <= 1'b0;
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_PID:
    begin
      if (PIDByte[3:0] == `SETUP)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if (PIDByte[3:0] == `OUT)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `IN_CHK_RDY;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
      end
      else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
      else if (PIDByte[3:0] == `IN)
      begin
        NextState_slvCntrl <= `CHK_RDY;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
      end
      else
      begin
        NextState_slvCntrl <= `PID_ERROR;
      end
    end
    `PID_ERROR:
    begin
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_RDY:
    begin
      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_transDone <= 1'b1;
        next_clrEPRdy <= 1'b1;
        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else if (NAKSent == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `FIN_SC;
      end
    end
    `SETUP_OUT_CHK:
    begin
      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    end
    `SETUP_OUT_SEND:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `SETUP_OUT_GET_PKT:
    begin
      next_getPacketREn <= 1'b0;
      if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
      else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
        bitStuffError == 1'b0 &&
        RxOverflow == 1'b0 &&
        RxTimeOut == 1'b0))
      begin
        NextState_slvCntrl <= `SETUP_OUT_CHK;
      end
      else if (getPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_NAK_STALL:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_CHK_RDY:
    begin
      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
      else
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    end
    `IN_RESP_GET_RESP:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_RESP_DATA:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `IN_RESP_CHK_ISO;
      end
    end
    `IN_RESP_CHK_ISO:
    begin
      if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
      else
      begin
        NextState_slvCntrl <= `IN_RESP_GET_RESP;
        next_getPacketREn <= 1'b1;
      end
    end
    `START_S1:
    begin
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `GET_TOKEN_WAIT_CRC:
    begin
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
        next_endpCRCTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_WAIT_ADDR:
    begin
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
        next_addrEndPTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_WAIT_STOP:
    begin
      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
      end
      else if (RxDataWEn == 1'b1)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_CHK_SOF:
    begin
      if (PIDByte[3:0] == `SOF)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
        next_SOFRxed <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `GET_TOKEN_DELAY;
        next_USBAddress <= addrEndPTemp[6:0];
        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
      end
    end
    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndP etc to update
    begin
      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
    end
    `GET_TOKEN_CHK_ADDR:
    begin
      if (USBEndP < `NUM_OF_ENDPOINTS  &&
        USBAddress == USBTgtAddress &&
        SCGlobalEn == 1'b1 &&
        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_PID;
        next_USBEndPControlRegCopy <= USBEndPControlReg;
        next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
      end
      else
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvCntrl <= `START_S1;
  else
    CurrState_slvCntrl <= NextState_slvCntrl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    stallSent <= 1'b0;
    NAKSent <= 1'b0;
    SOFRxed <= 1'b0;
    transDone <= 1'b0;
    clrEPRdy <= 1'b0;
    endPMuxErrorsWEn <= 1'b0;
    frameNum <= 11'b00000000000;
    USBEndP <= 4'h0;
    USBEndPTransTypeReg <= 2'b00;
    USBEndPNakTransTypeReg <= 2'b00;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
    getPacketREn <= 1'b0;
    endPointReadyToGetPkt <= 1'b0;
    PIDByte <= 8'h00;
    endpCRCTemp <= 8'h00;
    addrEndPTemp <= 8'h00;
    tempUSBEndPTransTypeReg <= 2'b00;
    USBAddress <= 7'b0000000;
    USBEndPControlRegCopy <= 5'b00000;
  end
  else
  begin
    stallSent <= next_stallSent;
    NAKSent <= next_NAKSent;
    SOFRxed <= next_SOFRxed;
    transDone <= next_transDone;
    clrEPRdy <= next_clrEPRdy;
    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
    frameNum <= next_frameNum;
    USBEndP <= next_USBEndP;
    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
    getPacketREn <= next_getPacketREn;
    endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
    PIDByte <= next_PIDByte;
    endpCRCTemp <= next_endpCRCTemp;
    addrEndPTemp <= next_addrEndPTemp;
    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
    USBAddress <= next_USBAddress;
    USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveController`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbSlaveControl_h.v"
48			`include "usbConstants_h.v"
49
50
51	18	sfielding	`module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);`
52	5	sfielding	`input bitStuffError;`
53			`input clk;`
54			`input CRCError;`
55			`input getPacketRdy;`
56			`input rst;`
57			`input [7:0]RxByte;`
58			`input RxDataWEn;`
59			`input RxOverflow;`
60			`input [7:0]RxStatus;`
61			`input RxTimeOut;`
62			`input SCGlobalEn;`
63			`input sendPacketRdy;`
64	14	sfielding	`input [4:0]USBEndPControlReg;`
65	5	sfielding	`input [6:0]USBTgtAddress;`
66			`output clrEPRdy;`
67			`output endPMuxErrorsWEn;`
68	18	sfielding	`output endPointReadyToGetPkt;`
69	5	sfielding	`output [10:0]frameNum;`
70			`output getPacketREn;`
71			`output NAKSent;`
72			`output [3:0]sendPacketPID;`
73			`output sendPacketWEn;`
74			`output SOFRxed;`
75			`output stallSent;`
76			`output transDone;`
77			`output [3:0]USBEndP;`
78			`output [1:0]USBEndPNakTransTypeReg;`
79			`output [1:0]USBEndPTransTypeReg;`
80
81			`wire bitStuffError;`
82			`wire clk;`
83			`reg clrEPRdy, next_clrEPRdy;`
84			`wire CRCError;`
85			`reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;`
86	18	sfielding	`reg endPointReadyToGetPkt, next_endPointReadyToGetPkt;`
87	5	sfielding	`reg [10:0]frameNum, next_frameNum;`
88			`wire getPacketRdy;`
89			`reg getPacketREn, next_getPacketREn;`
90			`reg NAKSent, next_NAKSent;`
91			`wire rst;`
92			`wire [7:0]RxByte;`
93			`wire RxDataWEn;`
94			`wire RxOverflow;`
95			`wire [7:0]RxStatus;`
96			`wire RxTimeOut;`
97			`wire SCGlobalEn;`
98			`reg [3:0]sendPacketPID, next_sendPacketPID;`
99			`wire sendPacketRdy;`
100			`reg sendPacketWEn, next_sendPacketWEn;`
101			`reg SOFRxed, next_SOFRxed;`
102			`reg stallSent, next_stallSent;`
103			`reg transDone, next_transDone;`
104			`reg [3:0]USBEndP, next_USBEndP;`
105	14	sfielding	`wire [4:0]USBEndPControlReg;`
106	5	sfielding	`reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;`
107			`reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;`
108			`wire [6:0]USBTgtAddress;`
109
110			`// diagram signals declarations`
111			`reg [7:0]addrEndPTemp, next_addrEndPTemp;`
112			`reg [7:0]endpCRCTemp, next_endpCRCTemp;`
113			`reg [7:0]PIDByte, next_PIDByte;`
114			`reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;`
115			`reg [6:0]USBAddress, next_USBAddress;`
116	18	sfielding	`reg [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;`
117	5	sfielding
118			`// BINARY ENCODED state machine: slvCntrl`
119			`// State codes definitions:`
120			`define WAIT_RX1 5'b00000
121			`define FIN_SC 5'b00001
122			`define GET_TOKEN_WAIT_CRC 5'b00010
123			`define GET_TOKEN_WAIT_ADDR 5'b00011
124			`define GET_TOKEN_WAIT_STOP 5'b00100
125			`define CHK_PID 5'b00101
126			`define GET_TOKEN_CHK_SOF 5'b00110
127			`define PID_ERROR 5'b00111
128			`define CHK_RDY 5'b01000
129			`define IN_NAK_STALL 5'b01001
130			`define IN_CHK_RDY 5'b01010
131	14	sfielding	`define SETUP_OUT_CHK 5'b01011
132			`define SETUP_OUT_SEND 5'b01100
133			`define SETUP_OUT_GET_PKT 5'b01101
134			`define START_S1 5'b01110
135			`define GET_TOKEN_DELAY 5'b01111
136			`define GET_TOKEN_CHK_ADDR 5'b10000
137			`define IN_RESP_GET_RESP 5'b10001
138			`define IN_RESP_DATA 5'b10010
139			`define IN_RESP_CHK_ISO 5'b10011
140	5	sfielding
141			`reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;`
142
143
144			`// Machine: slvCntrl`
145
146			`// NextState logic (combinatorial)`
147	18	sfielding	always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlRegCopy or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or USBEndPControlReg or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or endPointReadyToGetPkt or CurrState_slvCntrl)
148	5	sfielding	`begin`
149			`NextState_slvCntrl <= CurrState_slvCntrl;`
150			`// Set default values for outputs and signals`
151			`next_stallSent <= stallSent;`
152			`next_NAKSent <= NAKSent;`
153			`next_SOFRxed <= SOFRxed;`
154			`next_PIDByte <= PIDByte;`
155			`next_transDone <= transDone;`
156			`next_clrEPRdy <= clrEPRdy;`
157			`next_endPMuxErrorsWEn <= endPMuxErrorsWEn;`
158			`next_endpCRCTemp <= endpCRCTemp;`
159			`next_addrEndPTemp <= addrEndPTemp;`
160			`next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
161			`next_frameNum <= frameNum;`
162			`next_USBAddress <= USBAddress;`
163			`next_USBEndP <= USBEndP;`
164			`next_USBEndPTransTypeReg <= USBEndPTransTypeReg;`
165			`next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;`
166			`next_sendPacketWEn <= sendPacketWEn;`
167			`next_sendPacketPID <= sendPacketPID;`
168			`next_getPacketREn <= getPacketREn;`
169	18	sfielding	`next_USBEndPControlRegCopy <= USBEndPControlRegCopy;`
170			`next_endPointReadyToGetPkt <= endPointReadyToGetPkt;`
171	5	sfielding	`case (CurrState_slvCntrl) // synopsys parallel_case full_case`
172			`WAIT_RX1:
173			`begin`
174			`next_stallSent <= 1'b0;`
175			`next_NAKSent <= 1'b0;`
176			`next_SOFRxed <= 1'b0;`
177			`if (RxDataWEn == 1'b1 &&`
178			RxStatus == `RX_PACKET_START &&
179			RxByte[1:0] == `TOKEN)
180			`begin`
181			NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
182			`next_PIDByte <= RxByte;`
183			`end`
184			`end`
185			`FIN_SC:
186			`begin`
187			`next_transDone <= 1'b0;`
188			`next_clrEPRdy <= 1'b0;`
189			`next_endPMuxErrorsWEn <= 1'b0;`
190			NextState_slvCntrl <= `WAIT_RX1;
191			`end`
192			`CHK_PID:
193			`begin`
194			if (PIDByte[3:0] == `SETUP)
195			`begin`
196			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
197			next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
198			`next_getPacketREn <= 1'b1;`
199			`end`
200			else if (PIDByte[3:0] == `OUT)
201			`begin`
202			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
203			next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
204			`next_getPacketREn <= 1'b1;`
205			`end`
206	18	sfielding	else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
207	5	sfielding	`begin`
208			NextState_slvCntrl <= `IN_CHK_RDY;
209			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
210			`end`
211	18	sfielding	else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
212	14	sfielding	`begin`
213			NextState_slvCntrl <= `IN_RESP_DATA;
214			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
215			`next_sendPacketWEn <= 1'b1;`
216			next_sendPacketPID <= `DATA0;
217			`end`
218	18	sfielding	else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
219	14	sfielding	`begin`
220			NextState_slvCntrl <= `IN_RESP_DATA;
221			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
222			`next_sendPacketWEn <= 1'b1;`
223			next_sendPacketPID <= `DATA1;
224			`end`
225			else if (PIDByte[3:0] == `IN)
226			`begin`
227			NextState_slvCntrl <= `CHK_RDY;
228			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
229			`end`
230	5	sfielding	`else`
231			`begin`
232			NextState_slvCntrl <= `PID_ERROR;
233			`end`
234			`end`
235			`PID_ERROR:
236			`begin`
237			NextState_slvCntrl <= `WAIT_RX1;
238			`end`
239			`CHK_RDY:
240			`begin`
241	18	sfielding	if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
242	5	sfielding	`begin`
243			NextState_slvCntrl <= `FIN_SC;
244			`next_transDone <= 1'b1;`
245			`next_clrEPRdy <= 1'b1;`
246			`next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
247			`next_endPMuxErrorsWEn <= 1'b1;`
248			`end`
249			`else if (NAKSent == 1'b1)`
250			`begin`
251			NextState_slvCntrl <= `FIN_SC;
252			`next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;`
253			`next_endPMuxErrorsWEn <= 1'b1;`
254			`end`
255			`else`
256			`begin`
257			NextState_slvCntrl <= `FIN_SC;
258			`end`
259			`end`
260			`SETUP_OUT_CHK:
261			`begin`
262	18	sfielding	if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
263	5	sfielding	`begin`
264			NextState_slvCntrl <= `SETUP_OUT_SEND;
265			`next_sendPacketWEn <= 1'b1;`
266			next_sendPacketPID <= `NAK;
267			`next_NAKSent <= 1'b1;`
268			`end`
269	18	sfielding	else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
270	5	sfielding	`begin`
271			NextState_slvCntrl <= `SETUP_OUT_SEND;
272			`next_sendPacketWEn <= 1'b1;`
273			next_sendPacketPID <= `STALL;
274			`next_stallSent <= 1'b1;`
275			`end`
276			`else`
277			`begin`
278			NextState_slvCntrl <= `SETUP_OUT_SEND;
279			`next_sendPacketWEn <= 1'b1;`
280			next_sendPacketPID <= `ACK;
281			`end`
282			`end`
283			`SETUP_OUT_SEND:
284			`begin`
285			`next_sendPacketWEn <= 1'b0;`
286			`if (sendPacketRdy == 1'b1)`
287			`begin`
288			NextState_slvCntrl <= `CHK_RDY;
289			`end`
290			`end`
291			`SETUP_OUT_GET_PKT:
292			`begin`
293			`next_getPacketREn <= 1'b0;`
294	18	sfielding	if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
295	14	sfielding	`begin`
296			NextState_slvCntrl <= `CHK_RDY;
297			`end`
298			`else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&`
299	5	sfielding	`bitStuffError == 1'b0 &&`
300			`RxOverflow == 1'b0 &&`
301			`RxTimeOut == 1'b0))`
302			`begin`
303			NextState_slvCntrl <= `SETUP_OUT_CHK;
304			`end`
305			`else if (getPacketRdy == 1'b1)`
306			`begin`
307			NextState_slvCntrl <= `CHK_RDY;
308			`end`
309			`end`
310			`IN_NAK_STALL:
311			`begin`
312			`next_sendPacketWEn <= 1'b0;`
313			`if (sendPacketRdy == 1'b1)`
314			`begin`
315			NextState_slvCntrl <= `CHK_RDY;
316			`end`
317			`end`
318			`IN_CHK_RDY:
319			`begin`
320	18	sfielding	if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
321	5	sfielding	`begin`
322			NextState_slvCntrl <= `IN_NAK_STALL;
323			`next_sendPacketWEn <= 1'b1;`
324			next_sendPacketPID <= `NAK;
325			`next_NAKSent <= 1'b1;`
326			`end`
327	18	sfielding	else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
328	5	sfielding	`begin`
329			NextState_slvCntrl <= `IN_NAK_STALL;
330			`next_sendPacketWEn <= 1'b1;`
331			next_sendPacketPID <= `STALL;
332			`next_stallSent <= 1'b1;`
333			`end`
334	18	sfielding	else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
335	5	sfielding	`begin`
336	14	sfielding	NextState_slvCntrl <= `IN_RESP_DATA;
337	5	sfielding	`next_sendPacketWEn <= 1'b1;`
338			next_sendPacketPID <= `DATA0;
339			`end`
340			`else`
341			`begin`
342	14	sfielding	NextState_slvCntrl <= `IN_RESP_DATA;
343	5	sfielding	`next_sendPacketWEn <= 1'b1;`
344			next_sendPacketPID <= `DATA1;
345			`end`
346			`end`
347	14	sfielding	`IN_RESP_GET_RESP:
348	5	sfielding	`begin`
349	14	sfielding	`next_getPacketREn <= 1'b0;`
350			`if (getPacketRdy == 1'b1)`
351			`begin`
352			NextState_slvCntrl <= `CHK_RDY;
353			`end`
354			`end`
355			`IN_RESP_DATA:
356			`begin`
357	5	sfielding	`next_sendPacketWEn <= 1'b0;`
358			`if (sendPacketRdy == 1'b1)`
359			`begin`
360	14	sfielding	NextState_slvCntrl <= `IN_RESP_CHK_ISO;
361	5	sfielding	`end`
362			`end`
363	14	sfielding	`IN_RESP_CHK_ISO:
364	5	sfielding	`begin`
365	18	sfielding	if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
366	5	sfielding	`begin`
367			NextState_slvCntrl <= `CHK_RDY;
368			`end`
369	14	sfielding	`else`
370			`begin`
371			NextState_slvCntrl <= `IN_RESP_GET_RESP;
372			`next_getPacketREn <= 1'b1;`
373			`end`
374	5	sfielding	`end`
375			`START_S1:
376			`begin`
377			NextState_slvCntrl <= `WAIT_RX1;
378			`end`
379			`GET_TOKEN_WAIT_CRC:
380			`begin`
381			`if (RxDataWEn == 1'b1 &&`
382			RxStatus == `RX_PACKET_STREAM)
383			`begin`
384			NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
385			`next_endpCRCTemp <= RxByte;`
386			`end`
387			`else if (RxDataWEn == 1'b1 &&`
388			RxStatus != `RX_PACKET_STREAM)
389			`begin`
390			NextState_slvCntrl <= `WAIT_RX1;
391			`end`
392			`end`
393			`GET_TOKEN_WAIT_ADDR:
394			`begin`
395			`if (RxDataWEn == 1'b1 &&`
396			RxStatus == `RX_PACKET_STREAM)
397			`begin`
398			NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
399			`next_addrEndPTemp <= RxByte;`
400			`end`
401			`else if (RxDataWEn == 1'b1 &&`
402			RxStatus != `RX_PACKET_STREAM)
403			`begin`
404			NextState_slvCntrl <= `WAIT_RX1;
405			`end`
406			`end`
407			`GET_TOKEN_WAIT_STOP:
408			`begin`
409			if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
410			RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
411			RxByte [`RX_OVERFLOW_BIT] == 1'b0))
412			`begin`
413			NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
414			`end`
415			`else if (RxDataWEn == 1'b1)`
416			`begin`
417			NextState_slvCntrl <= `WAIT_RX1;
418			`end`
419			`end`
420			`GET_TOKEN_CHK_SOF:
421			`begin`
422			if (PIDByte[3:0] == `SOF)
423			`begin`
424			NextState_slvCntrl <= `WAIT_RX1;
425			`next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};`
426			`next_SOFRxed <= 1'b1;`
427			`end`
428			`else`
429			`begin`
430			NextState_slvCntrl <= `GET_TOKEN_DELAY;
431			`next_USBAddress <= addrEndPTemp[6:0];`
432			`next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};`
433			`end`
434			`end`
435	18	sfielding	`GET_TOKEN_DELAY: // Insert delay to allow USBEndP etc to update
436	5	sfielding	`begin`
437			NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
438			`end`
439			`GET_TOKEN_CHK_ADDR:
440			`begin`
441			if (USBEndP < `NUM_OF_ENDPOINTS &&
442			`USBAddress == USBTgtAddress &&`
443			`SCGlobalEn == 1'b1 &&`
444			USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
445			`begin`
446			NextState_slvCntrl <= `CHK_PID;
447	18	sfielding	`next_USBEndPControlRegCopy <= USBEndPControlReg;`
448			next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
449	5	sfielding	`end`
450			`else`
451			`begin`
452			NextState_slvCntrl <= `WAIT_RX1;
453			`end`
454			`end`
455			`endcase`
456			`end`
457
458			`// Current State Logic (sequential)`
459			`always @ (posedge clk)`
460			`begin`
461			`if (rst)`
462			CurrState_slvCntrl <= `START_S1;
463			`else`
464			`CurrState_slvCntrl <= NextState_slvCntrl;`
465			`end`
466
467			`// Registered outputs logic`
468			`always @ (posedge clk)`
469			`begin`
470			`if (rst)`
471			`begin`
472			`stallSent <= 1'b0;`
473			`NAKSent <= 1'b0;`
474			`SOFRxed <= 1'b0;`
475			`transDone <= 1'b0;`
476			`clrEPRdy <= 1'b0;`
477			`endPMuxErrorsWEn <= 1'b0;`
478			`frameNum <= 11'b00000000000;`
479			`USBEndP <= 4'h0;`
480			`USBEndPTransTypeReg <= 2'b00;`
481			`USBEndPNakTransTypeReg <= 2'b00;`
482			`sendPacketWEn <= 1'b0;`
483			`sendPacketPID <= 4'b0;`
484			`getPacketREn <= 1'b0;`
485	18	sfielding	`endPointReadyToGetPkt <= 1'b0;`
486	5	sfielding	`PIDByte <= 8'h00;`
487			`endpCRCTemp <= 8'h00;`
488			`addrEndPTemp <= 8'h00;`
489			`tempUSBEndPTransTypeReg <= 2'b00;`
490			`USBAddress <= 7'b0000000;`
491	18	sfielding	`USBEndPControlRegCopy <= 5'b00000;`
492	5	sfielding	`end`
493			`else`
494			`begin`
495			`stallSent <= next_stallSent;`
496			`NAKSent <= next_NAKSent;`
497			`SOFRxed <= next_SOFRxed;`
498			`transDone <= next_transDone;`
499			`clrEPRdy <= next_clrEPRdy;`
500			`endPMuxErrorsWEn <= next_endPMuxErrorsWEn;`

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