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[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slavecontroller.v] - Blame information for rev 9

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbSlaveControl_h.v"
`include "usbConstants_h.v"
 
 
module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
input   bitStuffError;
input   clk;
input   CRCError;
input   getPacketRdy;
input   rst;
input   [7:0]RxByte;
input   RxDataWEn;
input   RxOverflow;
input   [7:0]RxStatus;
input   RxTimeOut;
input   SCGlobalEn;
input   sendPacketRdy;
input   [3:0]USBEndPControlReg;
input   [6:0]USBTgtAddress;
output  clrEPRdy;
output  endPMuxErrorsWEn;
output  [10:0]frameNum;
output  getPacketREn;
output  NAKSent;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
output  SOFRxed;
output  stallSent;
output  transDone;
output  [3:0]USBEndP;
output  [1:0]USBEndPNakTransTypeReg;
output  [1:0]USBEndPTransTypeReg;
 
wire    bitStuffError;
wire    clk;
reg     clrEPRdy, next_clrEPRdy;
wire    CRCError;
reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
reg     [10:0]frameNum, next_frameNum;
wire    getPacketRdy;
reg     getPacketREn, next_getPacketREn;
reg     NAKSent, next_NAKSent;
wire    rst;
wire    [7:0]RxByte;
wire    RxDataWEn;
wire    RxOverflow;
wire    [7:0]RxStatus;
wire    RxTimeOut;
wire    SCGlobalEn;
reg     [3:0]sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     SOFRxed, next_SOFRxed;
reg     stallSent, next_stallSent;
reg     transDone, next_transDone;
reg     [3:0]USBEndP, next_USBEndP;
wire    [3:0]USBEndPControlReg;
reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
wire    [6:0]USBTgtAddress;
 
// diagram signals declarations
reg  [7:0]addrEndPTemp, next_addrEndPTemp;
reg  [7:0]endpCRCTemp, next_endpCRCTemp;
reg  [7:0]PIDByte, next_PIDByte;
reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
reg  [6:0]USBAddress, next_USBAddress;
 
// BINARY ENCODED state machine: slvCntrl
// State codes definitions:
`define WAIT_RX1 5'b00000
`define FIN_SC 5'b00001
`define GET_TOKEN_WAIT_CRC 5'b00010
`define GET_TOKEN_WAIT_ADDR 5'b00011
`define GET_TOKEN_WAIT_STOP 5'b00100
`define CHK_PID 5'b00101
`define GET_TOKEN_CHK_SOF 5'b00110
`define PID_ERROR 5'b00111
`define CHK_RDY 5'b01000
`define IN_NAK_STALL 5'b01001
`define IN_CHK_RDY 5'b01010
`define IN_DATA 5'b01011
`define IN_GET_RESP 5'b01100
`define SETUP_OUT_CHK 5'b01101
`define SETUP_OUT_SEND 5'b01110
`define SETUP_OUT_GET_PKT 5'b01111
`define START_S1 5'b10000
`define GET_TOKEN_DELAY 5'b10001
`define GET_TOKEN_CHK_ADDR 5'b10010
 
reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
 
 
// Machine: slvCntrl
 
// NextState logic (combinatorial)
always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
begin
  NextState_slvCntrl <= CurrState_slvCntrl;
  // Set default values for outputs and signals
  next_stallSent <= stallSent;
  next_NAKSent <= NAKSent;
  next_SOFRxed <= SOFRxed;
  next_PIDByte <= PIDByte;
  next_transDone <= transDone;
  next_clrEPRdy <= clrEPRdy;
  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
  next_endpCRCTemp <= endpCRCTemp;
  next_addrEndPTemp <= addrEndPTemp;
  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
  next_frameNum <= frameNum;
  next_USBAddress <= USBAddress;
  next_USBEndP <= USBEndP;
  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketPID <= sendPacketPID;
  next_getPacketREn <= getPacketREn;
  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
    `WAIT_RX1:
    begin
      next_stallSent <= 1'b0;
      next_NAKSent <= 1'b0;
      next_SOFRxed <= 1'b0;
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_START &&
        RxByte[1:0] == `TOKEN)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
        next_PIDByte <= RxByte;
      end
    end
    `FIN_SC:
    begin
      next_transDone <= 1'b0;
      next_clrEPRdy <= 1'b0;
      next_endPMuxErrorsWEn <= 1'b0;
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_PID:
    begin
      if (PIDByte[3:0] == `SETUP)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if (PIDByte[3:0] == `OUT)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if (PIDByte[3:0] == `IN)
      begin
        NextState_slvCntrl <= `IN_CHK_RDY;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
      end
      else
      begin
        NextState_slvCntrl <= `PID_ERROR;
      end
    end
    `PID_ERROR:
    begin
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_RDY:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_transDone <= 1'b1;
        next_clrEPRdy <= 1'b1;
        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else if (NAKSent == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `FIN_SC;
      end
    end
    `SETUP_OUT_CHK:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    end
    `SETUP_OUT_SEND:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `SETUP_OUT_GET_PKT:
    begin
      next_getPacketREn <= 1'b0;
      if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
        bitStuffError == 1'b0 &&
        RxOverflow == 1'b0 &&
        RxTimeOut == 1'b0))
      begin
        NextState_slvCntrl <= `SETUP_OUT_CHK;
      end
      else if (getPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_NAK_STALL:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `IN_CHK_RDY:
    begin
      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
      else
      begin
        NextState_slvCntrl <= `IN_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    end
    `IN_DATA:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `IN_GET_RESP;
        next_getPacketREn <= 1'b1;
      end
    end
    `IN_GET_RESP:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_RDY;
      end
    end
    `START_S1:
    begin
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `GET_TOKEN_WAIT_CRC:
    begin
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
        next_endpCRCTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_WAIT_ADDR:
    begin
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
        next_addrEndPTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_WAIT_STOP:
    begin
      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
      end
      else if (RxDataWEn == 1'b1)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
    `GET_TOKEN_CHK_SOF:
    begin
      if (PIDByte[3:0] == `SOF)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
        next_SOFRxed <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `GET_TOKEN_DELAY;
        next_USBAddress <= addrEndPTemp[6:0];
        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
      end
    end
    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndPControlReg to update
    begin
      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
    end
    `GET_TOKEN_CHK_ADDR:
    begin
      if (USBEndP < `NUM_OF_ENDPOINTS  &&
        USBAddress == USBTgtAddress &&
        SCGlobalEn == 1'b1 &&
        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_PID;
      end
      else
      begin
        NextState_slvCntrl <= `WAIT_RX1;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst)
    CurrState_slvCntrl <= `START_S1;
  else
    CurrState_slvCntrl <= NextState_slvCntrl;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst)
  begin
    stallSent <= 1'b0;
    NAKSent <= 1'b0;
    SOFRxed <= 1'b0;
    transDone <= 1'b0;
    clrEPRdy <= 1'b0;
    endPMuxErrorsWEn <= 1'b0;
    frameNum <= 11'b00000000000;
    USBEndP <= 4'h0;
    USBEndPTransTypeReg <= 2'b00;
    USBEndPNakTransTypeReg <= 2'b00;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
    getPacketREn <= 1'b0;
    PIDByte <= 8'h00;
    endpCRCTemp <= 8'h00;
    addrEndPTemp <= 8'h00;
    tempUSBEndPTransTypeReg <= 2'b00;
    USBAddress <= 7'b0000000;
  end
  else
  begin
    stallSent <= next_stallSent;
    NAKSent <= next_NAKSent;
    SOFRxed <= next_SOFRxed;
    transDone <= next_transDone;
    clrEPRdy <= next_clrEPRdy;
    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
    frameNum <= next_frameNum;
    USBEndP <= next_USBEndP;
    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
    getPacketREn <= next_getPacketREn;
    PIDByte <= next_PIDByte;
    endpCRCTemp <= next_endpCRCTemp;
    addrEndPTemp <= next_addrEndPTemp;
    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
    USBAddress <= next_USBAddress;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slavecontroller.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	5	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// slaveController`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`timescale 1ns / 1ps
46			`include "usbSerialInterfaceEngine_h.v"
47			`include "usbSlaveControl_h.v"
48			`include "usbConstants_h.v"
49
50
51			`module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);`
52			`input bitStuffError;`
53			`input clk;`
54			`input CRCError;`
55			`input getPacketRdy;`
56			`input rst;`
57			`input [7:0]RxByte;`
58			`input RxDataWEn;`
59			`input RxOverflow;`
60			`input [7:0]RxStatus;`
61			`input RxTimeOut;`
62			`input SCGlobalEn;`
63			`input sendPacketRdy;`
64			`input [3:0]USBEndPControlReg;`
65			`input [6:0]USBTgtAddress;`
66			`output clrEPRdy;`
67			`output endPMuxErrorsWEn;`
68			`output [10:0]frameNum;`
69			`output getPacketREn;`
70			`output NAKSent;`
71			`output [3:0]sendPacketPID;`
72			`output sendPacketWEn;`
73			`output SOFRxed;`
74			`output stallSent;`
75			`output transDone;`
76			`output [3:0]USBEndP;`
77			`output [1:0]USBEndPNakTransTypeReg;`
78			`output [1:0]USBEndPTransTypeReg;`
79
80			`wire bitStuffError;`
81			`wire clk;`
82			`reg clrEPRdy, next_clrEPRdy;`
83			`wire CRCError;`
84			`reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;`
85			`reg [10:0]frameNum, next_frameNum;`
86			`wire getPacketRdy;`
87			`reg getPacketREn, next_getPacketREn;`
88			`reg NAKSent, next_NAKSent;`
89			`wire rst;`
90			`wire [7:0]RxByte;`
91			`wire RxDataWEn;`
92			`wire RxOverflow;`
93			`wire [7:0]RxStatus;`
94			`wire RxTimeOut;`
95			`wire SCGlobalEn;`
96			`reg [3:0]sendPacketPID, next_sendPacketPID;`
97			`wire sendPacketRdy;`
98			`reg sendPacketWEn, next_sendPacketWEn;`
99			`reg SOFRxed, next_SOFRxed;`
100			`reg stallSent, next_stallSent;`
101			`reg transDone, next_transDone;`
102			`reg [3:0]USBEndP, next_USBEndP;`
103			`wire [3:0]USBEndPControlReg;`
104			`reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;`
105			`reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;`
106			`wire [6:0]USBTgtAddress;`
107
108			`// diagram signals declarations`
109			`reg [7:0]addrEndPTemp, next_addrEndPTemp;`
110			`reg [7:0]endpCRCTemp, next_endpCRCTemp;`
111			`reg [7:0]PIDByte, next_PIDByte;`
112			`reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;`
113			`reg [6:0]USBAddress, next_USBAddress;`
114
115			`// BINARY ENCODED state machine: slvCntrl`
116			`// State codes definitions:`
117			`define WAIT_RX1 5'b00000
118			`define FIN_SC 5'b00001
119			`define GET_TOKEN_WAIT_CRC 5'b00010
120			`define GET_TOKEN_WAIT_ADDR 5'b00011
121			`define GET_TOKEN_WAIT_STOP 5'b00100
122			`define CHK_PID 5'b00101
123			`define GET_TOKEN_CHK_SOF 5'b00110
124			`define PID_ERROR 5'b00111
125			`define CHK_RDY 5'b01000
126			`define IN_NAK_STALL 5'b01001
127			`define IN_CHK_RDY 5'b01010
128			`define IN_DATA 5'b01011
129			`define IN_GET_RESP 5'b01100
130			`define SETUP_OUT_CHK 5'b01101
131			`define SETUP_OUT_SEND 5'b01110
132			`define SETUP_OUT_GET_PKT 5'b01111
133			`define START_S1 5'b10000
134			`define GET_TOKEN_DELAY 5'b10001
135			`define GET_TOKEN_CHK_ADDR 5'b10010
136
137			`reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;`
138
139
140			`// Machine: slvCntrl`
141
142			`// NextState logic (combinatorial)`
143			`always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)`
144			`begin`
145			`NextState_slvCntrl <= CurrState_slvCntrl;`
146			`// Set default values for outputs and signals`
147			`next_stallSent <= stallSent;`
148			`next_NAKSent <= NAKSent;`
149			`next_SOFRxed <= SOFRxed;`
150			`next_PIDByte <= PIDByte;`
151			`next_transDone <= transDone;`
152			`next_clrEPRdy <= clrEPRdy;`
153			`next_endPMuxErrorsWEn <= endPMuxErrorsWEn;`
154			`next_endpCRCTemp <= endpCRCTemp;`
155			`next_addrEndPTemp <= addrEndPTemp;`
156			`next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
157			`next_frameNum <= frameNum;`
158			`next_USBAddress <= USBAddress;`
159			`next_USBEndP <= USBEndP;`
160			`next_USBEndPTransTypeReg <= USBEndPTransTypeReg;`
161			`next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;`
162			`next_sendPacketWEn <= sendPacketWEn;`
163			`next_sendPacketPID <= sendPacketPID;`
164			`next_getPacketREn <= getPacketREn;`
165			`case (CurrState_slvCntrl) // synopsys parallel_case full_case`
166			`WAIT_RX1:
167			`begin`
168			`next_stallSent <= 1'b0;`
169			`next_NAKSent <= 1'b0;`
170			`next_SOFRxed <= 1'b0;`
171			`if (RxDataWEn == 1'b1 &&`
172			RxStatus == `RX_PACKET_START &&
173			RxByte[1:0] == `TOKEN)
174			`begin`
175			NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
176			`next_PIDByte <= RxByte;`
177			`end`
178			`end`
179			`FIN_SC:
180			`begin`
181			`next_transDone <= 1'b0;`
182			`next_clrEPRdy <= 1'b0;`
183			`next_endPMuxErrorsWEn <= 1'b0;`
184			NextState_slvCntrl <= `WAIT_RX1;
185			`end`
186			`CHK_PID:
187			`begin`
188			if (PIDByte[3:0] == `SETUP)
189			`begin`
190			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
191			next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
192			`next_getPacketREn <= 1'b1;`
193			`end`
194			else if (PIDByte[3:0] == `OUT)
195			`begin`
196			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
197			next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
198			`next_getPacketREn <= 1'b1;`
199			`end`
200			else if (PIDByte[3:0] == `IN)
201			`begin`
202			NextState_slvCntrl <= `IN_CHK_RDY;
203			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
204			`end`
205			`else`
206			`begin`
207			NextState_slvCntrl <= `PID_ERROR;
208			`end`
209			`end`
210			`PID_ERROR:
211			`begin`
212			NextState_slvCntrl <= `WAIT_RX1;
213			`end`
214			`CHK_RDY:
215			`begin`
216			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
217			`begin`
218			NextState_slvCntrl <= `FIN_SC;
219			`next_transDone <= 1'b1;`
220			`next_clrEPRdy <= 1'b1;`
221			`next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
222			`next_endPMuxErrorsWEn <= 1'b1;`
223			`end`
224			`else if (NAKSent == 1'b1)`
225			`begin`
226			NextState_slvCntrl <= `FIN_SC;
227			`next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;`
228			`next_endPMuxErrorsWEn <= 1'b1;`
229			`end`
230			`else`
231			`begin`
232			NextState_slvCntrl <= `FIN_SC;
233			`end`
234			`end`
235			`SETUP_OUT_CHK:
236			`begin`
237			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
238			`begin`
239			NextState_slvCntrl <= `SETUP_OUT_SEND;
240			`next_sendPacketWEn <= 1'b1;`
241			next_sendPacketPID <= `NAK;
242			`next_NAKSent <= 1'b1;`
243			`end`
244			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
245			`begin`
246			NextState_slvCntrl <= `SETUP_OUT_SEND;
247			`next_sendPacketWEn <= 1'b1;`
248			next_sendPacketPID <= `STALL;
249			`next_stallSent <= 1'b1;`
250			`end`
251			`else`
252			`begin`
253			NextState_slvCntrl <= `SETUP_OUT_SEND;
254			`next_sendPacketWEn <= 1'b1;`
255			next_sendPacketPID <= `ACK;
256			`end`
257			`end`
258			`SETUP_OUT_SEND:
259			`begin`
260			`next_sendPacketWEn <= 1'b0;`
261			`if (sendPacketRdy == 1'b1)`
262			`begin`
263			NextState_slvCntrl <= `CHK_RDY;
264			`end`
265			`end`
266			`SETUP_OUT_GET_PKT:
267			`begin`
268			`next_getPacketREn <= 1'b0;`
269			`if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&`
270			`bitStuffError == 1'b0 &&`
271			`RxOverflow == 1'b0 &&`
272			`RxTimeOut == 1'b0))`
273			`begin`
274			NextState_slvCntrl <= `SETUP_OUT_CHK;
275			`end`
276			`else if (getPacketRdy == 1'b1)`
277			`begin`
278			NextState_slvCntrl <= `CHK_RDY;
279			`end`
280			`end`
281			`IN_NAK_STALL:
282			`begin`
283			`next_sendPacketWEn <= 1'b0;`
284			`if (sendPacketRdy == 1'b1)`
285			`begin`
286			NextState_slvCntrl <= `CHK_RDY;
287			`end`
288			`end`
289			`IN_CHK_RDY:
290			`begin`
291			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
292			`begin`
293			NextState_slvCntrl <= `IN_NAK_STALL;
294			`next_sendPacketWEn <= 1'b1;`
295			next_sendPacketPID <= `NAK;
296			`next_NAKSent <= 1'b1;`
297			`end`
298			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
299			`begin`
300			NextState_slvCntrl <= `IN_NAK_STALL;
301			`next_sendPacketWEn <= 1'b1;`
302			next_sendPacketPID <= `STALL;
303			`next_stallSent <= 1'b1;`
304			`end`
305			else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
306			`begin`
307			NextState_slvCntrl <= `IN_DATA;
308			`next_sendPacketWEn <= 1'b1;`
309			next_sendPacketPID <= `DATA0;
310			`end`
311			`else`
312			`begin`
313			NextState_slvCntrl <= `IN_DATA;
314			`next_sendPacketWEn <= 1'b1;`
315			next_sendPacketPID <= `DATA1;
316			`end`
317			`end`
318			`IN_DATA:
319			`begin`
320			`next_sendPacketWEn <= 1'b0;`
321			`if (sendPacketRdy == 1'b1)`
322			`begin`
323			NextState_slvCntrl <= `IN_GET_RESP;
324			`next_getPacketREn <= 1'b1;`
325			`end`
326			`end`
327			`IN_GET_RESP:
328			`begin`
329			`next_getPacketREn <= 1'b0;`
330			`if (getPacketRdy == 1'b1)`
331			`begin`
332			NextState_slvCntrl <= `CHK_RDY;
333			`end`
334			`end`
335			`START_S1:
336			`begin`
337			NextState_slvCntrl <= `WAIT_RX1;
338			`end`
339			`GET_TOKEN_WAIT_CRC:
340			`begin`
341			`if (RxDataWEn == 1'b1 &&`
342			RxStatus == `RX_PACKET_STREAM)
343			`begin`
344			NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
345			`next_endpCRCTemp <= RxByte;`
346			`end`
347			`else if (RxDataWEn == 1'b1 &&`
348			RxStatus != `RX_PACKET_STREAM)
349			`begin`
350			NextState_slvCntrl <= `WAIT_RX1;
351			`end`
352			`end`
353			`GET_TOKEN_WAIT_ADDR:
354			`begin`
355			`if (RxDataWEn == 1'b1 &&`
356			RxStatus == `RX_PACKET_STREAM)
357			`begin`
358			NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
359			`next_addrEndPTemp <= RxByte;`
360			`end`
361			`else if (RxDataWEn == 1'b1 &&`
362			RxStatus != `RX_PACKET_STREAM)
363			`begin`
364			NextState_slvCntrl <= `WAIT_RX1;
365			`end`
366			`end`
367			`GET_TOKEN_WAIT_STOP:
368			`begin`
369			if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
370			RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
371			RxByte [`RX_OVERFLOW_BIT] == 1'b0))
372			`begin`
373			NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
374			`end`
375			`else if (RxDataWEn == 1'b1)`
376			`begin`
377			NextState_slvCntrl <= `WAIT_RX1;
378			`end`
379			`end`
380			`GET_TOKEN_CHK_SOF:
381			`begin`
382			if (PIDByte[3:0] == `SOF)
383			`begin`
384			NextState_slvCntrl <= `WAIT_RX1;
385			`next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};`
386			`next_SOFRxed <= 1'b1;`
387			`end`
388			`else`
389			`begin`
390			NextState_slvCntrl <= `GET_TOKEN_DELAY;
391			`next_USBAddress <= addrEndPTemp[6:0];`
392			`next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};`
393			`end`
394			`end`
395			`GET_TOKEN_DELAY: // Insert delay to allow USBEndPControlReg to update
396			`begin`
397			NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
398			`end`
399			`GET_TOKEN_CHK_ADDR:
400			`begin`
401			if (USBEndP < `NUM_OF_ENDPOINTS &&
402			`USBAddress == USBTgtAddress &&`
403			`SCGlobalEn == 1'b1 &&`
404			USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
405			`begin`
406			NextState_slvCntrl <= `CHK_PID;
407			`end`
408			`else`
409			`begin`
410			NextState_slvCntrl <= `WAIT_RX1;
411			`end`
412			`end`
413			`endcase`
414			`end`
415
416			`// Current State Logic (sequential)`
417			`always @ (posedge clk)`
418			`begin`
419			`if (rst)`
420			CurrState_slvCntrl <= `START_S1;
421			`else`
422			`CurrState_slvCntrl <= NextState_slvCntrl;`
423			`end`
424
425			`// Registered outputs logic`
426			`always @ (posedge clk)`
427			`begin`
428			`if (rst)`
429			`begin`
430			`stallSent <= 1'b0;`
431			`NAKSent <= 1'b0;`
432			`SOFRxed <= 1'b0;`
433			`transDone <= 1'b0;`
434			`clrEPRdy <= 1'b0;`
435			`endPMuxErrorsWEn <= 1'b0;`
436			`frameNum <= 11'b00000000000;`
437			`USBEndP <= 4'h0;`
438			`USBEndPTransTypeReg <= 2'b00;`
439			`USBEndPNakTransTypeReg <= 2'b00;`
440			`sendPacketWEn <= 1'b0;`
441			`sendPacketPID <= 4'b0;`
442			`getPacketREn <= 1'b0;`
443			`PIDByte <= 8'h00;`
444			`endpCRCTemp <= 8'h00;`
445			`addrEndPTemp <= 8'h00;`
446			`tempUSBEndPTransTypeReg <= 2'b00;`
447			`USBAddress <= 7'b0000000;`
448			`end`
449			`else`
450			`begin`
451			`stallSent <= next_stallSent;`
452			`NAKSent <= next_NAKSent;`
453			`SOFRxed <= next_SOFRxed;`
454			`transDone <= next_transDone;`
455			`clrEPRdy <= next_clrEPRdy;`
456			`endPMuxErrorsWEn <= next_endPMuxErrorsWEn;`
457			`frameNum <= next_frameNum;`
458			`USBEndP <= next_USBEndP;`
459			`USBEndPTransTypeReg <= next_USBEndPTransTypeReg;`
460			`USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;`
461			`sendPacketWEn <= next_sendPacketWEn;`
462			`sendPacketPID <= next_sendPacketPID;`
463			`getPacketREn <= next_getPacketREn;`
464			`PIDByte <= next_PIDByte;`
465			`endpCRCTemp <= next_endpCRCTemp;`
466			`addrEndPTemp <= next_addrEndPTemp;`
467			`tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;`
468			`USBAddress <= next_USBAddress;`
469			`end`
470			`end`
471
472	2	sfielding	`endmodule`