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sfielding |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// usbSlaveControl.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module usbSlaveControl(
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busClk,
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rstSyncToBusClk,
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usbClk,
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rstSyncToUsbClk,
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//getPacket
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RxByteStatus, RxData, RxDataValid,
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SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
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//speedCtrlMux
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fullSpeedRate, fullSpeedPol,
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//SCTxPortArbiter
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SCTxPortEn, SCTxPortRdy,
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SCTxPortData, SCTxPortCtrl,
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//rxStatusMonitor
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connectStateIn,
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resumeDetectedIn,
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//USBHostControlBI
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busAddress,
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busDataIn,
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busDataOut,
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busWriteEn,
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busStrobe_i,
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SOFRxedIntOut,
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resetEventIntOut,
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resumeIntOut,
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transDoneIntOut,
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NAKSentIntOut,
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slaveControlSelect,
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//fifoMux
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TxFifoEP0REn,
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TxFifoEP1REn,
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TxFifoEP2REn,
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TxFifoEP3REn,
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TxFifoEP0Data,
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TxFifoEP1Data,
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TxFifoEP2Data,
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TxFifoEP3Data,
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TxFifoEP0Empty,
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TxFifoEP1Empty,
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TxFifoEP2Empty,
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TxFifoEP3Empty,
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RxFifoEP0WEn,
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RxFifoEP1WEn,
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RxFifoEP2WEn,
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RxFifoEP3WEn,
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RxFifoEP0Full,
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RxFifoEP1Full,
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RxFifoEP2Full,
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RxFifoEP3Full
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);
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input busClk;
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input rstSyncToBusClk;
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input usbClk;
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input rstSyncToUsbClk;
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//getPacket
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input [7:0] RxByteStatus;
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input [7:0] RxData;
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input RxDataValid;
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input SIERxTimeOut;
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output SIERxTimeOutEn;
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output [7:0] RxFifoData;
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//speedCtrlMux
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output fullSpeedRate;
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output fullSpeedPol;
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//HCTxPortArbiter
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output SCTxPortEn;
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input SCTxPortRdy;
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output [7:0] SCTxPortData;
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output [7:0] SCTxPortCtrl;
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//rxStatusMonitor
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input [1:0] connectStateIn;
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input resumeDetectedIn;
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//USBHostControlBI
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input [4:0] busAddress;
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input [7:0] busDataIn;
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output [7:0] busDataOut;
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input busWriteEn;
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input busStrobe_i;
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output SOFRxedIntOut;
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output resetEventIntOut;
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output resumeIntOut;
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output transDoneIntOut;
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output NAKSentIntOut;
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input slaveControlSelect;
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//fifoMux
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output TxFifoEP0REn;
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output TxFifoEP1REn;
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output TxFifoEP2REn;
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output TxFifoEP3REn;
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input [7:0] TxFifoEP0Data;
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input [7:0] TxFifoEP1Data;
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input [7:0] TxFifoEP2Data;
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input [7:0] TxFifoEP3Data;
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input TxFifoEP0Empty;
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input TxFifoEP1Empty;
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input TxFifoEP2Empty;
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input TxFifoEP3Empty;
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output RxFifoEP0WEn;
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output RxFifoEP1WEn;
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output RxFifoEP2WEn;
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output RxFifoEP3WEn;
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input RxFifoEP0Full;
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input RxFifoEP1Full;
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input RxFifoEP2Full;
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input RxFifoEP3Full;
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wire busClk;
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wire rstSyncToBusClk;
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wire usbClk;
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wire rstSyncToUsbClk;
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wire [7:0] RxByteStatus;
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wire [7:0] RxData;
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wire RxDataValid;
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wire SIERxTimeOut;
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wire SIERxTimeOutEn;
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wire [7:0] RxFifoData;
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wire fullSpeedRate;
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wire fullSpeedPol;
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wire [7:0] SCTxPortData;
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wire [7:0] SCTxPortCtrl;
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wire [1:0] connectStateIn;
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wire resumeDetectedIn;
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wire [4:0] busAddress;
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wire [7:0] busDataIn;
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wire [7:0] busDataOut;
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wire busWriteEn;
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wire busStrobe_i;
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wire SOFRxedIntOut;
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wire resetEventIntOut;
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wire resumeIntOut;
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wire transDoneIntOut;
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wire NAKSentIntOut;
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wire slaveControlSelect;
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wire TxFifoEP0REn;
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wire TxFifoEP1REn;
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wire TxFifoEP2REn;
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wire TxFifoEP3REn;
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wire [7:0] TxFifoEP0Data;
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wire [7:0] TxFifoEP1Data;
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wire [7:0] TxFifoEP2Data;
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wire [7:0] TxFifoEP3Data;
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wire TxFifoEP0Empty;
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wire TxFifoEP1Empty;
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wire TxFifoEP2Empty;
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wire TxFifoEP3Empty;
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wire RxFifoEP0WEn;
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wire RxFifoEP1WEn;
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wire RxFifoEP2WEn;
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wire RxFifoEP3WEn;
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wire RxFifoEP0Full;
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wire RxFifoEP1Full;
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wire RxFifoEP2Full;
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wire RxFifoEP3Full;
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//internal wiring
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wire [7:0] directCntlCntl;
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wire [7:0] directCntlData;
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wire directCntlGnt;
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wire directCntlReq;
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wire directCntlWEn;
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wire [7:0] sendPacketCntl;
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wire [7:0] sendPacketData;
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wire sendPacketGnt;
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| 210 |
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wire sendPacketReq;
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wire sendPacketWEn;
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wire SCTxPortArbRdyOut;
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wire transDone;
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wire [1:0] directLineState;
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wire directLineCtrlEn;
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wire [3:0] RxPID;
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wire [1:0] connectStateOut;
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wire resumeIntFromRxStatusMon;
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wire [1:0] endP0TransTypeReg;
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wire [1:0] endP1TransTypeReg;
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wire [1:0] endP2TransTypeReg;
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wire [1:0] endP3TransTypeReg;
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wire [1:0] endP0NAKTransTypeReg;
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wire [1:0] endP1NAKTransTypeReg;
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wire [1:0] endP2NAKTransTypeReg;
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wire [1:0] endP3NAKTransTypeReg;
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wire [4:0] endP0ControlReg;
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wire [4:0] endP1ControlReg;
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wire [4:0] endP2ControlReg;
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wire [4:0] endP3ControlReg;
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wire [7:0] endP0StatusReg;
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wire [7:0] endP1StatusReg;
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wire [7:0] endP2StatusReg;
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wire [7:0] endP3StatusReg;
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wire [6:0] USBTgtAddress;
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wire [10:0] frameNum;
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wire clrEP0Rdy;
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wire clrEP1Rdy;
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wire clrEP2Rdy;
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wire clrEP3Rdy;
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wire SCGlobalEn;
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wire ACKRxed;
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| 243 |
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wire CRCError;
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| 244 |
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wire RXOverflow;
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wire RXTimeOut;
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wire bitStuffError;
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| 247 |
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wire dataSequence;
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| 248 |
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wire stallSent;
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| 249 |
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wire NAKSent;
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wire SOFRxed;
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| 251 |
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wire [4:0] endPControlReg;
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| 252 |
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wire [1:0] transTypeNAK;
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| 253 |
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wire [1:0] transType;
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| 254 |
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wire [3:0] currEndP;
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| 255 |
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wire getPacketREn;
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| 256 |
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wire getPacketRdy;
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| 257 |
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wire [3:0] slaveControllerPIDOut;
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| 258 |
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wire slaveControllerReadyIn;
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| 259 |
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wire slaveControllerWEnOut;
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| 260 |
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wire TxFifoRE;
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| 261 |
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wire [7:0] TxFifoData;
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| 262 |
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wire TxFifoEmpty;
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| 263 |
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wire RxFifoWE;
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| 264 |
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wire RxFifoFull;
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| 265 |
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wire resetEventFromRxStatusMon;
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| 266 |
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wire clrEPRdy;
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| 267 |
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wire endPMuxErrorsWEn;
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| 268 |
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wire endPointReadyFromSlaveCtrlrToGetPkt;
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| 269 |
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| 270 |
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USBSlaveControlBI u_USBSlaveControlBI
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| 271 |
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(.address(busAddress),
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| 272 |
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.dataIn(busDataIn),
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| 273 |
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.dataOut(busDataOut),
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| 274 |
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.writeEn(busWriteEn),
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| 275 |
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.strobe_i(busStrobe_i),
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| 276 |
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.busClk(busClk),
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| 277 |
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.rstSyncToBusClk(rstSyncToBusClk),
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| 278 |
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.usbClk(usbClk),
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| 279 |
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.rstSyncToUsbClk(rstSyncToUsbClk),
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| 280 |
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.SOFRxedIntOut(SOFRxedIntOut),
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| 281 |
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.resetEventIntOut(resetEventIntOut),
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| 282 |
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.resumeIntOut(resumeIntOut),
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| 283 |
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.transDoneIntOut(transDoneIntOut),
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| 284 |
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.NAKSentIntOut(NAKSentIntOut),
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| 285 |
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.endP0TransTypeReg(endP0TransTypeReg),
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| 286 |
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.endP0NAKTransTypeReg(endP0NAKTransTypeReg),
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| 287 |
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.endP1TransTypeReg(endP1TransTypeReg),
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| 288 |
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.endP1NAKTransTypeReg(endP1NAKTransTypeReg),
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| 289 |
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.endP2TransTypeReg(endP2TransTypeReg),
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| 290 |
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.endP2NAKTransTypeReg(endP2NAKTransTypeReg),
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| 291 |
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.endP3TransTypeReg(endP3TransTypeReg),
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| 292 |
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.endP3NAKTransTypeReg(endP3NAKTransTypeReg),
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| 293 |
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.endP0ControlReg(endP0ControlReg),
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| 294 |
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.endP1ControlReg(endP1ControlReg),
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| 295 |
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.endP2ControlReg(endP2ControlReg),
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| 296 |
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.endP3ControlReg(endP3ControlReg),
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| 297 |
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.EP0StatusReg(endP0StatusReg),
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| 298 |
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.EP1StatusReg(endP1StatusReg),
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| 299 |
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.EP2StatusReg(endP2StatusReg),
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| 300 |
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.EP3StatusReg(endP3StatusReg),
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| 301 |
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.SCAddrReg(USBTgtAddress),
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| 302 |
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.frameNum(frameNum),
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| 303 |
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.connectStateIn(connectStateOut),
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| 304 |
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.SOFRxedIn(SOFRxed),
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| 305 |
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.resetEventIn(resetEventFromRxStatusMon),
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| 306 |
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.resumeIntIn(resumeIntFromRxStatusMon),
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| 307 |
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.transDoneIn(transDone),
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| 308 |
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.NAKSentIn(NAKSent),
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| 309 |
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.slaveControlSelect(slaveControlSelect),
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| 310 |
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.clrEP0Ready(clrEP0Rdy),
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| 311 |
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.clrEP1Ready(clrEP1Rdy),
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| 312 |
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.clrEP2Ready(clrEP2Rdy),
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| 313 |
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.clrEP3Ready(clrEP3Rdy),
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| 314 |
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.TxLineState(directLineState),
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| 315 |
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.LineDirectControlEn(directLineCtrlEn),
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| 316 |
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.fullSpeedPol(fullSpeedPol),
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| 317 |
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.fullSpeedRate(fullSpeedRate),
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| 318 |
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.SCGlobalEn(SCGlobalEn)
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| 319 |
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);
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| 320 |
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|
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| 321 |
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slavecontroller u_slavecontroller
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| 322 |
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(.CRCError(CRCError),
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| 323 |
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.NAKSent(NAKSent),
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| 324 |
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.RxByte(RxData),
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| 325 |
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.RxDataWEn(RxDataValid),
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| 326 |
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.RxOverflow(RXOverflow),
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| 327 |
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.RxStatus(RxByteStatus),
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| 328 |
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.RxTimeOut(RXTimeOut),
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| 329 |
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.SCGlobalEn(SCGlobalEn),
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| 330 |
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.SOFRxed(SOFRxed),
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| 331 |
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.USBEndPControlReg(endPControlReg),
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| 332 |
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.USBEndPNakTransTypeReg(transTypeNAK),
|
| 333 |
|
|
.USBEndPTransTypeReg(transType),
|
| 334 |
|
|
.USBEndP(currEndP),
|
| 335 |
|
|
.USBTgtAddress(USBTgtAddress),
|
| 336 |
|
|
.bitStuffError(bitStuffError),
|
| 337 |
|
|
.clk(usbClk),
|
| 338 |
|
|
.clrEPRdy(clrEPRdy),
|
| 339 |
|
|
.endPMuxErrorsWEn(endPMuxErrorsWEn),
|
| 340 |
|
|
.frameNum(frameNum),
|
| 341 |
|
|
.getPacketREn(getPacketREn),
|
| 342 |
|
|
.getPacketRdy(getPacketRdy),
|
| 343 |
|
|
.rst(rstSyncToUsbClk),
|
| 344 |
|
|
.sendPacketPID(slaveControllerPIDOut),
|
| 345 |
|
|
.sendPacketRdy(slaveControllerReadyIn),
|
| 346 |
|
|
.sendPacketWEn(slaveControllerWEnOut),
|
| 347 |
|
|
.stallSent(stallSent),
|
| 348 |
|
|
.transDone(transDone),
|
| 349 |
|
|
.endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
|
| 350 |
|
|
);
|
| 351 |
|
|
|
| 352 |
|
|
|
| 353 |
|
|
endpMux u_endpMux (
|
| 354 |
|
|
.clk(usbClk),
|
| 355 |
|
|
.rst(rstSyncToUsbClk),
|
| 356 |
|
|
.currEndP(currEndP),
|
| 357 |
|
|
.NAKSent(NAKSent),
|
| 358 |
|
|
.stallSent(stallSent),
|
| 359 |
|
|
.CRCError(CRCError),
|
| 360 |
|
|
.bitStuffError(bitStuffError),
|
| 361 |
|
|
.RxOverflow(RXOverflow),
|
| 362 |
|
|
.RxTimeOut(RXTimeOut),
|
| 363 |
|
|
.dataSequence(dataSequence),
|
| 364 |
|
|
.ACKRxed(ACKRxed),
|
| 365 |
|
|
.transType(transType),
|
| 366 |
|
|
.transTypeNAK(transTypeNAK),
|
| 367 |
|
|
.endPControlReg(endPControlReg),
|
| 368 |
|
|
.clrEPRdy(clrEPRdy),
|
| 369 |
|
|
.endPMuxErrorsWEn(endPMuxErrorsWEn),
|
| 370 |
|
|
.endP0ControlReg(endP0ControlReg),
|
| 371 |
|
|
.endP1ControlReg(endP1ControlReg),
|
| 372 |
|
|
.endP2ControlReg(endP2ControlReg),
|
| 373 |
|
|
.endP3ControlReg(endP3ControlReg),
|
| 374 |
|
|
.endP0StatusReg(endP0StatusReg),
|
| 375 |
|
|
.endP1StatusReg(endP1StatusReg),
|
| 376 |
|
|
.endP2StatusReg(endP2StatusReg),
|
| 377 |
|
|
.endP3StatusReg(endP3StatusReg),
|
| 378 |
|
|
.endP0TransTypeReg(endP0TransTypeReg),
|
| 379 |
|
|
.endP1TransTypeReg(endP1TransTypeReg),
|
| 380 |
|
|
.endP2TransTypeReg(endP2TransTypeReg),
|
| 381 |
|
|
.endP3TransTypeReg(endP3TransTypeReg),
|
| 382 |
|
|
.endP0NAKTransTypeReg(endP0NAKTransTypeReg),
|
| 383 |
|
|
.endP1NAKTransTypeReg(endP1NAKTransTypeReg),
|
| 384 |
|
|
.endP2NAKTransTypeReg(endP2NAKTransTypeReg),
|
| 385 |
|
|
.endP3NAKTransTypeReg(endP3NAKTransTypeReg),
|
| 386 |
|
|
.clrEP0Rdy(clrEP0Rdy),
|
| 387 |
|
|
.clrEP1Rdy(clrEP1Rdy),
|
| 388 |
|
|
.clrEP2Rdy(clrEP2Rdy),
|
| 389 |
|
|
.clrEP3Rdy(clrEP3Rdy)
|
| 390 |
|
|
);
|
| 391 |
|
|
|
| 392 |
|
|
slaveSendPacket u_slaveSendPacket
|
| 393 |
|
|
(.PID(slaveControllerPIDOut),
|
| 394 |
|
|
.SCTxPortCntl(sendPacketCntl),
|
| 395 |
|
|
.SCTxPortData(sendPacketData),
|
| 396 |
|
|
.SCTxPortGnt(sendPacketGnt),
|
| 397 |
|
|
.SCTxPortRdy(SCTxPortArbRdyOut),
|
| 398 |
|
|
.SCTxPortReq(sendPacketReq),
|
| 399 |
|
|
.SCTxPortWEn(sendPacketWEn),
|
| 400 |
|
|
.clk(usbClk),
|
| 401 |
|
|
.fifoData(TxFifoData),
|
| 402 |
|
|
.fifoEmpty(TxFifoEmpty),
|
| 403 |
|
|
.fifoReadEn(TxFifoRE),
|
| 404 |
|
|
.rst(rstSyncToUsbClk),
|
| 405 |
|
|
.sendPacketRdy(slaveControllerReadyIn),
|
| 406 |
|
|
.sendPacketWEn(slaveControllerWEnOut) );
|
| 407 |
|
|
|
| 408 |
|
|
slaveDirectControl u_slaveDirectControl
|
| 409 |
|
|
(.SCTxPortCntl(directCntlCntl),
|
| 410 |
|
|
.SCTxPortData(directCntlData),
|
| 411 |
|
|
.SCTxPortGnt(directCntlGnt),
|
| 412 |
|
|
.SCTxPortRdy(SCTxPortArbRdyOut),
|
| 413 |
|
|
.SCTxPortReq(directCntlReq),
|
| 414 |
|
|
.SCTxPortWEn(directCntlWEn),
|
| 415 |
|
|
.clk(usbClk),
|
| 416 |
|
|
.directControlEn(directLineCtrlEn),
|
| 417 |
|
|
.directControlLineState(directLineState),
|
| 418 |
|
|
.rst(rstSyncToUsbClk) );
|
| 419 |
|
|
|
| 420 |
|
|
SCTxPortArbiter u_SCTxPortArbiter
|
| 421 |
|
|
(.SCTxPortCntl(SCTxPortCtrl),
|
| 422 |
|
|
.SCTxPortData(SCTxPortData),
|
| 423 |
|
|
.SCTxPortRdyIn(SCTxPortRdy),
|
| 424 |
|
|
.SCTxPortRdyOut(SCTxPortArbRdyOut),
|
| 425 |
|
|
.SCTxPortWEnable(SCTxPortEn),
|
| 426 |
|
|
.clk(usbClk),
|
| 427 |
|
|
.directCntlCntl(directCntlCntl),
|
| 428 |
|
|
.directCntlData(directCntlData),
|
| 429 |
|
|
.directCntlGnt(directCntlGnt),
|
| 430 |
|
|
.directCntlReq(directCntlReq),
|
| 431 |
|
|
.directCntlWEn(directCntlWEn),
|
| 432 |
|
|
.rst(rstSyncToUsbClk),
|
| 433 |
|
|
.sendPacketCntl(sendPacketCntl),
|
| 434 |
|
|
.sendPacketData(sendPacketData),
|
| 435 |
|
|
.sendPacketGnt(sendPacketGnt),
|
| 436 |
|
|
.sendPacketReq(sendPacketReq),
|
| 437 |
|
|
.sendPacketWEn(sendPacketWEn) );
|
| 438 |
|
|
|
| 439 |
|
|
|
| 440 |
|
|
slaveGetPacket u_slaveGetPacket
|
| 441 |
|
|
(.ACKRxed(ACKRxed),
|
| 442 |
|
|
.CRCError(CRCError),
|
| 443 |
|
|
.RXDataIn(RxData),
|
| 444 |
|
|
.RXDataValid(RxDataValid),
|
| 445 |
|
|
.RXFifoData(RxFifoData),
|
| 446 |
|
|
.RXFifoFull(RxFifoFull),
|
| 447 |
|
|
.RXFifoWEn(RxFifoWE),
|
| 448 |
|
|
.RXPacketRdy(getPacketRdy),
|
| 449 |
|
|
.RXStreamStatusIn(RxByteStatus),
|
| 450 |
|
|
.RxPID(RxPID),
|
| 451 |
|
|
.SIERxTimeOut(SIERxTimeOut),
|
| 452 |
|
|
.SIERxTimeOutEn(SIERxTimeOutEn),
|
| 453 |
|
|
.clk(usbClk),
|
| 454 |
|
|
.RXOverflow(RXOverflow),
|
| 455 |
|
|
.RXTimeOut(RXTimeOut),
|
| 456 |
|
|
.bitStuffError(bitStuffError),
|
| 457 |
|
|
.dataSequence(dataSequence),
|
| 458 |
|
|
.getPacketEn(getPacketREn),
|
| 459 |
|
|
.rst(rstSyncToUsbClk),
|
| 460 |
|
|
.endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
|
| 461 |
|
|
);
|
| 462 |
|
|
|
| 463 |
|
|
slaveRxStatusMonitor u_slaveRxStatusMonitor
|
| 464 |
|
|
(.connectStateIn(connectStateIn),
|
| 465 |
|
|
.connectStateOut(connectStateOut),
|
| 466 |
|
|
.resumeDetectedIn(resumeDetectedIn),
|
| 467 |
|
|
.resetEventOut(resetEventFromRxStatusMon),
|
| 468 |
|
|
.resumeIntOut(resumeIntFromRxStatusMon),
|
| 469 |
|
|
.clk(usbClk),
|
| 470 |
|
|
.rst(rstSyncToUsbClk) );
|
| 471 |
|
|
|
| 472 |
|
|
fifoMux u_fifoMux (
|
| 473 |
|
|
.currEndP(currEndP),
|
| 474 |
|
|
//TxFifo
|
| 475 |
|
|
.TxFifoREn(TxFifoRE),
|
| 476 |
|
|
.TxFifoEP0REn(TxFifoEP0REn),
|
| 477 |
|
|
.TxFifoEP1REn(TxFifoEP1REn),
|
| 478 |
|
|
.TxFifoEP2REn(TxFifoEP2REn),
|
| 479 |
|
|
.TxFifoEP3REn(TxFifoEP3REn),
|
| 480 |
|
|
.TxFifoData(TxFifoData),
|
| 481 |
|
|
.TxFifoEP0Data(TxFifoEP0Data),
|
| 482 |
|
|
.TxFifoEP1Data(TxFifoEP1Data),
|
| 483 |
|
|
.TxFifoEP2Data(TxFifoEP2Data),
|
| 484 |
|
|
.TxFifoEP3Data(TxFifoEP3Data),
|
| 485 |
|
|
.TxFifoEmpty(TxFifoEmpty),
|
| 486 |
|
|
.TxFifoEP0Empty(TxFifoEP0Empty),
|
| 487 |
|
|
.TxFifoEP1Empty(TxFifoEP1Empty),
|
| 488 |
|
|
.TxFifoEP2Empty(TxFifoEP2Empty),
|
| 489 |
|
|
.TxFifoEP3Empty(TxFifoEP3Empty),
|
| 490 |
|
|
//RxFifo
|
| 491 |
|
|
.RxFifoWEn(RxFifoWE),
|
| 492 |
|
|
.RxFifoEP0WEn(RxFifoEP0WEn),
|
| 493 |
|
|
.RxFifoEP1WEn(RxFifoEP1WEn),
|
| 494 |
|
|
.RxFifoEP2WEn(RxFifoEP2WEn),
|
| 495 |
|
|
.RxFifoEP3WEn(RxFifoEP3WEn),
|
| 496 |
|
|
.RxFifoFull(RxFifoFull),
|
| 497 |
|
|
.RxFifoEP0Full(RxFifoEP0Full),
|
| 498 |
|
|
.RxFifoEP1Full(RxFifoEP1Full),
|
| 499 |
|
|
.RxFifoEP2Full(RxFifoEP2Full),
|
| 500 |
|
|
.RxFifoEP3Full(RxFifoEP3Full)
|
| 501 |
|
|
);
|
| 502 |
|
|
|
| 503 |
|
|
endmodule
|
| 504 |
|
|
|
| 505 |
|
|
|
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
|
| 510 |
|
|
|
