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[/] [usbhostslave/] [trunk/] [RTL/] [wrapper/] [usbHostSlave.v] - Blame information for rev 43

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Line No. Rev Author Line
1 43 sfielding
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// usbHostSlave.v                                               ////
4
////                                                              ////
5
//// This file is part of the usbhostslave opencores effort.
6
//// <http://www.opencores.org/cores//>                           ////
7
////                                                              ////
8
//// Module Description:                                          ////
9
////   Top level module
10
////                                                              ////
11
//// To Do:                                                       ////
12
//// 
13
////                                                              ////
14
//// Author(s):                                                   ////
15
//// - Steve Fielding, sfielding@base2designs.com                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE. See the GNU Lesser General Public License for more  ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from <http://www.opencores.org/lgpl.shtml>                   ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
`include "timescale.v"
45
 
46
module usbHostSlave(
47
  clk_i,
48
  rst_i,
49
  address_i,
50
  data_i,
51
  data_o,
52
  we_i,
53
  strobe_i,
54
  ack_o,
55
  usbClk,
56
  hostSOFSentIntOut,
57
  hostConnEventIntOut,
58
  hostResumeIntOut,
59
  hostTransDoneIntOut,
60
  slaveVBusDetIntOut,
61
  slaveNAKSentIntOut,
62
  slaveSOFRxedIntOut,
63
  slaveResetEventIntOut,
64
  slaveResumeIntOut,
65
  slaveTransDoneIntOut,
66
  USBWireDataIn,
67
  USBWireDataInTick,
68
  USBWireDataOut,
69
  USBWireDataOutTick,
70
  USBWireCtrlOut,
71
  USBFullSpeed,
72
  USBDPlusPullup,
73
  USBDMinusPullup,
74
  vBusDetect
75
   );
76
  parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
77
  parameter HOST_FIFO_ADDR_WIDTH = 6;
78
  parameter EP0_FIFO_DEPTH = 64;
79
  parameter EP0_FIFO_ADDR_WIDTH = 6;
80
  parameter EP1_FIFO_DEPTH = 64;
81
  parameter EP1_FIFO_ADDR_WIDTH = 6;
82
  parameter EP2_FIFO_DEPTH = 64;
83
  parameter EP2_FIFO_ADDR_WIDTH = 6;
84
  parameter EP3_FIFO_DEPTH = 64;
85
  parameter EP3_FIFO_ADDR_WIDTH = 6;
86
 
87
input clk_i;               //Wishbone bus clock. Min = usbClk/2 = 24MHz. Max 5*usbClk=240MHz
88
input rst_i;               //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
89
input [7:0] address_i;     //Wishbone bus address in
90
input [7:0] data_i;        //Wishbone bus data in
91
output [7:0] data_o;       //Wishbone bus data out
92
input we_i;                //Wishbone bus write enable in
93
input strobe_i;            //Wishbone bus strobe in
94
output ack_o;              //Wishbone bus acknowledge out
95
input usbClk;              //usb clock. 48Mhz +/-0.25%
96
output hostSOFSentIntOut;
97
output hostConnEventIntOut;
98
output hostResumeIntOut;
99
output hostTransDoneIntOut;
100
output slaveSOFRxedIntOut;
101
output slaveResetEventIntOut;
102
output slaveResumeIntOut;
103
output slaveTransDoneIntOut;
104
output slaveNAKSentIntOut;
105
output slaveVBusDetIntOut;
106
input [1:0] USBWireDataIn;
107
output [1:0] USBWireDataOut;
108
output USBWireDataOutTick;
109
output USBWireDataInTick;
110
output USBWireCtrlOut;
111
output USBFullSpeed;
112
output USBDPlusPullup;
113
output USBDMinusPullup;
114
input vBusDetect;
115
 
116
wire clk_i;
117
wire rst_i;
118
wire [7:0] address_i;
119
wire [7:0] data_i;
120
wire [7:0] data_o;
121
wire we_i;
122
wire strobe_i;
123
wire ack_o;
124
wire usbClk;
125
wire hostSOFSentIntOut;
126
wire hostConnEventIntOut;
127
wire hostResumeIntOut;
128
wire hostTransDoneIntOut;
129
wire slaveSOFRxedIntOut;
130
wire slaveResetEventIntOut;
131
wire slaveResumeIntOut;
132
wire slaveTransDoneIntOut;
133
wire slaveNAKSentIntOut;
134
wire slaveVBusDetIntOut;
135
wire [1:0] USBWireDataIn;
136
wire [1:0] USBWireDataOut;
137
wire USBWireDataOutTick;
138
wire USBWireDataInTick;
139
wire USBWireCtrlOut;
140
wire USBFullSpeed;
141
wire USBDPlusPullup;
142
wire USBDMinusPullup;
143
wire vBusDetect;
144
 
145
//internal wiring
146
wire hostControlSel;
147
wire slaveControlSel;
148
wire hostRxFifoSel;
149
wire hostTxFifoSel;
150
wire hostSlaveMuxSel;
151
wire [7:0] dataFromHostControl;
152
wire [7:0] dataFromSlaveControl;
153
wire [7:0] dataFromHostRxFifo;
154
wire [7:0] dataFromHostTxFifo;
155
wire [7:0] dataFromHostSlaveMux;
156
wire hostTxFifoRE;
157
wire [7:0] hostTxFifoData;
158
wire hostTxFifoEmpty;
159
wire hostRxFifoWE;
160
wire [7:0] hostRxFifoData;
161
wire hostRxFifoFull;
162
wire [7:0] RxCtrlOut;
163
wire [7:0] RxDataFromSIE;
164
wire RxDataOutWEn;
165
wire fullSpeedBitRateFromHost;
166
wire fullSpeedBitRateFromSlave;
167
wire fullSpeedPolarityFromHost;
168
wire fullSpeedPolarityFromSlave;
169
wire SIEPortWEnFromHost;
170
wire SIEPortWEnFromSlave;
171
wire SIEPortTxRdy;
172
wire [7:0] SIEPortDataInFromHost;
173
wire [7:0] SIEPortDataInFromSlave;
174
wire [7:0] SIEPortCtrlInFromHost;
175
wire [7:0] SIEPortCtrlInFromSlave;
176
wire [1:0] connectState;
177
wire resumeDetected;
178
wire [7:0] SIEPortDataInToSIE;
179
wire SIEPortWEnToSIE;
180
wire [7:0] SIEPortCtrlInToSIE;
181
wire fullSpeedPolarityToSIE;
182
wire fullSpeedBitRateToSIE;
183
wire noActivityTimeOut;
184
wire TxFifoEP0REn;
185
wire TxFifoEP1REn;
186
wire TxFifoEP2REn;
187
wire TxFifoEP3REn;
188
wire [7:0] TxFifoEP0Data;
189
wire [7:0] TxFifoEP1Data;
190
wire [7:0] TxFifoEP2Data;
191
wire [7:0] TxFifoEP3Data;
192
wire TxFifoEP0Empty;
193
wire TxFifoEP1Empty;
194
wire TxFifoEP2Empty;
195
wire TxFifoEP3Empty;
196
wire RxFifoEP0WEn;
197
wire RxFifoEP1WEn;
198
wire RxFifoEP2WEn;
199
wire RxFifoEP3WEn;
200
wire RxFifoEP0Full;
201
wire RxFifoEP1Full;
202
wire RxFifoEP2Full;
203
wire RxFifoEP3Full;
204
wire [7:0] slaveRxFifoData;
205
wire [7:0] dataFromEP0RxFifo;
206
wire [7:0] dataFromEP1RxFifo;
207
wire [7:0] dataFromEP2RxFifo;
208
wire [7:0] dataFromEP3RxFifo;
209
wire [7:0] dataFromEP0TxFifo;
210
wire [7:0] dataFromEP1TxFifo;
211
wire [7:0] dataFromEP2TxFifo;
212
wire [7:0] dataFromEP3TxFifo;
213
wire slaveEP0RxFifoSel;
214
wire slaveEP1RxFifoSel;
215
wire slaveEP2RxFifoSel;
216
wire slaveEP3RxFifoSel;
217
wire slaveEP0TxFifoSel;
218
wire slaveEP1TxFifoSel;
219
wire slaveEP2TxFifoSel;
220
wire slaveEP3TxFifoSel;
221
wire rstSyncToBusClk;
222
wire rstSyncToUsbClk;
223
wire noActivityTimeOutEnableToSIE;
224
wire noActivityTimeOutEnableFromHost;
225
wire noActivityTimeOutEnableFromSlave;
226
wire connectSlaveToHost;
227
 
228
// This is not a bug.
229
// USBFullSpeed controls the PHY edge speed.
230
// The only time that the PHY needs to operate with low speed edge rate is
231
// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
232
// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
233
// but according to spec edge speed must be full rate edge speed. 
234
assign USBFullSpeed = fullSpeedPolarityToSIE;
235
//assign USBFullSpeed = fullSpeedBitRateToSIE;  
236
assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
237
assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
238
 
239
usbHostControl u_usbHostControl(
240
  .busClk(clk_i),
241
  .rstSyncToBusClk(rstSyncToBusClk),
242
  .usbClk(usbClk),
243
  .rstSyncToUsbClk(rstSyncToUsbClk),
244
  .TxFifoRE(hostTxFifoRE),
245
  .TxFifoData(hostTxFifoData),
246
  .TxFifoEmpty(hostTxFifoEmpty),
247
  .RxFifoWE(hostRxFifoWE),
248
  .RxFifoData(hostRxFifoData),
249
  .RxFifoFull(hostRxFifoFull),
250
  .RxByteStatus(RxCtrlOut),
251
  .RxData(RxDataFromSIE),
252
  .RxDataValid(RxDataOutWEn),
253
  .SIERxTimeOut(noActivityTimeOut),
254
  .SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
255
  .fullSpeedRate(fullSpeedBitRateFromHost),
256
  .fullSpeedPol(fullSpeedPolarityFromHost),
257
  .HCTxPortEn(SIEPortWEnFromHost),
258
  .HCTxPortRdy(SIEPortTxRdy),
259
  .HCTxPortData(SIEPortDataInFromHost),
260
  .HCTxPortCtrl(SIEPortCtrlInFromHost),
261
  .connectStateIn(connectState),
262
  .resumeDetectedIn(resumeDetected),
263
  .busAddress(address_i[3:0]),
264
  .busDataIn(data_i),
265
  .busDataOut(dataFromHostControl),
266
  .busWriteEn(we_i),
267
  .busStrobe_i(strobe_i),
268
  .SOFSentIntOut(hostSOFSentIntOut),
269
  .connEventIntOut(hostConnEventIntOut),
270
  .resumeIntOut(hostResumeIntOut),
271
  .transDoneIntOut(hostTransDoneIntOut),
272
  .hostControlSelect(hostControlSel) );
273
 
274
 
275
usbSlaveControl u_usbSlaveControl(
276
  .busClk(clk_i),
277
  .rstSyncToBusClk(rstSyncToBusClk),
278
  .usbClk(usbClk),
279
  .rstSyncToUsbClk(rstSyncToUsbClk),
280
  .RxByteStatus(RxCtrlOut),
281
  .RxData(RxDataFromSIE),
282
  .RxDataValid(RxDataOutWEn),
283
  .SIERxTimeOut(noActivityTimeOut),
284
  .SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
285
  .RxFifoData(slaveRxFifoData),
286
  .connectSlaveToHost(connectSlaveToHost),
287
  .fullSpeedRate(fullSpeedBitRateFromSlave),
288
  .fullSpeedPol(fullSpeedPolarityFromSlave),
289
  .SCTxPortEn(SIEPortWEnFromSlave),
290
  .SCTxPortRdy(SIEPortTxRdy),
291
  .SCTxPortData(SIEPortDataInFromSlave),
292
  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
293
  .vBusDetect(vBusDetect),
294
  .connectStateIn(connectState),
295
  .resumeDetectedIn(resumeDetected),
296
  .busAddress(address_i[4:0]),
297
  .busDataIn(data_i),
298
  .busDataOut(dataFromSlaveControl),
299
  .busWriteEn(we_i),
300
  .busStrobe_i(strobe_i),
301
  .SOFRxedIntOut(slaveSOFRxedIntOut),
302
  .resetEventIntOut(slaveResetEventIntOut),
303
  .resumeIntOut(slaveResumeIntOut),
304
  .transDoneIntOut(slaveTransDoneIntOut),
305
  .NAKSentIntOut(slaveNAKSentIntOut),
306
  .vBusDetIntOut(slaveVBusDetIntOut),
307
  .slaveControlSelect(slaveControlSel),
308
  .TxFifoEP0REn(TxFifoEP0REn),
309
  .TxFifoEP1REn(TxFifoEP1REn),
310
  .TxFifoEP2REn(TxFifoEP2REn),
311
  .TxFifoEP3REn(TxFifoEP3REn),
312
  .TxFifoEP0Data(TxFifoEP0Data),
313
  .TxFifoEP1Data(TxFifoEP1Data),
314
  .TxFifoEP2Data(TxFifoEP2Data),
315
  .TxFifoEP3Data(TxFifoEP3Data),
316
  .TxFifoEP0Empty(TxFifoEP0Empty),
317
  .TxFifoEP1Empty(TxFifoEP1Empty),
318
  .TxFifoEP2Empty(TxFifoEP2Empty),
319
  .TxFifoEP3Empty(TxFifoEP3Empty),
320
  .RxFifoEP0WEn(RxFifoEP0WEn),
321
  .RxFifoEP1WEn(RxFifoEP1WEn),
322
  .RxFifoEP2WEn(RxFifoEP2WEn),
323
  .RxFifoEP3WEn(RxFifoEP3WEn),
324
  .RxFifoEP0Full(RxFifoEP0Full),
325
  .RxFifoEP1Full(RxFifoEP1Full),
326
  .RxFifoEP2Full(RxFifoEP2Full),
327
  .RxFifoEP3Full(RxFifoEP3Full)
328
  );
329
 
330
wishBoneBI u_wishBoneBI (
331
  .address(address_i),
332
  .dataIn(data_i),
333
  .dataOut(data_o),
334
  .writeEn(we_i),
335
  .strobe_i(strobe_i),
336
  .ack_o(ack_o),
337
  .clk(clk_i),
338
  .rst(rstSyncToBusClk),
339
  .hostControlSel(hostControlSel),
340
  .hostRxFifoSel(hostRxFifoSel),
341
  .hostTxFifoSel(hostTxFifoSel),
342
  .slaveControlSel(slaveControlSel),
343
  .slaveEP0RxFifoSel(slaveEP0RxFifoSel),
344
  .slaveEP1RxFifoSel(slaveEP1RxFifoSel),
345
  .slaveEP2RxFifoSel(slaveEP2RxFifoSel),
346
  .slaveEP3RxFifoSel(slaveEP3RxFifoSel),
347
  .slaveEP0TxFifoSel(slaveEP0TxFifoSel),
348
  .slaveEP1TxFifoSel(slaveEP1TxFifoSel),
349
  .slaveEP2TxFifoSel(slaveEP2TxFifoSel),
350
  .slaveEP3TxFifoSel(slaveEP3TxFifoSel),
351
  .hostSlaveMuxSel(hostSlaveMuxSel),
352
  .dataFromHostControl(dataFromHostControl),
353
  .dataFromHostRxFifo(dataFromHostRxFifo),
354
  .dataFromHostTxFifo(dataFromHostTxFifo),
355
  .dataFromSlaveControl(dataFromSlaveControl),
356
  .dataFromEP0RxFifo(dataFromEP0RxFifo),
357
  .dataFromEP1RxFifo(dataFromEP1RxFifo),
358
  .dataFromEP2RxFifo(dataFromEP2RxFifo),
359
  .dataFromEP3RxFifo(dataFromEP3RxFifo),
360
  .dataFromEP0TxFifo(dataFromEP0TxFifo),
361
  .dataFromEP1TxFifo(dataFromEP1TxFifo),
362
  .dataFromEP2TxFifo(dataFromEP2TxFifo),
363
  .dataFromEP3TxFifo(dataFromEP3TxFifo),
364
  .dataFromHostSlaveMux(dataFromHostSlaveMux)
365
   );
366
 
367
hostSlaveMux u_hostSlaveMux(
368
  .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
369
  .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
370
  .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
371
  .SIEPortDataInToSIE(SIEPortDataInToSIE),
372
  .SIEPortDataInFromHost(SIEPortDataInFromHost),
373
  .SIEPortDataInFromSlave(SIEPortDataInFromSlave),
374
  .SIEPortWEnToSIE(SIEPortWEnToSIE),
375
  .SIEPortWEnFromHost(SIEPortWEnFromHost),
376
  .SIEPortWEnFromSlave(SIEPortWEnFromSlave),
377
  .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
378
  .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
379
  .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
380
  .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
381
  .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
382
  .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
383
  .noActivityTimeOutEnableToSIE(noActivityTimeOutEnableToSIE),
384
  .noActivityTimeOutEnableFromHost(noActivityTimeOutEnableFromHost),
385
  .noActivityTimeOutEnableFromSlave(noActivityTimeOutEnableFromSlave),
386
  .dataIn(data_i),
387
  .dataOut(dataFromHostSlaveMux),
388
  .address(address_i[0]),
389
  .writeEn(we_i),
390
  .strobe_i(strobe_i),
391
  .usbClk(usbClk),
392
  .busClk(clk_i),
393
  .hostSlaveMuxSel(hostSlaveMuxSel),
394
  .rstFromWire(rst_i),
395
  .rstSyncToBusClkOut(rstSyncToBusClk),
396
  .rstSyncToUsbClkOut(rstSyncToUsbClk)
397
);
398
 
399
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
400
  .clk(usbClk),
401
  .rst(rstSyncToUsbClk),
402
  .USBWireDataIn(USBWireDataIn),
403
  .USBWireDataOut(USBWireDataOut),
404
  .USBWireDataInTick(USBWireDataInTick),
405
  .USBWireDataOutTick(USBWireDataOutTick),
406
  .USBWireCtrlOut(USBWireCtrlOut),
407
  .connectState(connectState),
408
  .resumeDetected(resumeDetected),
409
  .RxCtrlOut(RxCtrlOut),
410
  .RxDataOutWEn(RxDataOutWEn),
411
  .RxDataOut(RxDataFromSIE),
412
  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
413
  .SIEPortDataIn(SIEPortDataInToSIE),
414
  .SIEPortTxRdy(SIEPortTxRdy),
415
  .SIEPortWEn(SIEPortWEnToSIE),
416
  .fullSpeedPolarity(fullSpeedPolarityToSIE),
417
  .fullSpeedBitRate(fullSpeedBitRateToSIE),
418
  .noActivityTimeOut(noActivityTimeOut),
419
  .noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
420
);
421
 
422
//---Host fifos
423
TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
424
  .usbClk(usbClk),
425
  .busClk(clk_i),
426
  .rstSyncToBusClk(rstSyncToBusClk),
427
  .rstSyncToUsbClk(rstSyncToUsbClk),
428
  .fifoREn(hostTxFifoRE),
429
  .fifoEmpty(hostTxFifoEmpty),
430
  .busAddress(address_i[2:0]),
431
  .busWriteEn(we_i),
432
  .busStrobe_i(strobe_i),
433
  .busFifoSelect(hostTxFifoSel),
434
  .busDataIn(data_i),
435
  .busDataOut(dataFromHostTxFifo),
436
  .fifoDataOut(hostTxFifoData) );
437
 
438
 
439
RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
440
  .usbClk(usbClk),
441
  .busClk(clk_i),
442
  .rstSyncToBusClk(rstSyncToBusClk),
443
  .rstSyncToUsbClk(rstSyncToUsbClk),
444
  .fifoWEn(hostRxFifoWE),
445
  .fifoFull(hostRxFifoFull),
446
  .busAddress(address_i[2:0]),
447
  .busWriteEn(we_i),
448
  .busStrobe_i(strobe_i),
449
  .busFifoSelect(hostRxFifoSel),
450
  .busDataIn(data_i),
451
  .busDataOut(dataFromHostRxFifo),
452
  .fifoDataIn(hostRxFifoData)  );
453
 
454
//---Slave fifos
455
 
456
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
457
  .usbClk(usbClk),
458
  .busClk(clk_i),
459
  .rstSyncToBusClk(rstSyncToBusClk),
460
  .rstSyncToUsbClk(rstSyncToUsbClk),
461
  .fifoREn(TxFifoEP0REn),
462
  .fifoEmpty(TxFifoEP0Empty),
463
  .busAddress(address_i[2:0]),
464
  .busWriteEn(we_i),
465
  .busStrobe_i(strobe_i),
466
  .busFifoSelect(slaveEP0TxFifoSel),
467
  .busDataIn(data_i),
468
  .busDataOut(dataFromEP0TxFifo),
469
  .fifoDataOut(TxFifoEP0Data) );
470
 
471
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
472
  .usbClk(usbClk),
473
  .busClk(clk_i),
474
  .rstSyncToBusClk(rstSyncToBusClk),
475
  .rstSyncToUsbClk(rstSyncToUsbClk),
476
  .fifoREn(TxFifoEP1REn),
477
  .fifoEmpty(TxFifoEP1Empty),
478
  .busAddress(address_i[2:0]),
479
  .busWriteEn(we_i),
480
  .busStrobe_i(strobe_i),
481
  .busFifoSelect(slaveEP1TxFifoSel),
482
  .busDataIn(data_i),
483
  .busDataOut(dataFromEP1TxFifo),
484
  .fifoDataOut(TxFifoEP1Data) );
485
 
486
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
487
  .usbClk(usbClk),
488
  .busClk(clk_i),
489
  .rstSyncToBusClk(rstSyncToBusClk),
490
  .rstSyncToUsbClk(rstSyncToUsbClk),
491
  .fifoREn(TxFifoEP2REn),
492
  .fifoEmpty(TxFifoEP2Empty),
493
  .busAddress(address_i[2:0]),
494
  .busWriteEn(we_i),
495
  .busStrobe_i(strobe_i),
496
  .busFifoSelect(slaveEP2TxFifoSel),
497
  .busDataIn(data_i),
498
  .busDataOut(dataFromEP2TxFifo),
499
  .fifoDataOut(TxFifoEP2Data) );
500
 
501
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
502
  .usbClk(usbClk),
503
  .busClk(clk_i),
504
  .rstSyncToBusClk(rstSyncToBusClk),
505
  .rstSyncToUsbClk(rstSyncToUsbClk),
506
  .fifoREn(TxFifoEP3REn),
507
  .fifoEmpty(TxFifoEP3Empty),
508
  .busAddress(address_i[2:0]),
509
  .busWriteEn(we_i),
510
  .busStrobe_i(strobe_i),
511
  .busFifoSelect(slaveEP3TxFifoSel),
512
  .busDataIn(data_i),
513
  .busDataOut(dataFromEP3TxFifo),
514
  .fifoDataOut(TxFifoEP3Data) );
515
 
516
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
517
  .usbClk(usbClk),
518
  .busClk(clk_i),
519
  .rstSyncToBusClk(rstSyncToBusClk),
520
  .rstSyncToUsbClk(rstSyncToUsbClk),
521
  .fifoWEn(RxFifoEP0WEn),
522
  .fifoFull(RxFifoEP0Full),
523
  .busAddress(address_i[2:0]),
524
  .busWriteEn(we_i),
525
  .busStrobe_i(strobe_i),
526
  .busFifoSelect(slaveEP0RxFifoSel),
527
  .busDataIn(data_i),
528
  .busDataOut(dataFromEP0RxFifo),
529
  .fifoDataIn(slaveRxFifoData)  );
530
 
531
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
532
  .usbClk(usbClk),
533
  .busClk(clk_i),
534
  .rstSyncToBusClk(rstSyncToBusClk),
535
  .rstSyncToUsbClk(rstSyncToUsbClk),
536
  .fifoWEn(RxFifoEP1WEn),
537
  .fifoFull(RxFifoEP1Full),
538
  .busAddress(address_i[2:0]),
539
  .busWriteEn(we_i),
540
  .busStrobe_i(strobe_i),
541
  .busFifoSelect(slaveEP1RxFifoSel),
542
  .busDataIn(data_i),
543
  .busDataOut(dataFromEP1RxFifo),
544
  .fifoDataIn(slaveRxFifoData)  );
545
 
546
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
547
  .usbClk(usbClk),
548
  .busClk(clk_i),
549
  .rstSyncToBusClk(rstSyncToBusClk),
550
  .rstSyncToUsbClk(rstSyncToUsbClk),
551
  .fifoWEn(RxFifoEP2WEn),
552
  .fifoFull(RxFifoEP2Full),
553
  .busAddress(address_i[2:0]),
554
  .busWriteEn(we_i),
555
  .busStrobe_i(strobe_i),
556
  .busFifoSelect(slaveEP2RxFifoSel),
557
  .busDataIn(data_i),
558
  .busDataOut(dataFromEP2RxFifo),
559
  .fifoDataIn(slaveRxFifoData)  );
560
 
561
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
562
  .usbClk(usbClk),
563
  .busClk(clk_i),
564
  .rstSyncToBusClk(rstSyncToBusClk),
565
  .rstSyncToUsbClk(rstSyncToUsbClk),
566
  .fifoWEn(RxFifoEP3WEn),
567
  .fifoFull(RxFifoEP3Full),
568
  .busAddress(address_i[2:0]),
569
  .busWriteEn(we_i),
570
  .busStrobe_i(strobe_i),
571
  .busFifoSelect(slaveEP3RxFifoSel),
572
  .busDataIn(data_i),
573
  .busDataOut(dataFromEP3RxFifo),
574
  .fifoDataIn(slaveRxFifoData)  );
575
 
576
endmodule
577
 
578
 
579
 
580
 
581
 
582
 
583
 

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