| 1 |
43 |
sfielding |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// usbSlave.v ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// This file is part of the usbhostslave opencores effort.
|
| 6 |
|
|
//// <http://www.opencores.org/cores//> ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// Module Description: ////
|
| 9 |
|
|
//// Top level module
|
| 10 |
|
|
//// ////
|
| 11 |
|
|
//// To Do: ////
|
| 12 |
|
|
////
|
| 13 |
|
|
//// ////
|
| 14 |
|
|
//// Author(s): ////
|
| 15 |
|
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
| 16 |
|
|
//// ////
|
| 17 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 18 |
|
|
//// ////
|
| 19 |
|
|
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
|
| 20 |
|
|
//// ////
|
| 21 |
|
|
//// This source file may be used and distributed without ////
|
| 22 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 23 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 24 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 25 |
|
|
//// ////
|
| 26 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 27 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 28 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 29 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 30 |
|
|
//// later version. ////
|
| 31 |
|
|
//// ////
|
| 32 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 33 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 34 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 35 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 36 |
|
|
//// details. ////
|
| 37 |
|
|
//// ////
|
| 38 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 39 |
|
|
//// Public License along with this source; if not, download it ////
|
| 40 |
|
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
| 41 |
|
|
//// ////
|
| 42 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 43 |
|
|
//
|
| 44 |
|
|
`include "timescale.v"
|
| 45 |
|
|
|
| 46 |
|
|
module usbSlave(
|
| 47 |
|
|
clk_i,
|
| 48 |
|
|
rst_i,
|
| 49 |
|
|
address_i,
|
| 50 |
|
|
data_i,
|
| 51 |
|
|
data_o,
|
| 52 |
|
|
we_i,
|
| 53 |
|
|
strobe_i,
|
| 54 |
|
|
ack_o,
|
| 55 |
|
|
usbClk,
|
| 56 |
|
|
slaveVBusDetIntOut,
|
| 57 |
|
|
slaveNAKSentIntOut,
|
| 58 |
|
|
slaveSOFRxedIntOut,
|
| 59 |
|
|
slaveResetEventIntOut,
|
| 60 |
|
|
slaveResumeIntOut,
|
| 61 |
|
|
slaveTransDoneIntOut,
|
| 62 |
|
|
USBWireDataIn,
|
| 63 |
|
|
USBWireDataInTick,
|
| 64 |
|
|
USBWireDataOut,
|
| 65 |
|
|
USBWireDataOutTick,
|
| 66 |
|
|
USBWireCtrlOut,
|
| 67 |
|
|
USBFullSpeed,
|
| 68 |
|
|
USBDPlusPullup,
|
| 69 |
|
|
USBDMinusPullup,
|
| 70 |
|
|
vBusDetect
|
| 71 |
|
|
);
|
| 72 |
|
|
parameter EP0_FIFO_DEPTH = 64;
|
| 73 |
|
|
parameter EP0_FIFO_ADDR_WIDTH = 6;
|
| 74 |
|
|
parameter EP1_FIFO_DEPTH = 64;
|
| 75 |
|
|
parameter EP1_FIFO_ADDR_WIDTH = 6;
|
| 76 |
|
|
parameter EP2_FIFO_DEPTH = 64;
|
| 77 |
|
|
parameter EP2_FIFO_ADDR_WIDTH = 6;
|
| 78 |
|
|
parameter EP3_FIFO_DEPTH = 64;
|
| 79 |
|
|
parameter EP3_FIFO_ADDR_WIDTH = 6;
|
| 80 |
|
|
|
| 81 |
|
|
input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
|
| 82 |
|
|
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
|
| 83 |
|
|
input [7:0] address_i; //Wishbone bus address in
|
| 84 |
|
|
input [7:0] data_i; //Wishbone bus data in
|
| 85 |
|
|
output [7:0] data_o; //Wishbone bus data out
|
| 86 |
|
|
input we_i; //Wishbone bus write enable in
|
| 87 |
|
|
input strobe_i; //Wishbone bus strobe in
|
| 88 |
|
|
output ack_o; //Wishbone bus acknowledge out
|
| 89 |
|
|
input usbClk; //usb clock. 48Mhz +/-0.25%
|
| 90 |
|
|
output slaveSOFRxedIntOut;
|
| 91 |
|
|
output slaveResetEventIntOut;
|
| 92 |
|
|
output slaveResumeIntOut;
|
| 93 |
|
|
output slaveTransDoneIntOut;
|
| 94 |
|
|
output slaveNAKSentIntOut;
|
| 95 |
|
|
output slaveVBusDetIntOut;
|
| 96 |
|
|
input [1:0] USBWireDataIn;
|
| 97 |
|
|
output [1:0] USBWireDataOut;
|
| 98 |
|
|
output USBWireDataOutTick;
|
| 99 |
|
|
output USBWireDataInTick;
|
| 100 |
|
|
output USBWireCtrlOut;
|
| 101 |
|
|
output USBFullSpeed;
|
| 102 |
|
|
output USBDPlusPullup;
|
| 103 |
|
|
output USBDMinusPullup;
|
| 104 |
|
|
input vBusDetect;
|
| 105 |
|
|
|
| 106 |
|
|
wire clk_i;
|
| 107 |
|
|
wire rst_i;
|
| 108 |
|
|
wire [7:0] address_i;
|
| 109 |
|
|
wire [7:0] data_i;
|
| 110 |
|
|
wire [7:0] data_o;
|
| 111 |
|
|
wire we_i;
|
| 112 |
|
|
wire strobe_i;
|
| 113 |
|
|
wire ack_o;
|
| 114 |
|
|
wire usbClk;
|
| 115 |
|
|
wire slaveSOFRxedIntOut;
|
| 116 |
|
|
wire slaveResetEventIntOut;
|
| 117 |
|
|
wire slaveResumeIntOut;
|
| 118 |
|
|
wire slaveTransDoneIntOut;
|
| 119 |
|
|
wire slaveNAKSentIntOut;
|
| 120 |
|
|
wire slaveVBusDetIntOut;
|
| 121 |
|
|
wire [1:0] USBWireDataIn;
|
| 122 |
|
|
wire [1:0] USBWireDataOut;
|
| 123 |
|
|
wire USBWireDataOutTick;
|
| 124 |
|
|
wire USBWireDataInTick;
|
| 125 |
|
|
wire USBWireCtrlOut;
|
| 126 |
|
|
wire USBFullSpeed;
|
| 127 |
|
|
wire USBDPlusPullup;
|
| 128 |
|
|
wire USBDMinusPullup;
|
| 129 |
|
|
wire vBusDetect;
|
| 130 |
|
|
|
| 131 |
|
|
//internal wiring
|
| 132 |
|
|
wire slaveControlSel;
|
| 133 |
|
|
wire hostSlaveMuxSel;
|
| 134 |
|
|
wire [7:0] dataFromSlaveControl;
|
| 135 |
|
|
wire [7:0] dataFromHostSlaveMux;
|
| 136 |
|
|
wire [7:0] RxCtrlOut;
|
| 137 |
|
|
wire [7:0] RxDataFromSIE;
|
| 138 |
|
|
wire RxDataOutWEn;
|
| 139 |
|
|
wire fullSpeedBitRateFromSlave;
|
| 140 |
|
|
wire fullSpeedPolarityFromSlave;
|
| 141 |
|
|
wire SIEPortWEnFromSlave;
|
| 142 |
|
|
wire SIEPortTxRdy;
|
| 143 |
|
|
wire [7:0] SIEPortDataInFromSlave;
|
| 144 |
|
|
wire [7:0] SIEPortCtrlInFromSlave;
|
| 145 |
|
|
wire [1:0] connectState;
|
| 146 |
|
|
wire resumeDetected;
|
| 147 |
|
|
wire [7:0] SIEPortDataInToSIE;
|
| 148 |
|
|
wire SIEPortWEnToSIE;
|
| 149 |
|
|
wire [7:0] SIEPortCtrlInToSIE;
|
| 150 |
|
|
wire fullSpeedPolarityToSIE;
|
| 151 |
|
|
wire fullSpeedBitRateToSIE;
|
| 152 |
|
|
wire connectSlaveToHost;
|
| 153 |
|
|
wire noActivityTimeOut;
|
| 154 |
|
|
wire TxFifoEP0REn;
|
| 155 |
|
|
wire TxFifoEP1REn;
|
| 156 |
|
|
wire TxFifoEP2REn;
|
| 157 |
|
|
wire TxFifoEP3REn;
|
| 158 |
|
|
wire [7:0] TxFifoEP0Data;
|
| 159 |
|
|
wire [7:0] TxFifoEP1Data;
|
| 160 |
|
|
wire [7:0] TxFifoEP2Data;
|
| 161 |
|
|
wire [7:0] TxFifoEP3Data;
|
| 162 |
|
|
wire TxFifoEP0Empty;
|
| 163 |
|
|
wire TxFifoEP1Empty;
|
| 164 |
|
|
wire TxFifoEP2Empty;
|
| 165 |
|
|
wire TxFifoEP3Empty;
|
| 166 |
|
|
wire RxFifoEP0WEn;
|
| 167 |
|
|
wire RxFifoEP1WEn;
|
| 168 |
|
|
wire RxFifoEP2WEn;
|
| 169 |
|
|
wire RxFifoEP3WEn;
|
| 170 |
|
|
wire RxFifoEP0Full;
|
| 171 |
|
|
wire RxFifoEP1Full;
|
| 172 |
|
|
wire RxFifoEP2Full;
|
| 173 |
|
|
wire RxFifoEP3Full;
|
| 174 |
|
|
wire [7:0] slaveRxFifoData;
|
| 175 |
|
|
wire [7:0] dataFromEP0RxFifo;
|
| 176 |
|
|
wire [7:0] dataFromEP1RxFifo;
|
| 177 |
|
|
wire [7:0] dataFromEP2RxFifo;
|
| 178 |
|
|
wire [7:0] dataFromEP3RxFifo;
|
| 179 |
|
|
wire [7:0] dataFromEP0TxFifo;
|
| 180 |
|
|
wire [7:0] dataFromEP1TxFifo;
|
| 181 |
|
|
wire [7:0] dataFromEP2TxFifo;
|
| 182 |
|
|
wire [7:0] dataFromEP3TxFifo;
|
| 183 |
|
|
wire slaveEP0RxFifoSel;
|
| 184 |
|
|
wire slaveEP1RxFifoSel;
|
| 185 |
|
|
wire slaveEP2RxFifoSel;
|
| 186 |
|
|
wire slaveEP3RxFifoSel;
|
| 187 |
|
|
wire slaveEP0TxFifoSel;
|
| 188 |
|
|
wire slaveEP1TxFifoSel;
|
| 189 |
|
|
wire slaveEP2TxFifoSel;
|
| 190 |
|
|
wire slaveEP3TxFifoSel;
|
| 191 |
|
|
wire rstSyncToBusClk;
|
| 192 |
|
|
wire rstSyncToUsbClk;
|
| 193 |
|
|
wire noActivityTimeOutEnableToSIE;
|
| 194 |
|
|
wire noActivityTimeOutEnableFromHost;
|
| 195 |
|
|
wire noActivityTimeOutEnableFromSlave;
|
| 196 |
|
|
|
| 197 |
|
|
// This is not a bug.
|
| 198 |
|
|
// USBFullSpeed controls the PHY edge speed.
|
| 199 |
|
|
// The only time that the PHY needs to operate with low speed edge rate is
|
| 200 |
|
|
// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
|
| 201 |
|
|
// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
|
| 202 |
|
|
// but according to spec edge speed must be full rate edge speed.
|
| 203 |
|
|
assign USBFullSpeed = fullSpeedPolarityToSIE;
|
| 204 |
|
|
//assign USBFullSpeed = fullSpeedBitRateToSIE;
|
| 205 |
|
|
assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
|
| 206 |
|
|
assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
|
| 207 |
|
|
|
| 208 |
|
|
usbSlaveControl u_usbSlaveControl(
|
| 209 |
|
|
.busClk(clk_i),
|
| 210 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 211 |
|
|
.usbClk(usbClk),
|
| 212 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 213 |
|
|
.RxByteStatus(RxCtrlOut),
|
| 214 |
|
|
.RxData(RxDataFromSIE),
|
| 215 |
|
|
.RxDataValid(RxDataOutWEn),
|
| 216 |
|
|
.SIERxTimeOut(noActivityTimeOut),
|
| 217 |
|
|
.SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
|
| 218 |
|
|
.RxFifoData(slaveRxFifoData),
|
| 219 |
|
|
.connectSlaveToHost(connectSlaveToHost),
|
| 220 |
|
|
.fullSpeedRate(fullSpeedBitRateFromSlave),
|
| 221 |
|
|
.fullSpeedPol(fullSpeedPolarityFromSlave),
|
| 222 |
|
|
.SCTxPortEn(SIEPortWEnFromSlave),
|
| 223 |
|
|
.SCTxPortRdy(SIEPortTxRdy),
|
| 224 |
|
|
.SCTxPortData(SIEPortDataInFromSlave),
|
| 225 |
|
|
.SCTxPortCtrl(SIEPortCtrlInFromSlave),
|
| 226 |
|
|
.vBusDetect(vBusDetect),
|
| 227 |
|
|
.connectStateIn(connectState),
|
| 228 |
|
|
.resumeDetectedIn(resumeDetected),
|
| 229 |
|
|
.busAddress(address_i[4:0]),
|
| 230 |
|
|
.busDataIn(data_i),
|
| 231 |
|
|
.busDataOut(dataFromSlaveControl),
|
| 232 |
|
|
.busWriteEn(we_i),
|
| 233 |
|
|
.busStrobe_i(strobe_i),
|
| 234 |
|
|
.SOFRxedIntOut(slaveSOFRxedIntOut),
|
| 235 |
|
|
.resetEventIntOut(slaveResetEventIntOut),
|
| 236 |
|
|
.resumeIntOut(slaveResumeIntOut),
|
| 237 |
|
|
.transDoneIntOut(slaveTransDoneIntOut),
|
| 238 |
|
|
.NAKSentIntOut(slaveNAKSentIntOut),
|
| 239 |
|
|
.vBusDetIntOut(slaveVBusDetIntOut),
|
| 240 |
|
|
.slaveControlSelect(slaveControlSel),
|
| 241 |
|
|
.TxFifoEP0REn(TxFifoEP0REn),
|
| 242 |
|
|
.TxFifoEP1REn(TxFifoEP1REn),
|
| 243 |
|
|
.TxFifoEP2REn(TxFifoEP2REn),
|
| 244 |
|
|
.TxFifoEP3REn(TxFifoEP3REn),
|
| 245 |
|
|
.TxFifoEP0Data(TxFifoEP0Data),
|
| 246 |
|
|
.TxFifoEP1Data(TxFifoEP1Data),
|
| 247 |
|
|
.TxFifoEP2Data(TxFifoEP2Data),
|
| 248 |
|
|
.TxFifoEP3Data(TxFifoEP3Data),
|
| 249 |
|
|
.TxFifoEP0Empty(TxFifoEP0Empty),
|
| 250 |
|
|
.TxFifoEP1Empty(TxFifoEP1Empty),
|
| 251 |
|
|
.TxFifoEP2Empty(TxFifoEP2Empty),
|
| 252 |
|
|
.TxFifoEP3Empty(TxFifoEP3Empty),
|
| 253 |
|
|
.RxFifoEP0WEn(RxFifoEP0WEn),
|
| 254 |
|
|
.RxFifoEP1WEn(RxFifoEP1WEn),
|
| 255 |
|
|
.RxFifoEP2WEn(RxFifoEP2WEn),
|
| 256 |
|
|
.RxFifoEP3WEn(RxFifoEP3WEn),
|
| 257 |
|
|
.RxFifoEP0Full(RxFifoEP0Full),
|
| 258 |
|
|
.RxFifoEP1Full(RxFifoEP1Full),
|
| 259 |
|
|
.RxFifoEP2Full(RxFifoEP2Full),
|
| 260 |
|
|
.RxFifoEP3Full(RxFifoEP3Full)
|
| 261 |
|
|
);
|
| 262 |
|
|
|
| 263 |
|
|
|
| 264 |
|
|
wishBoneBI u_wishBoneBI (
|
| 265 |
|
|
.address(address_i),
|
| 266 |
|
|
.dataIn(data_i),
|
| 267 |
|
|
.dataOut(data_o),
|
| 268 |
|
|
.writeEn(we_i),
|
| 269 |
|
|
.strobe_i(strobe_i),
|
| 270 |
|
|
.ack_o(ack_o),
|
| 271 |
|
|
.clk(clk_i),
|
| 272 |
|
|
.rst(rstSyncToBusClk),
|
| 273 |
|
|
.hostControlSel(),
|
| 274 |
|
|
.hostRxFifoSel(),
|
| 275 |
|
|
.hostTxFifoSel(),
|
| 276 |
|
|
.slaveControlSel(slaveControlSel),
|
| 277 |
|
|
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
|
| 278 |
|
|
.slaveEP1RxFifoSel(slaveEP1RxFifoSel),
|
| 279 |
|
|
.slaveEP2RxFifoSel(slaveEP2RxFifoSel),
|
| 280 |
|
|
.slaveEP3RxFifoSel(slaveEP3RxFifoSel),
|
| 281 |
|
|
.slaveEP0TxFifoSel(slaveEP0TxFifoSel),
|
| 282 |
|
|
.slaveEP1TxFifoSel(slaveEP1TxFifoSel),
|
| 283 |
|
|
.slaveEP2TxFifoSel(slaveEP2TxFifoSel),
|
| 284 |
|
|
.slaveEP3TxFifoSel(slaveEP3TxFifoSel),
|
| 285 |
|
|
.hostSlaveMuxSel(hostSlaveMuxSel),
|
| 286 |
|
|
.dataFromHostControl(8'h00),
|
| 287 |
|
|
.dataFromHostRxFifo(8'h00),
|
| 288 |
|
|
.dataFromHostTxFifo(8'h00),
|
| 289 |
|
|
.dataFromSlaveControl(dataFromSlaveControl),
|
| 290 |
|
|
.dataFromEP0RxFifo(dataFromEP0RxFifo),
|
| 291 |
|
|
.dataFromEP1RxFifo(dataFromEP1RxFifo),
|
| 292 |
|
|
.dataFromEP2RxFifo(dataFromEP2RxFifo),
|
| 293 |
|
|
.dataFromEP3RxFifo(dataFromEP3RxFifo),
|
| 294 |
|
|
.dataFromEP0TxFifo(dataFromEP0TxFifo),
|
| 295 |
|
|
.dataFromEP1TxFifo(dataFromEP1TxFifo),
|
| 296 |
|
|
.dataFromEP2TxFifo(dataFromEP2TxFifo),
|
| 297 |
|
|
.dataFromEP3TxFifo(dataFromEP3TxFifo),
|
| 298 |
|
|
.dataFromHostSlaveMux(dataFromHostSlaveMux)
|
| 299 |
|
|
);
|
| 300 |
|
|
|
| 301 |
|
|
|
| 302 |
|
|
|
| 303 |
|
|
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
|
| 304 |
|
|
assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
|
| 305 |
|
|
assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
|
| 306 |
|
|
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
|
| 307 |
|
|
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
|
| 308 |
|
|
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
|
| 309 |
|
|
|
| 310 |
|
|
hostSlaveMuxBI u_hostSlaveMuxBI (
|
| 311 |
|
|
.dataIn(data_i),
|
| 312 |
|
|
.dataOut(dataFromHostSlaveMux),
|
| 313 |
|
|
.address(address_i[0]),
|
| 314 |
|
|
.writeEn(we_i),
|
| 315 |
|
|
.strobe_i(strobe_i),
|
| 316 |
|
|
.usbClk(usbClk),
|
| 317 |
|
|
.busClk(clk_i),
|
| 318 |
|
|
.hostSlaveMuxSel(hostSlaveMuxSel),
|
| 319 |
|
|
.hostMode(),
|
| 320 |
|
|
.rstFromWire(rst_i),
|
| 321 |
|
|
.rstSyncToBusClkOut(rstSyncToBusClk),
|
| 322 |
|
|
.rstSyncToUsbClkOut(rstSyncToUsbClk)
|
| 323 |
|
|
);
|
| 324 |
|
|
|
| 325 |
|
|
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
|
| 326 |
|
|
.clk(usbClk),
|
| 327 |
|
|
.rst(rstSyncToUsbClk),
|
| 328 |
|
|
.USBWireDataIn(USBWireDataIn),
|
| 329 |
|
|
.USBWireDataOut(USBWireDataOut),
|
| 330 |
|
|
.USBWireDataInTick(USBWireDataInTick),
|
| 331 |
|
|
.USBWireDataOutTick(USBWireDataOutTick),
|
| 332 |
|
|
.USBWireCtrlOut(USBWireCtrlOut),
|
| 333 |
|
|
.connectState(connectState),
|
| 334 |
|
|
.resumeDetected(resumeDetected),
|
| 335 |
|
|
.RxCtrlOut(RxCtrlOut),
|
| 336 |
|
|
.RxDataOutWEn(RxDataOutWEn),
|
| 337 |
|
|
.RxDataOut(RxDataFromSIE),
|
| 338 |
|
|
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
|
| 339 |
|
|
.SIEPortDataIn(SIEPortDataInToSIE),
|
| 340 |
|
|
.SIEPortTxRdy(SIEPortTxRdy),
|
| 341 |
|
|
.SIEPortWEn(SIEPortWEnToSIE),
|
| 342 |
|
|
.fullSpeedPolarity(fullSpeedPolarityToSIE),
|
| 343 |
|
|
.fullSpeedBitRate(fullSpeedBitRateToSIE),
|
| 344 |
|
|
.noActivityTimeOut(noActivityTimeOut),
|
| 345 |
|
|
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
|
| 346 |
|
|
);
|
| 347 |
|
|
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
//---Slave fifos
|
| 351 |
|
|
|
| 352 |
|
|
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
|
| 353 |
|
|
.usbClk(usbClk),
|
| 354 |
|
|
.busClk(clk_i),
|
| 355 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 356 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 357 |
|
|
.fifoREn(TxFifoEP0REn),
|
| 358 |
|
|
.fifoEmpty(TxFifoEP0Empty),
|
| 359 |
|
|
.busAddress(address_i[2:0]),
|
| 360 |
|
|
.busWriteEn(we_i),
|
| 361 |
|
|
.busStrobe_i(strobe_i),
|
| 362 |
|
|
.busFifoSelect(slaveEP0TxFifoSel),
|
| 363 |
|
|
.busDataIn(data_i),
|
| 364 |
|
|
.busDataOut(dataFromEP0TxFifo),
|
| 365 |
|
|
.fifoDataOut(TxFifoEP0Data) );
|
| 366 |
|
|
|
| 367 |
|
|
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
|
| 368 |
|
|
.usbClk(usbClk),
|
| 369 |
|
|
.busClk(clk_i),
|
| 370 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 371 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 372 |
|
|
.fifoREn(TxFifoEP1REn),
|
| 373 |
|
|
.fifoEmpty(TxFifoEP1Empty),
|
| 374 |
|
|
.busAddress(address_i[2:0]),
|
| 375 |
|
|
.busWriteEn(we_i),
|
| 376 |
|
|
.busStrobe_i(strobe_i),
|
| 377 |
|
|
.busFifoSelect(slaveEP1TxFifoSel),
|
| 378 |
|
|
.busDataIn(data_i),
|
| 379 |
|
|
.busDataOut(dataFromEP1TxFifo),
|
| 380 |
|
|
.fifoDataOut(TxFifoEP1Data) );
|
| 381 |
|
|
|
| 382 |
|
|
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
|
| 383 |
|
|
.usbClk(usbClk),
|
| 384 |
|
|
.busClk(clk_i),
|
| 385 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 386 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 387 |
|
|
.fifoREn(TxFifoEP2REn),
|
| 388 |
|
|
.fifoEmpty(TxFifoEP2Empty),
|
| 389 |
|
|
.busAddress(address_i[2:0]),
|
| 390 |
|
|
.busWriteEn(we_i),
|
| 391 |
|
|
.busStrobe_i(strobe_i),
|
| 392 |
|
|
.busFifoSelect(slaveEP2TxFifoSel),
|
| 393 |
|
|
.busDataIn(data_i),
|
| 394 |
|
|
.busDataOut(dataFromEP2TxFifo),
|
| 395 |
|
|
.fifoDataOut(TxFifoEP2Data) );
|
| 396 |
|
|
|
| 397 |
|
|
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
|
| 398 |
|
|
.usbClk(usbClk),
|
| 399 |
|
|
.busClk(clk_i),
|
| 400 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 401 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 402 |
|
|
.fifoREn(TxFifoEP3REn),
|
| 403 |
|
|
.fifoEmpty(TxFifoEP3Empty),
|
| 404 |
|
|
.busAddress(address_i[2:0]),
|
| 405 |
|
|
.busWriteEn(we_i),
|
| 406 |
|
|
.busStrobe_i(strobe_i),
|
| 407 |
|
|
.busFifoSelect(slaveEP3TxFifoSel),
|
| 408 |
|
|
.busDataIn(data_i),
|
| 409 |
|
|
.busDataOut(dataFromEP3TxFifo),
|
| 410 |
|
|
.fifoDataOut(TxFifoEP3Data) );
|
| 411 |
|
|
|
| 412 |
|
|
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
|
| 413 |
|
|
.usbClk(usbClk),
|
| 414 |
|
|
.busClk(clk_i),
|
| 415 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 416 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 417 |
|
|
.fifoWEn(RxFifoEP0WEn),
|
| 418 |
|
|
.fifoFull(RxFifoEP0Full),
|
| 419 |
|
|
.busAddress(address_i[2:0]),
|
| 420 |
|
|
.busWriteEn(we_i),
|
| 421 |
|
|
.busStrobe_i(strobe_i),
|
| 422 |
|
|
.busFifoSelect(slaveEP0RxFifoSel),
|
| 423 |
|
|
.busDataIn(data_i),
|
| 424 |
|
|
.busDataOut(dataFromEP0RxFifo),
|
| 425 |
|
|
.fifoDataIn(slaveRxFifoData) );
|
| 426 |
|
|
|
| 427 |
|
|
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
|
| 428 |
|
|
.usbClk(usbClk),
|
| 429 |
|
|
.busClk(clk_i),
|
| 430 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 431 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 432 |
|
|
.fifoWEn(RxFifoEP1WEn),
|
| 433 |
|
|
.fifoFull(RxFifoEP1Full),
|
| 434 |
|
|
.busAddress(address_i[2:0]),
|
| 435 |
|
|
.busWriteEn(we_i),
|
| 436 |
|
|
.busStrobe_i(strobe_i),
|
| 437 |
|
|
.busFifoSelect(slaveEP1RxFifoSel),
|
| 438 |
|
|
.busDataIn(data_i),
|
| 439 |
|
|
.busDataOut(dataFromEP1RxFifo),
|
| 440 |
|
|
.fifoDataIn(slaveRxFifoData) );
|
| 441 |
|
|
|
| 442 |
|
|
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
|
| 443 |
|
|
.usbClk(usbClk),
|
| 444 |
|
|
.busClk(clk_i),
|
| 445 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 446 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 447 |
|
|
.fifoWEn(RxFifoEP2WEn),
|
| 448 |
|
|
.fifoFull(RxFifoEP2Full),
|
| 449 |
|
|
.busAddress(address_i[2:0]),
|
| 450 |
|
|
.busWriteEn(we_i),
|
| 451 |
|
|
.busStrobe_i(strobe_i),
|
| 452 |
|
|
.busFifoSelect(slaveEP2RxFifoSel),
|
| 453 |
|
|
.busDataIn(data_i),
|
| 454 |
|
|
.busDataOut(dataFromEP2RxFifo),
|
| 455 |
|
|
.fifoDataIn(slaveRxFifoData) );
|
| 456 |
|
|
|
| 457 |
|
|
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
|
| 458 |
|
|
.usbClk(usbClk),
|
| 459 |
|
|
.busClk(clk_i),
|
| 460 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 461 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 462 |
|
|
.fifoWEn(RxFifoEP3WEn),
|
| 463 |
|
|
.fifoFull(RxFifoEP3Full),
|
| 464 |
|
|
.busAddress(address_i[2:0]),
|
| 465 |
|
|
.busWriteEn(we_i),
|
| 466 |
|
|
.busStrobe_i(strobe_i),
|
| 467 |
|
|
.busFifoSelect(slaveEP3RxFifoSel),
|
| 468 |
|
|
.busDataIn(data_i),
|
| 469 |
|
|
.busDataOut(dataFromEP3RxFifo),
|
| 470 |
|
|
.fifoDataIn(slaveRxFifoData) );
|
| 471 |
|
|
|
| 472 |
|
|
|
| 473 |
|
|
|
| 474 |
|
|
endmodule
|
| 475 |
|
|
|
| 476 |
|
|
|
| 477 |
|
|
|
| 478 |
|
|
|
| 479 |
|
|
|
| 480 |
|
|
|
| 481 |
|
|
|
