URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [bench/] [testCase0.v] - Blame information for rev 43

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// ---------------------------------- testcase0.v ----------------------------
`include "timescale.v"
`include "usbHostSlave_h.v"
`include "usbHostControl_h.v"
`include "usbHostSlaveTB_defines.v"
 
module testCase0();
 
reg ack;
reg [7:0] data;
reg [15:0] dataWord;
reg [7:0] dataRead;
reg [7:0] dataWrite;
reg [7:0] USBAddress;
reg [7:0] USBEndPoint;
reg [7:0] transType;
integer dataSize;
integer i;
integer j;
 
initial
begin
  $write("\n\n");
  #1000;
 
  testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
  $display("Host Version number = 0x%0x\n", dataRead);
  testHarness.u_wb_master_model.wb_read(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
  $display("Slave Version number = 0x%0x\n", dataRead);
 
  $write("Testing host register read/write  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
  $write("--- PASSED\n");
  $write("Testing slave register read/write  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
  $write("--- PASSED\n");
 
  $write("Testing register reset  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
  #1000;
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h00);
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h00);
  $write("--- PASSED\n");
  #1000;
 
  $write("Configure host and slave mode.  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h1);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h0);
 
  $write("Connect full speed  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
  #20000;
  //expecting connection event interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
  //expecting full speed connect
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 6'h02);
  //expecting change in reset state event, and change in vbus state event
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h24);
  //expecting full speed connect and vbus present
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
  $write("--- PASSED\n");
 
  $write("Cancel interrupts  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h24);
  //expecting all interrupts cancelled
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
  //expecting all interrupts cancelled
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
  $write("--- PASSED\n");
  #1000;
 
  $write("Disconnect  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h30);
  #10000;
  //expecting connection event interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
  //expecting disconnect state
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h00);
  //expecting change in reset state event
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
  //expecting vbus present, and disconnect state
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h04);
  //cancel interrupts
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
  $write("--- PASSED\n");
 
 
  $write("Connect full speed  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
  #20000;
  //expecting connection event interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
  //expecting full speed connect
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
  //expecting change in reset state event
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
  //expecting full speed connect and vbus present
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
  //cancel interrupts
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
  $write("--- PASSED\n");
  #1000;
 
 
  $write("Host forcing reset  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h1c);
  #20000;
  //expecting change in reset state event
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
  //expecting vbus present, and disconnect state
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h04);
  //cancel interrupt
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
  $write("--- PASSED\n");
 
  $write("Connect full speed  ");
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
  #20000;
  //expecting no host interrupts
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
  //expecting full speed connect
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
  //expecting change in reset state event
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
  //expecting full speed connect and vbus present
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
  //cancel interrupts
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
  $write("--- PASSED\n");
  #1000;
 
  $write("Trans test: Device address = 0x00, 2 byte SETUP transaction to Endpoint 0. ");
  USBAddress = 8'h00;
  USBEndPoint = 8'h00;
  transType = `SETUP_TRANS;
  dataSize = 2;
  //enable endpoint, and make ready
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP0_CTRL_REG , 8'h03);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
  data = 8'h00;
  for (i=0; i<dataSize; i=i+1) begin
    testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
    data = data + 1'b1;
  end
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
  #20000
  //expecting transaction done interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
  //expecting transaction done interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
  //endpoint enabled, and endpoint ready cleared
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP0_CTRL_REG , 8'h01);
  $write("Checking receive data  ");
  data = 8'h00;
  for (i=0; i<dataSize; i=i+1) begin
    testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP0_RX_FIFO_BASE + `FIFO_DATA_REG , data);
    data = data + 1'b1;
  end
  $write("--- PASSED\n");
 
  $write("Trans test: Device address = 0x5a, 20 byte OUT DATA0 transaction to Endpoint 1. ");
  USBAddress = 8'h5a;
  USBEndPoint = 8'h01;
  transType = `OUTDATA0_TRANS;
  dataSize = 20;
  //enable endpoint, and make ready
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP1_CTRL_REG , 8'h03);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
  data = 8'h00;
  for (i=0; i<dataSize; i=i+1) begin
    testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
    data = data + 1'b1;
  end
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
  #20000
  //expecting transaction done interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
  //expecting transaction done interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
  //endpoint enabled, and endpoint ready cleared
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP1_CTRL_REG , 8'h01);
  $write("Checking receive data  ");
  data = 8'h00;
  for (i=0; i<dataSize; i=i+1) begin
    testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP1_RX_FIFO_BASE + `FIFO_DATA_REG , data);
    data = data + 1'b1;
  end
  $write("--- PASSED\n");
 
  $write("Trans test: Device address = 0x01, 2 byte IN transaction to Endpoint 2. ");
  USBAddress = 8'h01;
  USBEndPoint = 8'h02;
  transType = `IN_TRANS;
  dataSize = 2;
  //enable endpoint, and make ready
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP2_CTRL_REG , 8'h03);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
  data = 8'h00;
  for (i=0; i<dataSize; i=i+1) begin
    testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `EP2_TX_FIFO_BASE + `FIFO_DATA_REG , data);
    data = data + 1'b1;
  end
  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
  #20000
  //expecting transaction done interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
  //expecting transaction done interrupt
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
  //endpoint enabled, and endpoint ready cleared
  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP2_CTRL_REG , 8'h01);
  $write("Checking receive data  ");
  data = 8'h00;
  for (i=0; i<dataSize; i=i+1) begin
    testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , data);
    data = data + 1'b1;
  end
  $write("--- PASSED\n");
 
  $write("Finished all tests\n");
  $stop;
 
end
 
endmodule
 

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [bench/] [testCase0.v] - Blame information for rev 43

Line No.	Rev	Author	Line
1	37	sfielding	`// ---------------------------------- testcase0.v ----------------------------`
2			`include "timescale.v"
3			`include "usbHostSlave_h.v"
4			`include "usbHostControl_h.v"
5			`include "usbHostSlaveTB_defines.v"
6
7			`module testCase0();`
8
9			`reg ack;`
10			`reg [7:0] data;`
11			`reg [15:0] dataWord;`
12			`reg [7:0] dataRead;`
13			`reg [7:0] dataWrite;`
14			`reg [7:0] USBAddress;`
15			`reg [7:0] USBEndPoint;`
16			`reg [7:0] transType;`
17			`integer dataSize;`
18			`integer i;`
19			`integer j;`
20
21			`initial`
22			`begin`
23			`$write("\n\n");`
24			`#1000;`
25
26			testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
27			`$display("Host Version number = 0x%0x\n", dataRead);`
28			testHarness.u_wb_master_model.wb_read(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
29			`$display("Slave Version number = 0x%0x\n", dataRead);`
30
31			`$write("Testing host register read/write ");`
32			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
33			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
34			`$write("--- PASSED\n");`
35			`$write("Testing slave register read/write ");`
36			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
37			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
38			`$write("--- PASSED\n");`
39
40			`$write("Testing register reset ");`
41			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
42			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
43			`#1000;`
44			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h00);
45			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h00);
46			`$write("--- PASSED\n");`
47			`#1000;`
48
49			`$write("Configure host and slave mode. ");`
50			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h1);
51			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h0);
52
53			`$write("Connect full speed ");`
54			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
55			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
56			`#20000;`
57			`//expecting connection event interrupt`
58			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
59			`//expecting full speed connect`
60			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 6'h02);
61			`//expecting change in reset state event, and change in vbus state event`
62			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h24);
63			`//expecting full speed connect and vbus present`
64			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
65			`$write("--- PASSED\n");`
66
67			`$write("Cancel interrupts ");`
68			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
69			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h24);
70			`//expecting all interrupts cancelled`
71			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
72			`//expecting all interrupts cancelled`
73			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
74			`$write("--- PASSED\n");`
75			`#1000;`
76
77			`$write("Disconnect ");`
78			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
79			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h30);
80			`#10000;`
81			`//expecting connection event interrupt`
82			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
83			`//expecting disconnect state`
84			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h00);
85			`//expecting change in reset state event`
86			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
87			`//expecting vbus present, and disconnect state`
88			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h04);
89			`//cancel interrupts`
90			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
91			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
92			`$write("--- PASSED\n");`
93
94
95			`$write("Connect full speed ");`
96			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
97			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
98			`#20000;`
99			`//expecting connection event interrupt`
100			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
101			`//expecting full speed connect`
102			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
103			`//expecting change in reset state event`
104			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
105			`//expecting full speed connect and vbus present`
106			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
107			`//cancel interrupts`
108			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
109			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
110			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
111			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
112			`$write("--- PASSED\n");`
113			`#1000;`
114
115
116			`$write("Host forcing reset ");`
117			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h1c);
118			`#20000;`
119			`//expecting change in reset state event`
120			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
121			`//expecting vbus present, and disconnect state`
122			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h04);
123			`//cancel interrupt`
124			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
125			`$write("--- PASSED\n");`
126
127			`$write("Connect full speed ");`
128			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
129			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
130			`#20000;`
131			`//expecting no host interrupts`
132			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
133			`//expecting full speed connect`
134			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
135			`//expecting change in reset state event`
136			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
137			`//expecting full speed connect and vbus present`
138			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
139			`//cancel interrupts`
140			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
141			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
142			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
143			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
144			`$write("--- PASSED\n");`
145			`#1000;`
146
147			`$write("Trans test: Device address = 0x00, 2 byte SETUP transaction to Endpoint 0. ");`
148			`USBAddress = 8'h00;`
149			`USBEndPoint = 8'h00;`
150			transType = `SETUP_TRANS;
151			`dataSize = 2;`
152			`//enable endpoint, and make ready`
153			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
154			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
155			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP0_CTRL_REG , 8'h03);
156			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
157			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
158			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
159			`data = 8'h00;`
160			`for (i=0; i<dataSize; i=i+1) begin`
161			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
162			`data = data + 1'b1;`
163			`end`
164			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
165			`#20000`
166			`//expecting transaction done interrupt`
167			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
168			`//expecting transaction done interrupt`
169			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
170			`//endpoint enabled, and endpoint ready cleared`
171			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP0_CTRL_REG , 8'h01);
172			`$write("Checking receive data ");`
173			`data = 8'h00;`
174			`for (i=0; i<dataSize; i=i+1) begin`
175			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP0_RX_FIFO_BASE + `FIFO_DATA_REG , data);
176			`data = data + 1'b1;`
177			`end`
178			`$write("--- PASSED\n");`
179
180			`$write("Trans test: Device address = 0x5a, 20 byte OUT DATA0 transaction to Endpoint 1. ");`
181			`USBAddress = 8'h5a;`
182			`USBEndPoint = 8'h01;`
183			transType = `OUTDATA0_TRANS;
184			`dataSize = 20;`
185			`//enable endpoint, and make ready`
186			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
187			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
188			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP1_CTRL_REG , 8'h03);
189			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
190			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
191			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
192			`data = 8'h00;`
193			`for (i=0; i<dataSize; i=i+1) begin`
194			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
195			`data = data + 1'b1;`
196			`end`
197			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
198			`#20000`
199			`//expecting transaction done interrupt`
200			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
201			`//expecting transaction done interrupt`
202			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
203			`//endpoint enabled, and endpoint ready cleared`
204			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP1_CTRL_REG , 8'h01);
205			`$write("Checking receive data ");`
206			`data = 8'h00;`
207			`for (i=0; i<dataSize; i=i+1) begin`
208			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP1_RX_FIFO_BASE + `FIFO_DATA_REG , data);
209			`data = data + 1'b1;`
210			`end`
211			`$write("--- PASSED\n");`
212
213			`$write("Trans test: Device address = 0x01, 2 byte IN transaction to Endpoint 2. ");`
214			`USBAddress = 8'h01;`
215			`USBEndPoint = 8'h02;`
216			transType = `IN_TRANS;
217			`dataSize = 2;`
218			`//enable endpoint, and make ready`
219			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
220			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
221			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP2_CTRL_REG , 8'h03);
222			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
223			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
224			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
225			`data = 8'h00;`
226			`for (i=0; i<dataSize; i=i+1) begin`
227			testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `EP2_TX_FIFO_BASE + `FIFO_DATA_REG , data);
228			`data = data + 1'b1;`
229			`end`
230			testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
231			`#20000`
232			`//expecting transaction done interrupt`
233			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
234			`//expecting transaction done interrupt`
235			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
236			`//endpoint enabled, and endpoint ready cleared`
237			testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP2_CTRL_REG , 8'h01);
238			`$write("Checking receive data ");`
239			`data = 8'h00;`
240			`for (i=0; i<dataSize; i=i+1) begin`
241			testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , data);
242			`data = data + 1'b1;`
243			`end`
244			`$write("--- PASSED\n");`
245
246			`$write("Finished all tests\n");`
247			`$stop;`
248
249			`end`
250
251			`endmodule`
252