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sfielding |
# Copyright (C) 1991-2006 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# usbHostSlaveAvalonWrap_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name FAMILY Cyclone
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set_global_assignment -name DEVICE EP1C4F400C7
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set_global_assignment -name TOP_LEVEL_ENTITY usbHostSlaveAvalonWrap
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:38:48 OCTOBER 06, 2006"
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set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
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set_global_assignment -name VERILOG_FILE src/writeUSBWireData.v
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set_global_assignment -name VERILOG_FILE src/directcontrol.v
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set_global_assignment -name VERILOG_FILE src/dpMem_dc.v
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set_global_assignment -name VERILOG_FILE src/endpMux.v
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set_global_assignment -name VERILOG_FILE src/fifoMux.v
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set_global_assignment -name VERILOG_FILE src/fifoRTL.v
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set_global_assignment -name VERILOG_FILE src/getpacket.v
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set_global_assignment -name VERILOG_FILE src/hctxportarbiter.v
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set_global_assignment -name VERILOG_FILE src/hostcontroller.v
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set_global_assignment -name VERILOG_FILE src/hostSlaveMux.v
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set_global_assignment -name VERILOG_FILE src/hostSlaveMuxBI.v
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set_global_assignment -name VERILOG_FILE src/lineControlUpdate.v
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set_global_assignment -name VERILOG_FILE src/processRxBit.v
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set_global_assignment -name VERILOG_FILE src/processRxByte.v
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set_global_assignment -name VERILOG_FILE src/processTxByte.v
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set_global_assignment -name VERILOG_FILE src/readUSBWireData.v
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set_global_assignment -name VERILOG_FILE src/RxFifo.v
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set_global_assignment -name VERILOG_FILE src/RxFifoBI.v
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set_global_assignment -name VERILOG_FILE src/rxStatusMonitor.v
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set_global_assignment -name VERILOG_FILE src/sctxportarbiter.v
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set_global_assignment -name VERILOG_FILE src/sendpacket.v
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set_global_assignment -name VERILOG_FILE src/sendpacketarbiter.v
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set_global_assignment -name VERILOG_FILE src/sendpacketcheckpreamble.v
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set_global_assignment -name VERILOG_FILE src/siereceiver.v
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set_global_assignment -name VERILOG_FILE src/SIETransmitter.v
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set_global_assignment -name VERILOG_FILE src/slavecontroller.v
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set_global_assignment -name VERILOG_FILE src/slaveDirectcontrol.v
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set_global_assignment -name VERILOG_FILE src/slaveGetpacket.v
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set_global_assignment -name VERILOG_FILE src/slaveRxStatusMonitor.v
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set_global_assignment -name VERILOG_FILE src/slaveSendpacket.v
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set_global_assignment -name VERILOG_FILE src/sofcontroller.v
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set_global_assignment -name VERILOG_FILE src/softransmit.v
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set_global_assignment -name VERILOG_FILE src/speedCtrlMux.v
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set_global_assignment -name VERILOG_FILE src/timescale.v
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set_global_assignment -name VERILOG_FILE src/TxFifo.v
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set_global_assignment -name VERILOG_FILE src/TxFifoBI.v
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set_global_assignment -name VERILOG_FILE src/updateCRC5.v
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set_global_assignment -name VERILOG_FILE src/updateCRC16.v
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set_global_assignment -name VERILOG_FILE src/usbConstants_h.v
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set_global_assignment -name VERILOG_FILE src/usbHostControl.v
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set_global_assignment -name VERILOG_FILE src/usbHostControl_h.v
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set_global_assignment -name VERILOG_FILE src/USBHostControlBI.v
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set_global_assignment -name VERILOG_FILE src/usbHostSlave.v
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set_global_assignment -name VERILOG_FILE src/usbHostSlave_h.v
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set_global_assignment -name VERILOG_FILE src/usbHostSlaveAvalonWrap.v
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set_global_assignment -name VERILOG_FILE src/usbSerialInterfaceEngine.v
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set_global_assignment -name VERILOG_FILE src/usbSerialInterfaceEngine_h.v
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set_global_assignment -name VERILOG_FILE src/usbSlaveControl.v
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set_global_assignment -name VERILOG_FILE src/usbSlaveControl_h.v
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set_global_assignment -name VERILOG_FILE src/USBSlaveControlBI.v
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set_global_assignment -name VERILOG_FILE src/usbTxWireArbiter.v
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set_global_assignment -name VERILOG_FILE src/wishBoneBI.v
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set_global_assignment -name VERILOG_FILE src/wishBoneBus_h.v
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