URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [syn/] [Altera/] [sopcCompProj/] [usbhostslaveavalonwrap/] [class.ptf] - Blame information for rev 43

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#
# This class.ptf file built by Component Editor
# 2006.10.11.20:54:36
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
# the very best results, just relax and
# DO NOT MODIFY THIS FILE
#
CLASS usbhostslaveavalonwrap
{
   CB_GENERATOR
   {
      HDL_FILES
      {
         FILE
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "verilog";
            filepath = "hdl/usbHostSlaveAvalonWrap.v";
         }
      }
      top_module_name = "usbHostSlaveAvalonWrap.v:usbHostSlaveAvalonWrap";
      emit_system_h = "0";
      LIBRARIES
      {
      }
   }
   MODULE_DEFAULTS global_signals
   {
      class = "usbhostslaveavalonwrap";
      class_version = "1.0";
      SYSTEM_BUILDER_INFO
      {
         Instantiate_In_System_Module = "1";
         Has_Clock = "1";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      COMPONENT_BUILDER
      {
         GLS_SETTINGS
         {
         }
      }
      PORT_WIRING
      {
         PORT clk
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "clk";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT reset
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "reset";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT usbClk
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS
      {
         hdl_parameters
         {
         }
      }
      SIMULATION
      {
         DISPLAY
         {
         }
      }
      SLAVE avalon_slave_0
      {
         SYSTEM_BUILDER_INFO
         {
            Bus_Type = "avalon";
            Address_Group = "1";
            Has_Clock = "0";
            Address_Width = "8";
            Address_Alignment = "native";
            Data_Width = "8";
            Has_Base_Address = "1";
            Has_IRQ = "1";
            Setup_Time = "0";
            Hold_Time = "0";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Read_Latency = "0";
            Maximum_Pending_Read_Transactions = "0";
            Active_CS_Through_Read_Latency = "0";
            Is_Printable_Device = "0";
            Is_Memory_Device = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            Minimum_Uninterrupted_Run_Length = "1";
         }
         COMPONENT_BUILDER
         {
            AVS_SETTINGS
            {
               Setup_Value = "0";
               Read_Wait_Value = "1";
               Write_Wait_Value = "1";
               Hold_Value = "0";
               Timing_Units = "cycles";
               Read_Latency_Value = "0";
               Minimum_Arbitration_Shares = "1";
               Active_CS_Through_Read_Latency = "0";
               Max_Pending_Read_Transactions_Value = "1";
               Address_Alignment = "native";
               Is_Printable_Device = "0";
               Interleave_Bursts = "0";
               interface_name = "Avalon Slave";
               external_wait = "1";
               Is_Memory_Device = "0";
            }
         }
         PORT_WIRING
         {
            PORT address
            {
               width = "8";
               width_expression = "";
               direction = "input";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT writedata
            {
               width = "8";
               width_expression = "";
               direction = "input";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT readdata
            {
               width = "8";
               width_expression = "";
               direction = "output";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT write
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "write";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT read
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "read";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT waitrequest
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "waitrequest";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT chipselect
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "chipselect";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT irq
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "irq";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT USBWireVPI
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT USBWireVMI
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT USBWireDataInTick
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT USBWireVPO
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT USBWireVMO
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT USBWireDataOutTick
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT USBWireOutEn_n
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT USBFullSpeed
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
   }
   USER_INTERFACE
   {
      USER_LABELS
      {
         name = "usbHostSlaveAvalonWrap";
         technology = "user logic";
      }
      WIZARD_UI the_wizard_ui
      {
         title = "usbHostSlaveAvalonWrap - {{ $MOD }}";
         CONTEXT
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "usbHostSlaveAvalonWrap 1.0 Settings";
               layout = "vertical";
               TEXT
               {
                  title = "Built on: 2006.10.11.20:54:36";
               }
               TEXT
               {
                  title = "Class name: usbhostslaveavalonwrap";
               }
               TEXT
               {
                  title = "Class version: 1.0";
               }
               TEXT
               {
                  title = "Component name: usbHostSlaveAvalonWrap";
               }
               TEXT
               {
                  title = "Component Group: user logic";
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "6.00";
   COMPONENT_BUILDER
   {
      HDL_PARAMETERS
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
      }
      SW_FILES
      {
      }
      built_on = "2006.10.11.20:54:36";
      CACHED_HDL_INFO
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE usbHostSlaveAvalonWrap.v
         {
            file_mod = "Fri Oct 06 19:53:44 PDT 2006";
            quartus_map_start = "Sat Oct 07 21:44:02 PDT 2006";
            quartus_map_finished = "Sat Oct 07 21:44:11 PDT 2006";
            #found 1 valid modules
            WRAPPER usbHostSlaveAvalonWrap
            {
               CLASS usbHostSlaveAvalonWrap
               {
                  CB_GENERATOR
                  {
                     HDL_FILES
                     {
                        FILE
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "C:/projects/usbhostslaveCVS/usbhostslave/syn/Altera/sopcCompProj/atom_netlists/usbHostSlaveAvalonWrap.v";
                        }
                     }
                     top_module_name = "usbHostSlaveAvalonWrap";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "usbHostSlaveAvalonWrap";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING
                        {
                           PORT address
                           {
                              width = "8";
                              width_expression = "";
                              direction = "input";
                              type = "address";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT writedata
                           {
                              width = "8";
                              width_expression = "";
                              direction = "input";
                              type = "writedata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT readdata
                           {
                              width = "8";
                              width_expression = "";
                              direction = "output";
                              type = "readdata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT write
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "write";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT read
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "read";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT waitrequest
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "waitrequest";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT chipselect
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "chipselect";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT irq
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "irq";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT usbClk
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT USBWireVPI
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT USBWireVMI
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT USBWireDataInTick
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT USBWireVPO
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT USBWireVMO
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT USBWireDataOutTick
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT USBWireOutEn_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT USBFullSpeed
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     PORT_WIRING
                     {
                        PORT clk
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "clk";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                        PORT reset
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "reset";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                     }
                  }
                  USER_INTERFACE
                  {
                     USER_LABELS
                     {
                        name = "usbHostSlaveAvalonWrap";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
               }
            }
         }
      }
   }
   ASSOCIATED_FILES
   {
      Add_Program = "the_wizard_ui";
      Edit_Program = "the_wizard_ui";
      Generator_Program = "cb_generator.pl";
   }
}

Line No.	Rev	Author	Line
1	25	sfielding	`#`
2			`# This class.ptf file built by Component Editor`
3			`# 2006.10.11.20:54:36`
4			`#`
5			`# DO NOT MODIFY THIS FILE`
6			`# If you hand-modify this file you will likely`
7			`# interfere with Component Editor's ability to`
8			`# read and edit it. And then Component Editor`
9			`# will overwrite your changes anyway. So, for`
10			`# the very best results, just relax and`
11			`# DO NOT MODIFY THIS FILE`
12			`#`
13			`CLASS usbhostslaveavalonwrap`
14			`{`
15			`CB_GENERATOR`
16			`{`
17			`HDL_FILES`
18			`{`
19			`FILE`
20			`{`
21			`use_in_simulation = "1";`
22			`use_in_synthesis = "1";`
23			`type = "verilog";`
24			`filepath = "hdl/usbHostSlaveAvalonWrap.v";`
25			`}`
26			`}`
27			`top_module_name = "usbHostSlaveAvalonWrap.v:usbHostSlaveAvalonWrap";`
28			`emit_system_h = "0";`
29			`LIBRARIES`
30			`{`
31			`}`
32			`}`
33			`MODULE_DEFAULTS global_signals`
34			`{`
35			`class = "usbhostslaveavalonwrap";`
36			`class_version = "1.0";`
37			`SYSTEM_BUILDER_INFO`
38			`{`
39			`Instantiate_In_System_Module = "1";`
40			`Has_Clock = "1";`
41			`Top_Level_Ports_Are_Enumerated = "1";`
42			`}`
43			`COMPONENT_BUILDER`
44			`{`
45			`GLS_SETTINGS`
46			`{`
47			`}`
48			`}`
49			`PORT_WIRING`
50			`{`
51			`PORT clk`
52			`{`
53			`width = "1";`
54			`width_expression = "";`
55			`direction = "input";`
56			`type = "clk";`
57			`is_shared = "0";`
58			`vhdl_record_name = "";`
59			`vhdl_record_type = "";`
60			`}`
61			`PORT reset`
62			`{`
63			`width = "1";`
64			`width_expression = "";`
65			`direction = "input";`
66			`type = "reset";`
67			`is_shared = "0";`
68			`vhdl_record_name = "";`
69			`vhdl_record_type = "";`
70			`}`
71			`PORT usbClk`
72			`{`
73			`width = "1";`
74			`width_expression = "";`
75			`direction = "input";`
76			`type = "export";`
77			`is_shared = "0";`
78			`vhdl_record_name = "";`
79			`vhdl_record_type = "";`
80			`}`
81			`}`
82			`WIZARD_SCRIPT_ARGUMENTS`
83			`{`
84			`hdl_parameters`
85			`{`
86			`}`
87			`}`
88			`SIMULATION`
89			`{`
90			`DISPLAY`
91			`{`
92			`}`
93			`}`
94			`SLAVE avalon_slave_0`
95			`{`
96			`SYSTEM_BUILDER_INFO`
97			`{`
98			`Bus_Type = "avalon";`
99			`Address_Group = "1";`
100			`Has_Clock = "0";`
101			`Address_Width = "8";`
102			`Address_Alignment = "native";`
103			`Data_Width = "8";`
104			`Has_Base_Address = "1";`
105			`Has_IRQ = "1";`
106			`Setup_Time = "0";`
107			`Hold_Time = "0";`
108			`Read_Wait_States = "peripheral_controlled";`
109			`Write_Wait_States = "peripheral_controlled";`
110			`Read_Latency = "0";`
111			`Maximum_Pending_Read_Transactions = "0";`
112			`Active_CS_Through_Read_Latency = "0";`
113			`Is_Printable_Device = "0";`
114			`Is_Memory_Device = "0";`
115			`Is_Readable = "1";`
116			`Is_Writable = "1";`
117			`Minimum_Uninterrupted_Run_Length = "1";`
118			`}`
119			`COMPONENT_BUILDER`
120			`{`
121			`AVS_SETTINGS`
122			`{`
123			`Setup_Value = "0";`
124			`Read_Wait_Value = "1";`
125			`Write_Wait_Value = "1";`
126			`Hold_Value = "0";`
127			`Timing_Units = "cycles";`
128			`Read_Latency_Value = "0";`
129			`Minimum_Arbitration_Shares = "1";`
130			`Active_CS_Through_Read_Latency = "0";`
131			`Max_Pending_Read_Transactions_Value = "1";`
132			`Address_Alignment = "native";`
133			`Is_Printable_Device = "0";`
134			`Interleave_Bursts = "0";`
135			`interface_name = "Avalon Slave";`
136			`external_wait = "1";`
137			`Is_Memory_Device = "0";`
138			`}`
139			`}`
140			`PORT_WIRING`
141			`{`
142			`PORT address`
143			`{`
144			`width = "8";`
145			`width_expression = "";`
146			`direction = "input";`
147			`type = "address";`
148			`is_shared = "0";`
149			`vhdl_record_name = "";`
150			`vhdl_record_type = "";`
151			`}`
152			`PORT writedata`
153			`{`
154			`width = "8";`
155			`width_expression = "";`
156			`direction = "input";`
157			`type = "writedata";`
158			`is_shared = "0";`
159			`vhdl_record_name = "";`
160			`vhdl_record_type = "";`
161			`}`
162			`PORT readdata`
163			`{`
164			`width = "8";`
165			`width_expression = "";`
166			`direction = "output";`
167			`type = "readdata";`
168			`is_shared = "0";`
169			`vhdl_record_name = "";`
170			`vhdl_record_type = "";`
171			`}`
172			`PORT write`
173			`{`
174			`width = "1";`
175			`width_expression = "";`
176			`direction = "input";`
177			`type = "write";`
178			`is_shared = "0";`
179			`vhdl_record_name = "";`
180			`vhdl_record_type = "";`
181			`}`
182			`PORT read`
183			`{`
184			`width = "1";`
185			`width_expression = "";`
186			`direction = "input";`
187			`type = "read";`
188			`is_shared = "0";`
189			`vhdl_record_name = "";`
190			`vhdl_record_type = "";`
191			`}`
192			`PORT waitrequest`
193			`{`
194			`width = "1";`
195			`width_expression = "";`
196			`direction = "output";`
197			`type = "waitrequest";`
198			`is_shared = "0";`
199			`vhdl_record_name = "";`
200			`vhdl_record_type = "";`
201			`}`
202			`PORT chipselect`
203			`{`
204			`width = "1";`
205			`width_expression = "";`
206			`direction = "input";`
207			`type = "chipselect";`
208			`is_shared = "0";`
209			`vhdl_record_name = "";`
210			`vhdl_record_type = "";`
211			`}`
212			`PORT irq`
213			`{`
214			`width = "1";`
215			`width_expression = "";`
216			`direction = "output";`
217			`type = "irq";`
218			`is_shared = "0";`
219			`vhdl_record_name = "";`
220			`vhdl_record_type = "";`
221			`}`
222			`PORT USBWireVPI`
223			`{`
224			`width = "1";`
225			`width_expression = "";`
226			`direction = "input";`
227			`type = "export";`
228			`is_shared = "0";`
229			`vhdl_record_name = "";`
230			`vhdl_record_type = "";`
231			`}`
232			`PORT USBWireVMI`
233			`{`
234			`width = "1";`
235			`width_expression = "";`
236			`direction = "input";`
237			`type = "export";`
238			`is_shared = "0";`
239			`vhdl_record_name = "";`
240			`vhdl_record_type = "";`
241			`}`
242			`PORT USBWireDataInTick`
243			`{`
244			`width = "1";`
245			`width_expression = "";`
246			`direction = "output";`
247			`type = "export";`
248			`is_shared = "0";`
249			`vhdl_record_name = "";`
250			`vhdl_record_type = "";`
251			`}`
252			`PORT USBWireVPO`
253			`{`
254			`width = "1";`
255			`width_expression = "";`
256			`direction = "output";`
257			`type = "export";`
258			`is_shared = "0";`
259			`vhdl_record_name = "";`
260			`vhdl_record_type = "";`
261			`}`
262			`PORT USBWireVMO`
263			`{`
264			`width = "1";`
265			`width_expression = "";`
266			`direction = "output";`
267			`type = "export";`
268			`is_shared = "0";`
269			`vhdl_record_name = "";`
270			`vhdl_record_type = "";`
271			`}`
272			`PORT USBWireDataOutTick`
273			`{`
274			`width = "1";`
275			`width_expression = "";`
276			`direction = "output";`
277			`type = "export";`
278			`is_shared = "0";`
279			`vhdl_record_name = "";`
280			`vhdl_record_type = "";`
281			`}`
282			`PORT USBWireOutEn_n`
283			`{`
284			`width = "1";`
285			`width_expression = "";`
286			`direction = "output";`
287			`type = "export";`
288			`is_shared = "0";`
289			`vhdl_record_name = "";`
290			`vhdl_record_type = "";`
291			`}`
292			`PORT USBFullSpeed`
293			`{`
294			`width = "1";`
295			`width_expression = "";`
296			`direction = "output";`
297			`type = "export";`
298			`is_shared = "0";`
299			`vhdl_record_name = "";`
300			`vhdl_record_type = "";`
301			`}`
302			`}`
303			`}`
304			`}`
305			`USER_INTERFACE`
306			`{`
307			`USER_LABELS`
308			`{`
309			`name = "usbHostSlaveAvalonWrap";`
310			`technology = "user logic";`
311			`}`
312			`WIZARD_UI the_wizard_ui`
313			`{`
314			`title = "usbHostSlaveAvalonWrap - {{ $MOD }}";`
315			`CONTEXT`
316			`{`
317			`H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";`
318			`M = "";`
319			`SBI_global_signals = "SYSTEM_BUILDER_INFO";`
320			`SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";`
321			`}`
322			`PAGES main`
323			`{`
324			`PAGE 1`
325			`{`
326			`align = "left";`
327			`title = "usbHostSlaveAvalonWrap 1.0 Settings";`
328			`layout = "vertical";`
329			`TEXT`
330			`{`
331			`title = "Built on: 2006.10.11.20:54:36";`
332			`}`
333			`TEXT`
334			`{`
335			`title = "Class name: usbhostslaveavalonwrap";`
336			`}`
337			`TEXT`
338			`{`
339			`title = "Class version: 1.0";`
340			`}`
341			`TEXT`
342			`{`
343			`title = "Component name: usbHostSlaveAvalonWrap";`
344			`}`
345			`TEXT`
346			`{`
347			`title = "Component Group: user logic";`
348			`}`
349			`}`
350			`}`
351			`}`
352			`}`
353			`SOPC_Builder_Version = "6.00";`
354			`COMPONENT_BUILDER`
355			`{`
356			`HDL_PARAMETERS`
357			`{`
358			`# generated by CBDocument.getParameterContainer`
359			`# used only by Component Editor`
360			`}`
361			`SW_FILES`
362			`{`
363			`}`
364			`built_on = "2006.10.11.20:54:36";`
365			`CACHED_HDL_INFO`
366			`{`
367			`# cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection`
368			`# used only by Component Builder`
369			`FILE usbHostSlaveAvalonWrap.v`
370			`{`
371			`file_mod = "Fri Oct 06 19:53:44 PDT 2006";`
372			`quartus_map_start = "Sat Oct 07 21:44:02 PDT 2006";`
373			`quartus_map_finished = "Sat Oct 07 21:44:11 PDT 2006";`
374			`#found 1 valid modules`
375			`WRAPPER usbHostSlaveAvalonWrap`
376			`{`
377			`CLASS usbHostSlaveAvalonWrap`
378			`{`
379			`CB_GENERATOR`
380			`{`
381			`HDL_FILES`
382			`{`
383			`FILE`
384			`{`
385			`use_in_simulation = "1";`
386			`use_in_synthesis = "1";`
387			`type = "";`
388			`filepath = "C:/projects/usbhostslaveCVS/usbhostslave/syn/Altera/sopcCompProj/atom_netlists/usbHostSlaveAvalonWrap.v";`
389			`}`
390			`}`
391			`top_module_name = "usbHostSlaveAvalonWrap";`
392			`emit_system_h = "0";`
393			`}`
394			`MODULE_DEFAULTS global_signals`
395			`{`
396			`class = "usbHostSlaveAvalonWrap";`
397			`class_version = "1.0";`
398			`SYSTEM_BUILDER_INFO`
399			`{`
400			`Instantiate_In_System_Module = "1";`
401			`}`
402			`SLAVE avalon_slave_0`
403			`{`
404			`SYSTEM_BUILDER_INFO`
405			`{`
406			`Bus_Type = "avalon";`
407			`}`
408			`PORT_WIRING`
409			`{`
410			`PORT address`
411			`{`
412			`width = "8";`
413			`width_expression = "";`
414			`direction = "input";`
415			`type = "address";`
416			`is_shared = "0";`
417			`vhdl_record_name = "";`
418			`vhdl_record_type = "";`
419			`}`
420			`PORT writedata`
421			`{`
422			`width = "8";`
423			`width_expression = "";`
424			`direction = "input";`
425			`type = "writedata";`
426			`is_shared = "0";`
427			`vhdl_record_name = "";`
428			`vhdl_record_type = "";`
429			`}`
430			`PORT readdata`
431			`{`
432			`width = "8";`
433			`width_expression = "";`
434			`direction = "output";`
435			`type = "readdata";`
436			`is_shared = "0";`
437			`vhdl_record_name = "";`
438			`vhdl_record_type = "";`
439			`}`
440			`PORT write`
441			`{`
442			`width = "1";`
443			`width_expression = "";`
444			`direction = "input";`
445			`type = "write";`
446			`is_shared = "0";`
447			`vhdl_record_name = "";`
448			`vhdl_record_type = "";`
449			`}`
450			`PORT read`
451			`{`
452			`width = "1";`
453			`width_expression = "";`
454			`direction = "input";`
455			`type = "read";`
456			`is_shared = "0";`
457			`vhdl_record_name = "";`
458			`vhdl_record_type = "";`
459			`}`
460			`PORT waitrequest`
461			`{`
462			`width = "1";`
463			`width_expression = "";`
464			`direction = "output";`
465			`type = "waitrequest";`
466			`is_shared = "0";`
467			`vhdl_record_name = "";`
468			`vhdl_record_type = "";`
469			`}`
470			`PORT chipselect`
471			`{`
472			`width = "1";`
473			`width_expression = "";`
474			`direction = "input";`
475			`type = "chipselect";`
476			`is_shared = "0";`
477			`vhdl_record_name = "";`
478			`vhdl_record_type = "";`
479			`}`
480			`PORT irq`
481			`{`
482			`width = "1";`
483			`width_expression = "";`
484			`direction = "output";`
485			`type = "irq";`
486			`is_shared = "0";`
487			`vhdl_record_name = "";`
488			`vhdl_record_type = "";`
489			`}`
490			`PORT usbClk`
491			`{`
492			`width = "1";`
493			`width_expression = "";`
494			`direction = "input";`
495			`type = "export";`
496			`is_shared = "0";`
497			`vhdl_record_name = "";`
498			`vhdl_record_type = "";`
499			`}`
500			`PORT USBWireVPI`

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