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sfielding |
VERSION=1.15
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HEADER
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FILE="checkLineState.asf"
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FID=4788d213
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LANGUAGE=VERILOG
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ENTITY="checkLineState"
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FRAMES=ON
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FREEOID=1077
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"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// checkLineState.v ////\n//// ////\n//// This file is part of the usbHostSlave opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// Checks USB line state. When reset state detected\n//// asserts usbRstDet for one clock tick\n//// usbRstDet is used to reset most of the logic.\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbHostSlaveReg_define.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbDevice_define.v\""
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END
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BUNDLES
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B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0
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B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0
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B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0
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B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0
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B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0
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B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0
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B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0
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B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0
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B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4
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B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0
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B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0
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B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0
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END
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INSTHEADER 1
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PAGE 25400,25400 215900,279400
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UPPERLEFT 0,0
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GRID=OFF
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GRIDSIZE 5000,5000 10000,10000
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END
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OBJECTS
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G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: checkLineState"
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A 5 0 1 TEXT "Actions" | 30400,266400 1 0 0 "-- diagram ACTION"
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F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,212603
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L 7 6 0 TEXT "Labels" | 31673,209974 1 0 0 "chkLSt"
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L 564 565 0 TEXT "Labels" | 83155,262907 1 0 0 "usbRstDet"
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I 565 0 2 Builtin OutPort | 77155,262907 "" ""
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I 74 0 2 Builtin InPort | 195700,267632 "" ""
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L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst"
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I 72 0 3 Builtin InPort | 195700,272800 "" ""
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L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk"
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S 100 6 0 ELLIPSE "States" | 112176,193512 6500 6500
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L 99 100 0 TEXT "State Labels" | 112176,193512 1 0 0 "START\n/0/"
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C 389 388 0 TEXT "Conditions" | 64133,197548 1 0 0 "rst == 1'b1"
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W 388 6 0 387 100 BEZIER "Transitions" | 49555,202550 64193,201024 91216,196545 105854,195019
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I 387 6 0 Builtin Reset | 49555,202550
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I 471 0 130 Builtin OutPort | 120974,258272 "" ""
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L 472 471 0 TEXT "Labels" | 126974,258272 1 0 0 "wb_addr[7:0]"
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I 473 0 2 Builtin OutPort | 121470,234129 "" ""
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L 474 473 0 TEXT "Labels" | 127470,234129 1 0 0 "wb_we"
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I 475 0 2 Builtin OutPort | 121470,239089 "" ""
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L 476 475 0 TEXT "Labels" | 127470,239089 1 0 0 "wb_stb"
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I 479 0 130 Builtin InPort | 123454,253473 "" ""
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| 54 |
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L 480 479 0 TEXT "Labels" | 129454,253473 1 0 0 "wb_data_i[7:0]"
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I 481 0 2 Builtin InPort | 123702,243801 "" ""
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L 482 481 0 TEXT "Labels" | 129702,243801 1 0 0 "wb_ack"
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L 494 495 0 TEXT "Labels" | 83190,258260 1 0 0 "initComplete"
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I 495 0 2 Builtin InPort | 77190,258260 "" ""
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L 496 497 0 TEXT "Labels" | 83190,253838 1 0 0 "wbBusReq"
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I 497 0 2 Builtin OutPort | 77190,253838 "" ""
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L 498 499 0 TEXT "Labels" | 85401,249215 1 0 0 "wbBusGnt"
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I 499 0 2 Builtin InPort | 79401,249215 "" ""
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S 1043 6 4096 ELLIPSE "States" | 74797,116753 6500 6500
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A 1044 1043 4 TEXT "Actions" | 91359,124097 1 0 0 "wb_addr <= `RA_SC_LINE_STATUS_REG;\nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
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S 1045 6 8192 ELLIPSE "States" | 74187,138513 6500 6500
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L 1046 1045 0 TEXT "State Labels" | 74187,138513 1 0 0 "WT_GNT\n/2/"
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A 1047 1045 4 TEXT "Actions" | 91995,140209 1 0 0 "wbBusReq <= 1'b1;"
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W 1051 6 0 1045 1043 BEZIER "Transitions" | 74066,132060 74119,129516 74220,125771 74273,123227
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C 1052 1051 0 TEXT "Conditions" | 76307,130457 1 0 0 "wbBusGnt == 1'b1"
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W 1053 6 0 1043 1063 BEZIER "Transitions" | 74742,110285 74658,108295 74665,87535 74878,72303
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C 1054 1053 0 TEXT "Conditions" | 52376,109915 1 0 0 "wb_ack == 1'b1"
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A 1055 1053 16 TEXT "Actions" | 43552,104880 1 0 0 "wb_stb <= 1'b0;\nif ( (wb_data_i[1:0] == `DISCONNECT) || (wb_data_i[`VBUS_PRES_BIT] == 1'b0) )\n resetState <= {resetState[0], 1'b1};\nelse\n resetState <= 2'b00;\nwbBusReq <= 1'b0;"
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C 1071 1061 0 TEXT "Conditions" | 101452,177220 1 0 0 "initComplete == 1'b1"
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L 1056 1043 0 TEXT "State Labels" | 74797,116753 1 0 0 "GET_STAT\n/1/"
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W 1061 6 0 100 1045 BEZIER "Transitions" | 108298,188296 100155,176813 85729,155535 77586,144052
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L 1062 1063 0 TEXT "State Labels" | 75483,66966 1 0 0 "SET_RST_DET\n/3/"
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S 1063 6 12288 ELLIPSE "States" | 75483,66966 6500 6500
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L 1064 1065 0 TEXT "State Labels" | 76581,38853 1 0 0 "DEL_ONE_MSEC\n/4/"
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S 1065 6 16384 ELLIPSE "States" | 76581,38853 6500 6500
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W 1066 6 0 1063 1065 BEZIER "Transitions" | 75394,60480 75571,54410 75922,51155 75989,45315
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A 1067 1066 16 TEXT "Actions" | 66310,59029 1 0 0 "if (resetState == 2'b11) // if reset condition aserted for 2mS\n usbRstDet <= 1'b1; \ncnt <= 16'h0000;"
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A 1068 1065 4 TEXT "Actions" | 97514,47021 1 0 0 "cnt <= cnt + 1'b1;\nusbRstDet <= 1'b0;"
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W 1069 6 0 1065 1045 BEZIER "Transitions" | 82990,37770 98582,38531 128050,34971 141866,41055\
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155682,47140 179565,74042 183796,90420 188028,106798\
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181074,145412 173411,156071 165748,166731 142049,170757\
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129605,167943 117162,165130 92622,149773 79584,142133
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C 1070 1069 0 TEXT "Conditions" | 97438,36458 1 0 0 "cnt == `ONE_MSEC_DEL"
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I 1076 0 130 Builtin Signal | 43632,229376 "" ""
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L 1075 1076 0 TEXT "Labels" | 46632,229376 1 0 0 "resetState[1:0]"
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I 1074 0 130 Builtin Signal | 42480,236720 "" ""
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L 1073 1074 0 TEXT "Labels" | 45480,236720 1 0 0 "cnt[15:0]"
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A 1072 100 4 TEXT "Actions" | 128684,204360 1 0 0 "usbRstDet <= 1'b0;\nwbBusReq <= 1'b0;\nwb_addr <= 8'h00;\nwb_stb <= 1'b0;\nwb_we <= 1'b0;\ncnt <= 16'h0000;\nresetState <= 2'b00;"
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END
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