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[/] [usbhostslave/] [trunk/] [usbDevice/] [RTL/] [EP1Mouse.v] - Blame information for rev 43

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// EP1Mouse.v                                                 ////
////                                                              ////
//// This file is part of the usbHostSlave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// Implements EP1 as a IN endpoint
//// simulating a mouse (a broken one) by 
//// responding to IN requests with a constant (x,y) <= (1,1)
//// which causes the mouse pointer to move from 
//// top left to bottom right of the screen
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostSlaveReg_define.v"
 
module EP1Mouse (clk, initComplete, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
input   clk;
input   initComplete;
input   rst;
input   wb_ack;
input   [7:0]wb_data_i;
input   wbBusGnt;
output  [7:0]wb_addr;
output  [7:0]wb_data_o;
output  wb_stb;
output  wb_we;
output  wbBusReq;
 
wire    clk;
wire    initComplete;
wire    rst;
wire    wb_ack;
reg     [7:0]wb_addr, next_wb_addr;
wire    [7:0]wb_data_i;
reg     [7:0]wb_data_o, next_wb_data_o;
reg     wb_stb, next_wb_stb;
reg     wb_we, next_wb_we;
wire    wbBusGnt;
reg     wbBusReq, next_wbBusReq;
 
// diagram signals declarations
reg  [7:0]cnt, next_cnt;
reg dataSeq, next_dataSeq;
reg localRst, next_localRst;
reg transDone, next_transDone;
 
// BINARY ENCODED state machine: EP1St
// State codes definitions:
`define DO_TRANS_WT_GNT 4'b0000
`define DO_TRANS_TX_EMPTY 4'b0001
`define DO_TRANS_WR_TX_FIFO1 4'b0010
`define DO_TRANS_TRANS_GO 4'b0011
`define DO_TRANS_WT_TRANS_DONE_WT_GNT 4'b0100
`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 4'b0101
`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 4'b0110
`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 4'b0111
`define START 4'b1000
`define DO_TRANS_WR_TX_FIFO2 4'b1001
`define DO_TRANS_WR_TX_FIFO3 4'b1010
`define DO_TRANS_WT_TRANS_DONE_DEL 4'b1011
 
reg [3:0]CurrState_EP1St, NextState_EP1St;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: EP1St
 
// NextState logic (combinatorial)
always @ (wbBusGnt or wb_ack or wb_data_i or transDone or initComplete or cnt or wbBusReq or wb_addr or wb_data_o or wb_stb or wb_we or dataSeq or CurrState_EP1St)
begin
  NextState_EP1St <= CurrState_EP1St;
  // Set default values for outputs and signals
  next_wbBusReq <= wbBusReq;
  next_wb_addr <= wb_addr;
  next_wb_data_o <= wb_data_o;
  next_wb_stb <= wb_stb;
  next_wb_we <= wb_we;
  next_dataSeq <= dataSeq;
  next_transDone <= transDone;
  next_cnt <= cnt;
  case (CurrState_EP1St)  // synopsys parallel_case full_case
    `START:
    begin
      next_wbBusReq <= 1'b0;
      next_wb_addr <= 8'h00;
      next_wb_data_o <= 8'h00;
      next_wb_stb <= 1'b0;
      next_wb_we <= 1'b0;
      next_cnt <= 8'h00;
      next_dataSeq <= 1'b0;
      next_transDone <= 1'b0;
      if (initComplete == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_WT_GNT;
      end
    end
    `DO_TRANS_WT_GNT:
    begin
      next_wbBusReq <= 1'b1;
      if (wbBusGnt == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_TX_EMPTY;
      end
    end
    `DO_TRANS_TX_EMPTY:
    begin
      next_wb_addr <= `RA_EP1_TX_FIFO_CONTROL_REG;
      next_wb_data_o <= 8'h01;
      //force tx fifo empty
      next_wb_stb <= 1'b1;
      next_wb_we <= 1'b1;
      if (wb_ack == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO1;
        next_wb_stb <= 1'b0;
        next_wb_addr <= `RA_EP1_TX_FIFO_DATA_REG;
        next_wb_we <= 1'b1;
      end
    end
    `DO_TRANS_WR_TX_FIFO1:
    begin
      next_wb_data_o <= 8'h00;
      next_wb_stb <= 1'b1;
      if (wb_ack == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO2;
        next_wb_stb <= 1'b0;
      end
    end
    `DO_TRANS_TRANS_GO:
    begin
      next_wb_addr <= `RA_EP1_CONTROL_REG;
      if (dataSeq == 1'b1)
      next_wb_data_o <= 8'h07;
      else
      next_wb_data_o <= 8'h03;
      next_wb_stb <= 1'b1;
      next_wb_we <= 1'b1;
      if (wb_ack == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
        next_wb_stb <= 1'b0;
        if (dataSeq == 1'b1)
        next_dataSeq <= 1'b0;
        else
        next_dataSeq <= 1'b1;
        next_transDone <= 1'b0;
      end
    end
    `DO_TRANS_WR_TX_FIFO2:
    begin
      next_wb_data_o <= 8'h01;
      next_wb_stb <= 1'b1;
      if (wb_ack == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO3;
        next_wb_stb <= 1'b0;
      end
    end
    `DO_TRANS_WR_TX_FIFO3:
    begin
      next_wb_data_o <= 8'h01;
      next_wb_stb <= 1'b1;
      if (wb_ack == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_TRANS_GO;
        next_wb_stb <= 1'b0;
      end
    end
    `DO_TRANS_WT_TRANS_DONE_WT_GNT:
    begin
      next_wbBusReq <= 1'b1;
      if (wbBusGnt == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
      end
    end
    `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
    begin
      next_wb_addr <= `RA_EP1_CONTROL_REG;
      next_wb_stb <= 1'b1;
      next_wb_we <= 1'b0;
      if (wb_ack == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
        next_wb_stb <= 1'b0;
        next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
      end
    end
    `DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
    begin
      next_wbBusReq <= 1'b0;
      if (wbBusGnt == 1'b0)
      begin
        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
      end
    end
    `DO_TRANS_WT_TRANS_DONE_CHK_DONE:
    begin
      if (transDone == 1'b1)
      begin
        NextState_EP1St <= `DO_TRANS_WT_GNT;
      end
      else
      begin
        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_DEL;
        next_cnt <= 8'h00;
      end
    end
    `DO_TRANS_WT_TRANS_DONE_DEL:
    begin
      next_cnt <= cnt + 1'b1;
      if (cnt == `ONE_USEC_DEL)
      begin
        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst == 1'b1)
    CurrState_EP1St <= `START;
  else
    CurrState_EP1St <= NextState_EP1St;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst == 1'b1)
  begin
    wbBusReq <= 1'b0;
    wb_addr <= 8'h00;
    wb_data_o <= 8'h00;
    wb_stb <= 1'b0;
    wb_we <= 1'b0;
    dataSeq <= 1'b0;
    transDone <= 1'b0;
    cnt <= 8'h00;
  end
  else
  begin
    wbBusReq <= next_wbBusReq;
    wb_addr <= next_wb_addr;
    wb_data_o <= next_wb_data_o;
    wb_stb <= next_wb_stb;
    wb_we <= next_wb_we;
    dataSeq <= next_dataSeq;
    transDone <= next_transDone;
    cnt <= next_cnt;
  end
end
 
endmodule

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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [usbDevice/] [RTL/] [EP1Mouse.v] - Blame information for rev 43

Line No.	Rev	Author	Line
1	37	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// EP1Mouse.v ////`
5			`//// ////`
6			`//// This file is part of the usbHostSlave opencores effort.`
7			`//// <http://www.opencores.org/cores//> ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`//// Implements EP1 as a IN endpoint`
11			`//// simulating a mouse (a broken one) by`
12			`//// responding to IN requests with a constant (x,y) <= (1,1)`
13			`//// which causes the mouse pointer to move from`
14			`//// top left to bottom right of the screen`
15			`//// ////`
16			`//// To Do: ////`
17			`////`
18			`//// ////`
19			`//// Author(s): ////`
20			`//// - Steve Fielding, sfielding@base2designs.com ////`
21			`//// ////`
22			`//////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from <http://www.opencores.org/lgpl.shtml> ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48			`//`
49			`include "timescale.v"
50			`include "usbHostSlaveReg_define.v"
51
52			`module EP1Mouse (clk, initComplete, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);`
53			`input clk;`
54			`input initComplete;`
55			`input rst;`
56			`input wb_ack;`
57			`input [7:0]wb_data_i;`
58			`input wbBusGnt;`
59			`output [7:0]wb_addr;`
60			`output [7:0]wb_data_o;`
61			`output wb_stb;`
62			`output wb_we;`
63			`output wbBusReq;`
64
65			`wire clk;`
66			`wire initComplete;`
67			`wire rst;`
68			`wire wb_ack;`
69			`reg [7:0]wb_addr, next_wb_addr;`
70			`wire [7:0]wb_data_i;`
71			`reg [7:0]wb_data_o, next_wb_data_o;`
72			`reg wb_stb, next_wb_stb;`
73			`reg wb_we, next_wb_we;`
74			`wire wbBusGnt;`
75			`reg wbBusReq, next_wbBusReq;`
76
77			`// diagram signals declarations`
78			`reg [7:0]cnt, next_cnt;`
79			`reg dataSeq, next_dataSeq;`
80			`reg localRst, next_localRst;`
81			`reg transDone, next_transDone;`
82
83			`// BINARY ENCODED state machine: EP1St`
84			`// State codes definitions:`
85			`define DO_TRANS_WT_GNT 4'b0000
86			`define DO_TRANS_TX_EMPTY 4'b0001
87			`define DO_TRANS_WR_TX_FIFO1 4'b0010
88			`define DO_TRANS_TRANS_GO 4'b0011
89			`define DO_TRANS_WT_TRANS_DONE_WT_GNT 4'b0100
90			`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 4'b0101
91			`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 4'b0110
92			`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 4'b0111
93			`define START 4'b1000
94			`define DO_TRANS_WR_TX_FIFO2 4'b1001
95			`define DO_TRANS_WR_TX_FIFO3 4'b1010
96			`define DO_TRANS_WT_TRANS_DONE_DEL 4'b1011
97
98			`reg [3:0]CurrState_EP1St, NextState_EP1St;`
99
100			`// Diagram actions (continuous assignments allowed only: assign ...)`
101			`// diagram ACTION`
102
103
104			`// Machine: EP1St`
105
106			`// NextState logic (combinatorial)`
107			`always @ (wbBusGnt or wb_ack or wb_data_i or transDone or initComplete or cnt or wbBusReq or wb_addr or wb_data_o or wb_stb or wb_we or dataSeq or CurrState_EP1St)`
108			`begin`
109			`NextState_EP1St <= CurrState_EP1St;`
110			`// Set default values for outputs and signals`
111			`next_wbBusReq <= wbBusReq;`
112			`next_wb_addr <= wb_addr;`
113			`next_wb_data_o <= wb_data_o;`
114			`next_wb_stb <= wb_stb;`
115			`next_wb_we <= wb_we;`
116			`next_dataSeq <= dataSeq;`
117			`next_transDone <= transDone;`
118			`next_cnt <= cnt;`
119			`case (CurrState_EP1St) // synopsys parallel_case full_case`
120			`START:
121			`begin`
122			`next_wbBusReq <= 1'b0;`
123			`next_wb_addr <= 8'h00;`
124			`next_wb_data_o <= 8'h00;`
125			`next_wb_stb <= 1'b0;`
126			`next_wb_we <= 1'b0;`
127			`next_cnt <= 8'h00;`
128			`next_dataSeq <= 1'b0;`
129			`next_transDone <= 1'b0;`
130			`if (initComplete == 1'b1)`
131			`begin`
132			NextState_EP1St <= `DO_TRANS_WT_GNT;
133			`end`
134			`end`
135			`DO_TRANS_WT_GNT:
136			`begin`
137			`next_wbBusReq <= 1'b1;`
138			`if (wbBusGnt == 1'b1)`
139			`begin`
140			NextState_EP1St <= `DO_TRANS_TX_EMPTY;
141			`end`
142			`end`
143			`DO_TRANS_TX_EMPTY:
144			`begin`
145			next_wb_addr <= `RA_EP1_TX_FIFO_CONTROL_REG;
146			`next_wb_data_o <= 8'h01;`
147			`//force tx fifo empty`
148			`next_wb_stb <= 1'b1;`
149			`next_wb_we <= 1'b1;`
150			`if (wb_ack == 1'b1)`
151			`begin`
152			NextState_EP1St <= `DO_TRANS_WR_TX_FIFO1;
153			`next_wb_stb <= 1'b0;`
154			next_wb_addr <= `RA_EP1_TX_FIFO_DATA_REG;
155			`next_wb_we <= 1'b1;`
156			`end`
157			`end`
158			`DO_TRANS_WR_TX_FIFO1:
159			`begin`
160			`next_wb_data_o <= 8'h00;`
161			`next_wb_stb <= 1'b1;`
162			`if (wb_ack == 1'b1)`
163			`begin`
164			NextState_EP1St <= `DO_TRANS_WR_TX_FIFO2;
165			`next_wb_stb <= 1'b0;`
166			`end`
167			`end`
168			`DO_TRANS_TRANS_GO:
169			`begin`
170			next_wb_addr <= `RA_EP1_CONTROL_REG;
171			`if (dataSeq == 1'b1)`
172			`next_wb_data_o <= 8'h07;`
173			`else`
174			`next_wb_data_o <= 8'h03;`
175			`next_wb_stb <= 1'b1;`
176			`next_wb_we <= 1'b1;`
177			`if (wb_ack == 1'b1)`
178			`begin`
179			NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
180			`next_wb_stb <= 1'b0;`
181			`if (dataSeq == 1'b1)`
182			`next_dataSeq <= 1'b0;`
183			`else`
184			`next_dataSeq <= 1'b1;`
185			`next_transDone <= 1'b0;`
186			`end`
187			`end`
188			`DO_TRANS_WR_TX_FIFO2:
189			`begin`
190			`next_wb_data_o <= 8'h01;`
191			`next_wb_stb <= 1'b1;`
192			`if (wb_ack == 1'b1)`
193			`begin`
194			NextState_EP1St <= `DO_TRANS_WR_TX_FIFO3;
195			`next_wb_stb <= 1'b0;`
196			`end`
197			`end`
198			`DO_TRANS_WR_TX_FIFO3:
199			`begin`
200			`next_wb_data_o <= 8'h01;`
201			`next_wb_stb <= 1'b1;`
202			`if (wb_ack == 1'b1)`
203			`begin`
204			NextState_EP1St <= `DO_TRANS_TRANS_GO;
205			`next_wb_stb <= 1'b0;`
206			`end`
207			`end`
208			`DO_TRANS_WT_TRANS_DONE_WT_GNT:
209			`begin`
210			`next_wbBusReq <= 1'b1;`
211			`if (wbBusGnt == 1'b1)`
212			`begin`
213			NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
214			`end`
215			`end`
216			`DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
217			`begin`
218			next_wb_addr <= `RA_EP1_CONTROL_REG;
219			`next_wb_stb <= 1'b1;`
220			`next_wb_we <= 1'b0;`
221			`if (wb_ack == 1'b1)`
222			`begin`
223			NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
224			`next_wb_stb <= 1'b0;`
225			next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
226			`end`
227			`end`
228			`DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
229			`begin`
230			`next_wbBusReq <= 1'b0;`
231			`if (wbBusGnt == 1'b0)`
232			`begin`
233			NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
234			`end`
235			`end`
236			`DO_TRANS_WT_TRANS_DONE_CHK_DONE:
237			`begin`
238			`if (transDone == 1'b1)`
239			`begin`
240			NextState_EP1St <= `DO_TRANS_WT_GNT;
241			`end`
242			`else`
243			`begin`
244			NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_DEL;
245			`next_cnt <= 8'h00;`
246			`end`
247			`end`
248			`DO_TRANS_WT_TRANS_DONE_DEL:
249			`begin`
250			`next_cnt <= cnt + 1'b1;`
251			if (cnt == `ONE_USEC_DEL)
252			`begin`
253			NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
254			`end`
255			`end`
256			`endcase`
257			`end`
258
259			`// Current State Logic (sequential)`
260			`always @ (posedge clk)`
261			`begin`
262			`if (rst == 1'b1)`
263			CurrState_EP1St <= `START;
264			`else`
265			`CurrState_EP1St <= NextState_EP1St;`
266			`end`
267
268			`// Registered outputs logic`
269			`always @ (posedge clk)`
270			`begin`
271			`if (rst == 1'b1)`
272			`begin`
273			`wbBusReq <= 1'b0;`
274			`wb_addr <= 8'h00;`
275			`wb_data_o <= 8'h00;`
276			`wb_stb <= 1'b0;`
277			`wb_we <= 1'b0;`
278			`dataSeq <= 1'b0;`
279			`transDone <= 1'b0;`
280			`cnt <= 8'h00;`
281			`end`
282			`else`
283			`begin`
284			`wbBusReq <= next_wbBusReq;`
285			`wb_addr <= next_wb_addr;`
286			`wb_data_o <= next_wb_data_o;`
287			`wb_stb <= next_wb_stb;`
288			`wb_we <= next_wb_we;`
289			`dataSeq <= next_dataSeq;`
290			`transDone <= next_transDone;`
291			`cnt <= next_cnt;`
292			`end`
293			`end`
294
295			`endmodule`