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[/] [usbhostslave/] [trunk/] [usbDevice/] [RTL/] [usbDeviceAlteraTop.v] - Blame information for rev 43

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1 37 sfielding 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// usbDeviceAlteraTop.v                                                 ////
4 
////                                                              ////
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//// This file is part of the spiMaster opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
9 
//// Top level module for Altera FPGA and NXP ISP1105 USB PHY.
10 
//// Specifically it targets the Base2Designs Altera Development board.
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//// Instantiates a PLL so that the lock signal can be used
12 
//// to reset the logic, and ties unused control signals
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//// to the off or disabled state
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////                                                              ////
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//// To Do:                                                       ////
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////
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
47 
//
48 39 sfielding 
//`define PHY_ISP1105
49 37 sfielding 
module usbDeviceAlteraTop (
50 
 
51 
        //
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        // Global signals
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        //
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                clk,
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56 
        //
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        // SDRAM
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        //
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        mc_addr,
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        mc_ba,
61 
        mc_dqm,
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        mc_we_,
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        mc_cas_,
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        mc_ras_,
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        mc_cke_,
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        sdram_cs,
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        sdram_clk,
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69 
  //
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  // SPI bus
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  //
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  spiClk,
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  spiMasterDataOut,
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  spiCS_n,
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76 
 
77 
  //
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  // USB host
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  //
80 39 sfielding 
  //usbHostOE_n,
81 37 sfielding 
 
82 
  //
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  // USB slave
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  //
85 39 sfielding 
  //usbSlaveVP,
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  //usbSlaveVM,
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88 
  //usbSlaveOE_n,
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  //usbDPlusPullup,
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  //vBusDetect,
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92 
  //
93 
  // Santa Cruz header
94 
  //
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  SC_P_CLK,
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  SC_RST_N,
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  SC_CS_N,
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  SC_P0,
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  SC_P1,
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  SC_P2,
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  SC_P3,
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  SC_P4,
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  SC_P5,
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  SC_P6,
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  SC_P7,
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  SC_P8,
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  SC_P9,
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  SC_P10,
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  SC_P11,
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  SC_P12,
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  SC_P13,
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  SC_P14,
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  SC_P15,
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  SC_P16,
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  SC_P17,
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  SC_P18,
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  SC_P19,
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  SC_P20,
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  SC_P21,
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  SC_P22,
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  SC_P23,
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  SC_P24,
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  SC_P25,
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  SC_P26,
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  SC_P27,
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  SC_P28,
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  SC_P29,
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  SC_P30,
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  SC_P31,
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  SC_P32,
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  SC_P33,
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  SC_P34,
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  SC_P35,
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  SC_P36,
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  SC_P37,
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  SC_P38,
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  SC_P39
138 
 
139 
 
140 
 
141 37 sfielding 
);
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        //
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        // Global signals
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        //
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        input   clk;
146 
 
147 
        //
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        // SDRAM
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        //
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        output  [11:0]   mc_addr;
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        output  [1:0]    mc_ba;
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        output  [3:0]    mc_dqm;
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        output          mc_we_;
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        output          mc_cas_;
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        output          mc_ras_;
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        output          mc_cke_;
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        output          sdram_cs;
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        output          sdram_clk;
159 
 
160 
  //
161 
  // SPI bus
162 
  //
163 
  output spiClk;
164 
  output spiMasterDataOut;
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  output spiCS_n;
166 
 
167 
  //
168 
  // USB host
169 
  //
170 39 sfielding 
  //output usbHostOE_n;
171 37 sfielding 
 
172 
  //
173 
  // USB slave
174 
  //
175 39 sfielding 
  //inout usbSlaveVP;
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  //inout usbSlaveVM;
177 37 sfielding 
 
178 39 sfielding 
  //output usbSlaveOE_n;
179 
  //output usbDPlusPullup;
180 
  //input vBusDetect;
181 
 
182 
`ifdef PHY_ISP1105
183 
  output SC_P_CLK;
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  output SC_RST_N;
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  output SC_CS_N;
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  output SC_P0;
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  output SC_P1;
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  output SC_P2;
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  output SC_P3;
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  output SC_P4;
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  output SC_P5;
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  output SC_P6;
193 
  output SC_P7;
194 
  output SC_P8;
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  output SC_P9;
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  output SC_P10;
197 
  output SC_P11;
198 
  output SC_P12;
199 
  output SC_P13;
200 
  output SC_P14;
201 
  output SC_P15;
202 
  output SC_P16;
203 
  output SC_P17;
204 
  output SC_P18;
205 
  output SC_P19;
206 
  input SC_P20;
207 
  output SC_P21;
208 
  inout SC_P22;
209 
  inout SC_P23;
210 
  output SC_P24;
211 
  output SC_P25;
212 
  output SC_P26;
213 
  output SC_P27;
214 
  output SC_P28;
215 
  output SC_P29;
216 
  output SC_P30;
217 
  output SC_P31;
218 
  output SC_P32;
219 
  output SC_P33;
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  output SC_P34;
221 
  output SC_P35;
222 
  output SC_P36;
223 
  output SC_P37;
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  output SC_P38;
225 
  output SC_P39;
226 
`else
227 
  output SC_P_CLK;
228 
  output SC_RST_N;
229 
  output SC_CS_N;
230 
  output SC_P0;
231 
  output SC_P1;
232 
  input SC_P2;
233 
  output SC_P3;
234 
  input SC_P4;
235 
  output SC_P5;
236 
  output SC_P6;
237 
  output SC_P7;
238 
  output SC_P8;
239 
  output SC_P9;
240 
  output SC_P10;
241 
  output SC_P11;
242 
  output SC_P12;
243 
  output SC_P13;
244 
  output SC_P14;
245 
  output SC_P15;
246 
  output SC_P16;
247 
  output SC_P17;
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  output SC_P18;
249 
  output SC_P19;
250 
  output SC_P20;
251 
  output SC_P21;
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  input SC_P22;
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  output SC_P23;
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  input SC_P24;
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  output SC_P25;
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  output SC_P26;
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  output SC_P27;
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  output SC_P28;
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  output SC_P29;
260 
  output SC_P30;
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  output SC_P31;
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  output SC_P32;
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  output SC_P33;
264 
  output SC_P34;
265 
  output SC_P35;
266 
  output SC_P36;
267 
  output SC_P37;
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  output SC_P38;
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  output SC_P39;
270 
`endif
271 
 
272 
 
273 
 
274 37 sfielding 
//local wires and regs
275 
reg [1:0] rstReg;
276 
wire rst;
277 
wire pll_locked;
278 39 sfielding 
wire usbSlaveVP_in;
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wire usbSlaveVM_in;
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wire usbSlaveVP_out;
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wire usbSlaveVM_out;
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wire usbSlaveFullSpeed;
283 37 sfielding 
 
284 
assign mc_addr = {12{1'b0}};
285 
assign mc_ba = 2'b00;
286 
assign mc_dqm = 4'h0;
287 
assign mc_we_ = 1'b1;
288 
assign mc_cas_ = 1'b1;
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assign mc_ras_ = 1'b1;
290 
assign mc_cke_ = 1'b1;
291 
assign sdram_cs = 1'b1;
292 
assign sdram_clk = 1'b1;
293 
assign spiClk = 1'b0;
294 
assign spiMasterDataOut = 1'b0;
295 
assign spiCS_n = 1'b1;
296 
assign usbHostOE_n = 1'b1;
297 
 
298 
pll_48MHz       pll_48MHz_inst (
299 
        .inclk0 ( clk ),
300 
        .locked( pll_locked)
301 
        );
302 
 
303 
//generate sync reset from pll lock signal
304 
always @(posedge clk) begin
305 
  rstReg[1:0] <= {rstReg[0], ~pll_locked};
306 
end
307 
assign rst = rstReg[1];
308 
 
309 
 
310 
usbDevice u_usbDevice (
311 
  .clk(clk),
312 
  .rst(rst),
313 
  .usbSlaveVP_in(usbSlaveVP_in),
314 
  .usbSlaveVM_in(usbSlaveVM_in),
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  .usbSlaveVP_out(usbSlaveVP_out),
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  .usbSlaveVM_out(usbSlaveVM_out),
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  .usbSlaveOE_n(usbSlaveOE_n),
318 39 sfielding 
  .USBFullSpeed(usbSlaveFullSpeed),
319 37 sfielding 
  .usbDPlusPullup(usbDPlusPullup),
320 39 sfielding 
  .usbDMinusPullup(usbDMinusPullup),
321 37 sfielding 
  .vBusDetect(vBusDetect)
322 
);
323 
 
324 39 sfielding 
`ifdef PHY_ISP1105
325 37 sfielding 
assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
326 
assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
327 39 sfielding 
`else
328 
assign vBusDetect = 1'b1;
329 
`endif
330 37 sfielding 
 
331 39 sfielding 
`ifdef PHY_ISP1105
332 
  assign SC_P_CLK = 1'b0;
333 
  assign SC_RST_N = 1'b0;
334 
  assign SC_CS_N = 1'b0;
335 
  assign SC_P0 = 1'b0;
336 
  assign SC_P1 = 1'b0;
337 
  assign SC_P2 = 1'b0;
338 
  assign SC_P3 = 1'b0;
339 
  assign SC_P4 = 1'b0;
340 
  assign SC_P5 = 1'b0;
341 
  assign SC_P6 = 1'b0;
342 
  assign SC_P7 = 1'b0;
343 
  assign SC_P8 = 1'b0;
344 
  assign SC_P9 = 1'b0;
345 
  assign SC_P10 = 1'b0;
346 
  assign SC_P11 = 1'b0;
347 
  assign SC_P12 = 1'b0;
348 
  assign SC_P13 = 1'b0;
349 
  assign SC_P14 = 1'b0;
350 
  assign SC_P15 = 1'b0;
351 
  assign SC_P16 = 1'b0;
352 
  assign SC_P17 = 1'b0;
353 
  assign SC_P18 = 1'b0;
354 
  assign SC_P19 = 1'b0;
355 
  assign vBusDetect = SC_P20;
356 
  assign SC_P21 = 1'b0;
357 
  assign SC_P22 = usbSlaveVM;
358 
  assign SC_P23 = usbSlaveVP;
359 
  assign SC_P24 = usbSlaveOE_n;
360 
  assign SC_P25 = 1'b0;
361 
  assign SC_P26 = usbDPlusPullup;
362 
  assign SC_P27 = 1'b0;
363 
  assign SC_P28 = usbHostOE_n;
364 
  assign SC_P29 = 1'b0;
365 
  assign SC_P30 = 1'b0;
366 
  assign SC_P31 = 1'b0;
367 
  assign SC_P32 = 1'b0;
368 
  assign SC_P33 = 1'b0;
369 
  assign SC_P34 = 1'b0;
370 
  assign SC_P35 = 1'b0;
371 
  assign SC_P36 = 1'b0;
372 
  assign SC_P37 = 1'b0;
373 
  assign SC_P38 = 1'b0;
374 
  assign SC_P39 = 1'b0;
375 
`else
376 
  assign SC_P_CLK = 1'b0;
377 
  assign SC_RST_N = 1'b0;
378 
  assign SC_CS_N = 1'b0;
379 
  assign SC_P0 = usbSlaveFullSpeed;
380 
  assign SC_P1 = 1'b0;
381 
  assign usbSlaveVM_in = SC_P2;
382 
  assign SC_P3 = 1'b0;
383 
  assign usbSlaveVP_in = SC_P4;
384 
  assign SC_P5 = 1'b0;
385 
  assign SC_P6 = usbSlaveOE_n;
386 
  assign SC_P7 = 1'b0;
387 
  assign SC_P8 = usbSlaveVM_out;
388 
  assign SC_P9 = 1'b0;
389 
  assign SC_P10 = usbSlaveVP_out;
390 
  assign SC_P11 = 1'b0;
391 
  assign SC_P12 = usbDPlusPullup;
392 
  assign SC_P13 = 1'b0;
393 
  assign SC_P14 = usbDMinusPullup;
394 
  assign SC_P15 = 1'b0;
395 
  assign SC_P16 = 1'b0;
396 
  assign SC_P17 = 1'b0;
397 
  assign SC_P18 = 1'b0;
398 
  assign SC_P19 = 1'b0;
399 
  assign SC_P20 = 1'b0;
400 
  assign SC_P21 = 1'b0;
401 
  assign usbHostVM_in = SC_P22;
402 
  assign SC_P23 = 1'b0;
403 
  assign usbHostVP_in = SC_P24;
404 
  assign SC_P25 = usbHostOE_n;
405 
  assign SC_P26 = 1'b0;
406 
  assign SC_P27 = 1'b0;
407 
  assign SC_P28 = 1'b0;
408 
  assign SC_P29 = 1'b0;
409 
  assign SC_P30 = 1'b0;
410 
  assign SC_P31 = 1'b0;
411 
  assign SC_P32 = 1'b0;
412 
  assign SC_P33 = 1'b0;
413 
  assign SC_P34 = 1'b0;
414 
  assign SC_P35 = 1'b0;
415 
  assign SC_P36 = 1'b0;
416 
  assign SC_P37 = 1'b0;
417 
  assign SC_P38 = 1'b0;
418 
  assign SC_P39 = 1'b0;
419 
`endif
420 
 
421 
 
422 
 
423 37 sfielding 
endmodule
424 
 
425 
 

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