OpenCores
URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [usbDevice/] [RTL/] [usbHostSlaveReg_define.v] - Blame information for rev 40

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 37 sfielding 
// ------------------------------ usbHostSlaveReg_define.v ----------------------------
2 
`include "wishBoneBus_h.v"
3 
`include "usbHostSlave_h.v"
4 
 
5 
 
6 
 
7 
`define RA_EP0_CONTROL_REG              `SCREG_BASE+`ENDPOINT_CONTROL_REG
8 
`define RA_EP0_STATUS_REG               `SCREG_BASE+`ENDPOINT_STATUS_REG
9 
`define RA_EP0_TRANSTYPE_STATUS_REG     `SCREG_BASE+`ENDPOINT_TRANSTYPE_STATUS_REG
10 
`define RA_EP0_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NAK_TRANSTYPE_STATUS_REG
11 
`define RA_EP1_CONTROL_REG              `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_CONTROL_REG
12 
`define RA_EP1_STATUS_REG               `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_STATUS_REG
13 
`define RA_EP1_TRANSTYPE_STATUS_REG     `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_TRANSTYPE_STATUS_REG
14 
`define RA_EP1_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`NAK_TRANSTYPE_STATUS_REG
15 
`define RA_EP2_CONTROL_REG              `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_CONTROL_REG
16 
`define RA_EP2_STATUS_REG               `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_STATUS_REG
17 
`define RA_EP2_TRANSTYPE_STATUS_REG     `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)`+`ENDPOINT_TRANSTYPE_STATUS_REG
18 
`define RA_EP2_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`NAK_TRANSTYPE_STATUS_REG
19 
`define RA_EP3_CONTROL_REG              `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_CONTROL_REG
20 
`define RA_EP3_STATUS_REG               `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_STATUS_REG
21 
`define RA_EP3_TRANSTYPE_STATUS_REG     `SCREG_BASE+(NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_TRANSTYPE_STATUS_REG
22 
`define RA_EP3_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`NAK_TRANSTYPE_STATUS_REG
23 
`define RA_SC_CONTROL_REG               `SCREG_BASE+`SC_CONTROL_REG
24 
`define RA_SC_LINE_STATUS_REG           `SCREG_BASE+`SC_LINE_STATUS_REG
25 
`define RA_SC_INTERRUPT_STATUS_REG      `SCREG_BASE+`SC_INTERRUPT_STATUS_REG
26 
`define RA_SC_INTERRUPT_MASK_REG        `SCREG_BASE+`SC_INTERRUPT_MASK_REG
27 
`define RA_SC_ADDRESS                   `SCREG_BASE+`SC_ADDRESS
28 
`define RA_SC_FRAME_NUM_MSP             `SCREG_BASE+`SC_FRAME_NUM_MSP
29 
`define RA_SC_FRAME_NUM_LSP             `SCREG_BASE+`SC_FRAME_NUM_LSP
30 
 
31 
`define RA_EP0_RX_FIFO_DATA_REG         `EP0_RX_FIFO_BASE+`FIFO_DATA_REG
32 
`define RA_EP0_RX_FIFO_STATUS_REG       `EP0_RX_FIFO_BASE+`FIFO_STATUS_REG
33 
`define RA_EP0_RX_FIFO_DATA_COUNT_MSB   `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
34 
`define RA_EP0_RX_FIFO_DATA_COUNT_LSB   `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
35 
`define RA_EP0_RX_FIFO_CONTROL_REG      `EP0_RX_FIFO_BASE+`FIFO_CONTROL_REG
36 
`define RA_EP0_TX_FIFO_DATA_REG         `EP0_TX_FIFO_BASE+`FIFO_DATA_REG
37 
`define RA_EP0_TX_FIFO_STATUS_REG       `EP0_TX_FIFO_BASE+`FIFO_STATUS_REG
38 
`define RA_EP0_TX_FIFO_DATA_COUNT_MSB   `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
39 
`define RA_EP0_TX_FIFO_DATA_COUNT_LSB   `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
40 
`define RA_EP0_TX_FIFO_CONTROL_REG      `EP0_TX_FIFO_BASE+`FIFO_CONTROL_REG
41 
 
42 
`define RA_EP1_RX_FIFO_DATA_REG         `EP1_RX_FIFO_BASE+`FIFO_DATA_REG
43 
`define RA_EP1_RX_FIFO_STATUS_REG       `EP1_RX_FIFO_BASE+`FIFO_STATUS_REG
44 
`define RA_EP1_RX_FIFO_DATA_COUNT_MSB   `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
45 
`define RA_EP1_RX_FIFO_DATA_COUNT_LSB   `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
46 
`define RA_EP1_RX_FIFO_CONTROL_REG      `EP1_RX_FIFO_BASE+`FIFO_CONTROL_REG
47 
`define RA_EP1_TX_FIFO_DATA_REG         `EP1_TX_FIFO_BASE+`FIFO_DATA_REG
48 
`define RA_EP1_TX_FIFO_STATUS_REG       `EP1_TX_FIFO_BASE+`FIFO_STATUS_REG
49 
`define RA_EP1_TX_FIFO_DATA_COUNT_MSB   `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
50 
`define RA_EP1_TX_FIFO_DATA_COUNT_LSB   `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
51 
`define RA_EP1_TX_FIFO_CONTROL_REG      `EP1_TX_FIFO_BASE+`FIFO_CONTROL_REG
52 
 
53 
`define RA_EP2_RX_FIFO_DATA_REG         `EP2_RX_FIFO_BASE+`FIFO_DATA_REG
54 
`define RA_EP2_RX_FIFO_STATUS_REG       `EP2_RX_FIFO_BASE+`FIFO_STATUS_REG
55 
`define RA_EP2_RX_FIFO_DATA_COUNT_MSB   `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
56 
`define RA_EP2_RX_FIFO_DATA_COUNT_LSB   `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
57 
`define RA_EP2_RX_FIFO_CONTROL_REG      `EP2_RX_FIFO_BASE+`FIFO_CONTROL_REG
58 
`define RA_EP2_TX_FIFO_DATA_REG         `EP2_TX_FIFO_BASE+`FIFO_DATA_REG
59 
`define RA_EP2_TX_FIFO_STATUS_REG       `EP2_TX_FIFO_BASE+`FIFO_STATUS_REG
60 
`define RA_EP2_TX_FIFO_DATA_COUNT_MSB   `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
61 
`define RA_EP2_TX_FIFO_DATA_COUNT_LSB   `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
62 
`define RA_EP2_TX_FIFO_CONTROL_REG      `EP2_TX_FIFO_BASE+`FIFO_CONTROL_REG
63 
 
64 
`define RA_EP3_RX_FIFO_DATA_REG         `EP3_RX_FIFO_BASE+`FIFO_DATA_REG
65 
`define RA_EP3_RX_FIFO_STATUS_REG       `EP3_RX_FIFO_BASE+`FIFO_STATUS_REG
66 
`define RA_EP3_RX_FIFO_DATA_COUNT_MSB   `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
67 
`define RA_EP3_RX_FIFO_DATA_COUNT_LSB   `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
68 
`define RA_EP3_RX_FIFO_CONTROL_REG      `EP3_RX_FIFO_BASE+`FIFO_CONTROL_REG
69 
`define RA_EP3_TX_FIFO_DATA_REG         `EP3_TX_FIFO_BASE+`FIFO_DATA_REG
70 
`define RA_EP3_TX_FIFO_STATUS_REG       `EP3_TX_FIFO_BASE+`FIFO_STATUS_REG
71 
`define RA_EP3_TX_FIFO_DATA_COUNT_MSB   `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
72 
`define RA_EP3_TX_FIFO_DATA_COUNT_LSB   `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
73 
`define RA_EP3_TX_FIFO_CONTROL_REG      `EP3_TX_FIFO_BASE+`FIFO_CONTROL_REG
74 
 
75 
`define RA_HOST_SLAVE_MODE              `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG
76 
`define RA_HOST_SLAVE_VERSION           `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG
77 
 
78 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.