1 |
37 |
sfielding |
// ---------------------------------- testcase0.v ----------------------------
|
2 |
|
|
`include "timescale.v"
|
3 |
|
|
`include "usbHostSlave_h.v"
|
4 |
|
|
`include "usbHostControl_h.v"
|
5 |
|
|
`include "usbHostSlaveTB_defines.v"
|
6 |
|
|
|
7 |
|
|
module testCase0();
|
8 |
|
|
|
9 |
|
|
reg ack;
|
10 |
|
|
reg [7:0] data;
|
11 |
|
|
reg [15:0] dataWord;
|
12 |
|
|
reg [7:0] dataRead;
|
13 |
|
|
reg [7:0] dataWrite;
|
14 |
|
|
reg [7:0] USBAddress;
|
15 |
|
|
reg [7:0] USBEndPoint;
|
16 |
|
|
reg [7:0] transType;
|
17 |
|
|
integer dataSize;
|
18 |
|
|
integer i;
|
19 |
|
|
integer j;
|
20 |
|
|
reg bm_req_dir;
|
21 |
|
|
reg [1:0] bm_req_type;
|
22 |
|
|
reg [4:0] bm_req_recp;
|
23 |
|
|
reg [7:0] bRequest;
|
24 |
|
|
reg [15:0] wValue;
|
25 |
|
|
reg [15:0] wIndex;
|
26 |
|
|
reg [15:0] wLength;
|
27 |
|
|
|
28 |
|
|
initial
|
29 |
|
|
begin
|
30 |
|
|
$write("\n\n");
|
31 |
|
|
#1000;
|
32 |
|
|
|
33 |
|
|
testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
|
34 |
|
|
$display("Host Version number = 0x%0x\n", dataRead);
|
35 |
|
|
|
36 |
|
|
$write("Testing host register read/write ");
|
37 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
|
38 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
|
39 |
|
|
$write("--- PASSED\n");
|
40 |
|
|
|
41 |
|
|
$write("Testing register reset ");
|
42 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
|
43 |
|
|
#1000;
|
44 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h00);
|
45 |
|
|
$write("--- PASSED\n");
|
46 |
|
|
#1000;
|
47 |
|
|
|
48 |
|
|
$write("Connect full speed ");
|
49 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
|
50 |
|
|
#40000;
|
51 |
|
|
//expecting full speed connect
|
52 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 6'h02);
|
53 |
|
|
$write("--- PASSED\n");
|
54 |
|
|
|
55 |
|
|
|
56 |
|
|
$write("Host forcing reset ");
|
57 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h1c);
|
58 |
|
|
#40000;
|
59 |
|
|
$write("--- PASSED\n");
|
60 |
|
|
|
61 |
|
|
$write("Connect full speed ");
|
62 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
|
63 |
|
|
#20000;
|
64 |
|
|
//expecting full speed connect
|
65 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
|
66 |
|
|
$write("--- PASSED\n");
|
67 |
|
|
#5000;
|
68 |
|
|
|
69 |
|
|
$write("Cancel interrupts \n");
|
70 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
|
71 |
|
|
|
72 |
|
|
|
73 |
|
|
// --- get status
|
74 |
|
|
$write("Trans test: Device address = 0x00, GET_STATUS. ");
|
75 |
|
|
USBAddress = 8'h00;
|
76 |
|
|
USBEndPoint = 8'h00;
|
77 |
|
|
transType = `SETUP_TRANS;
|
78 |
|
|
dataSize = 8;
|
79 |
|
|
//enable endpoint, and make ready
|
80 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
81 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
82 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
83 |
|
|
bm_req_dir = 1'b1; // 0-Host to device; 1-device to host
|
84 |
|
|
bm_req_type = 2'b00; // 0-standard; 1-class; 2-vendor; 3-RESERVED
|
85 |
|
|
bm_req_recp = 5'b00000; // 0-device; 1-interface; 2-endpoint; 3-other 4..31-reserved
|
86 |
|
|
bRequest = `GET_STATUS;
|
87 |
|
|
wValue = 16'h0000;
|
88 |
|
|
wIndex = 16'h0000;
|
89 |
|
|
wLength = 16'h0008;
|
90 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , {bm_req_dir, bm_req_type, bm_req_recp});
|
91 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , bRequest);
|
92 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[7:0]);
|
93 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[15:8]);
|
94 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[7:0]);
|
95 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[15:8]);
|
96 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[7:0]);
|
97 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[15:8]);
|
98 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
99 |
|
|
#100000
|
100 |
|
|
//expecting transaction done interrupt
|
101 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
102 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
103 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h40);
|
104 |
|
|
$write("--- PASSED\n");
|
105 |
|
|
$write("Trans test: Device address = 0x00, 3 byte IN transaction to Endpoint 0. ");
|
106 |
|
|
USBAddress = 8'h00;
|
107 |
|
|
USBEndPoint = 8'h00;
|
108 |
|
|
transType = `IN_TRANS;
|
109 |
|
|
//enable endpoint, and make ready
|
110 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
111 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
112 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
113 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
114 |
|
|
#20000
|
115 |
|
|
//expecting transaction done interrupt
|
116 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
117 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
118 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h80);
|
119 |
|
|
$write("Checking receive data ");
|
120 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_LSB , 2);
|
121 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_MSB , 0);
|
122 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 1);
|
123 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 0);
|
124 |
|
|
$write("--- PASSED\n");
|
125 |
|
|
|
126 |
|
|
|
127 |
|
|
|
128 |
|
|
|
129 |
|
|
|
130 |
|
|
|
131 |
|
|
|
132 |
|
|
|
133 |
|
|
|
134 |
|
|
// --- set address
|
135 |
|
|
$write("Trans test: Device address = 0x00, SET_ADDRESS. ");
|
136 |
|
|
USBAddress = 8'h00;
|
137 |
|
|
USBEndPoint = 8'h00;
|
138 |
|
|
transType = `SETUP_TRANS;
|
139 |
|
|
dataSize = 8;
|
140 |
|
|
//enable endpoint, and make ready
|
141 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
142 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
143 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
144 |
|
|
bm_req_dir = 1'b1; // 0-Host to device; 1-device to host
|
145 |
|
|
bm_req_type = 2'b00; // 0-standard; 1-class; 2-vendor; 3-RESERVED
|
146 |
|
|
bm_req_recp = 5'b00000; // 0-device; 1-interface; 2-endpoint; 3-other 4..31-reserved
|
147 |
|
|
bRequest = `SET_ADDRESS;
|
148 |
|
|
wValue = 16'h0012; //set device address = 0x12
|
149 |
|
|
wIndex = 16'h0000;
|
150 |
|
|
wLength = 16'h0000;
|
151 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , {bm_req_dir, bm_req_type, bm_req_recp});
|
152 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , bRequest);
|
153 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[7:0]);
|
154 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[15:8]);
|
155 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[7:0]);
|
156 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[15:8]);
|
157 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[7:0]);
|
158 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[15:8]);
|
159 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
160 |
|
|
#100000
|
161 |
|
|
//expecting transaction done interrupt
|
162 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
163 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
164 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h40);
|
165 |
|
|
$write("--- PASSED\n");
|
166 |
|
|
$write("Trans test: Device address = 0x00, Sending IN so that USB address change will take effect. ");
|
167 |
|
|
USBAddress = 8'h00;
|
168 |
|
|
USBEndPoint = 8'h00;
|
169 |
|
|
transType = `IN_TRANS;
|
170 |
|
|
//enable endpoint, and make ready
|
171 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
172 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
173 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
174 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
175 |
|
|
#20000
|
176 |
|
|
//expecting transaction done interrupt
|
177 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
178 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
179 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h80);
|
180 |
|
|
$write("Checking receive data is zero ");
|
181 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_LSB , 0);
|
182 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_MSB , 0);
|
183 |
|
|
$write("--- PASSED\n");
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
|
187 |
|
|
// --- get device descriptor
|
188 |
|
|
$write("Trans test: Device address = 0x12, get device descriptor. ");
|
189 |
|
|
USBAddress = 8'h012;
|
190 |
|
|
USBEndPoint = 8'h00;
|
191 |
|
|
transType = `SETUP_TRANS;
|
192 |
|
|
//enable endpoint, and make ready
|
193 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
194 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
195 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
196 |
|
|
bm_req_dir = 1'b1; // 0-Host to device; 1-device to host
|
197 |
|
|
bm_req_type = 2'b00; // 0-standard; 1-class; 2-vendor; 3-RESERVED
|
198 |
|
|
bm_req_recp = 5'b00000; // 0-device; 1-interface; 2-endpoint; 3-other 4..31-reserved
|
199 |
|
|
bRequest = `GET_DESCRIPTOR;
|
200 |
|
|
wValue = {`DEV_DESC, 8'h00};
|
201 |
|
|
wIndex = 16'h0000;
|
202 |
|
|
wLength = 16'h0040;
|
203 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , {bm_req_dir, bm_req_type, bm_req_recp});
|
204 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , bRequest);
|
205 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[7:0]);
|
206 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[15:8]);
|
207 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[7:0]);
|
208 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[15:8]);
|
209 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[7:0]);
|
210 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[15:8]);
|
211 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
212 |
|
|
#100000
|
213 |
|
|
//expecting transaction done interrupt
|
214 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
215 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
216 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h40);
|
217 |
|
|
$write("--- PASSED\n");
|
218 |
|
|
$write("Trans test: Device address = 0x12, 18 byte IN transaction to Endpoint 0. ");
|
219 |
|
|
USBAddress = 8'h12;
|
220 |
|
|
USBEndPoint = 8'h00;
|
221 |
|
|
transType = `IN_TRANS;
|
222 |
|
|
//enable endpoint, and make ready
|
223 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
224 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
225 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
226 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
227 |
|
|
#100000
|
228 |
|
|
//expecting transaction done interrupt
|
229 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
230 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
231 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h80);
|
232 |
|
|
$write("Checking receive data ");
|
233 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_LSB , 8'h12);
|
234 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_MSB , 0);
|
235 |
|
|
for (i=0; i<18; i=i+1) begin
|
236 |
|
|
testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , dataRead);
|
237 |
|
|
$display("Data[0x%0x] = 0x%0x\n", i, dataRead);
|
238 |
|
|
end
|
239 |
|
|
$write("--- PASSED\n");
|
240 |
|
|
|
241 |
|
|
|
242 |
|
|
|
243 |
|
|
|
244 |
|
|
|
245 |
|
|
|
246 |
|
|
// --- get config descriptor
|
247 |
|
|
$write("Trans test: Device address = 0x12, get config descriptor. ");
|
248 |
|
|
USBAddress = 8'h012;
|
249 |
|
|
USBEndPoint = 8'h00;
|
250 |
|
|
transType = `SETUP_TRANS;
|
251 |
|
|
//enable endpoint, and make ready
|
252 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
253 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
254 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
255 |
|
|
bm_req_dir = 1'b1; // 0-Host to device; 1-device to host
|
256 |
|
|
bm_req_type = 2'b00; // 0-standard; 1-class; 2-vendor; 3-RESERVED
|
257 |
|
|
bm_req_recp = 5'b00000; // 0-device; 1-interface; 2-endpoint; 3-other 4..31-reserved
|
258 |
|
|
bRequest = `GET_DESCRIPTOR;
|
259 |
|
|
wValue = {`CFG_DESC, 8'h00};
|
260 |
|
|
wIndex = 16'h0000;
|
261 |
|
|
wLength = 16'h0009;
|
262 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , {bm_req_dir, bm_req_type, bm_req_recp});
|
263 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , bRequest);
|
264 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[7:0]);
|
265 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[15:8]);
|
266 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[7:0]);
|
267 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[15:8]);
|
268 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[7:0]);
|
269 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[15:8]);
|
270 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
271 |
|
|
#100000
|
272 |
|
|
//expecting transaction done interrupt
|
273 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
274 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
275 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h40);
|
276 |
|
|
$write("--- PASSED\n");
|
277 |
|
|
$write("Trans test: Device address = 0x12, 18 byte IN transaction to Endpoint 0. ");
|
278 |
|
|
USBAddress = 8'h12;
|
279 |
|
|
USBEndPoint = 8'h00;
|
280 |
|
|
transType = `IN_TRANS;
|
281 |
|
|
//enable endpoint, and make ready
|
282 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
283 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
284 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
285 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
286 |
|
|
#100000
|
287 |
|
|
//expecting transaction done interrupt
|
288 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
289 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
290 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h80);
|
291 |
|
|
$write("Checking receive data ");
|
292 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_LSB , 8'h09);
|
293 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_MSB , 0);
|
294 |
|
|
for (i=0; i<9; i=i+1) begin
|
295 |
|
|
testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , dataRead);
|
296 |
|
|
$display("Data[0x%0x] = 0x%0x\n", i, dataRead);
|
297 |
|
|
end
|
298 |
|
|
$write("--- PASSED\n");
|
299 |
|
|
|
300 |
|
|
|
301 |
|
|
|
302 |
|
|
// -- get mouse data from EP1
|
303 |
|
|
$write("Trans test: Device address = 0x12, 3 byte IN transaction to Endpoint 1. ");
|
304 |
|
|
USBAddress = 8'h12;
|
305 |
|
|
USBEndPoint = 8'h01;
|
306 |
|
|
transType = `IN_TRANS;
|
307 |
|
|
//enable endpoint, and make ready
|
308 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
|
309 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
|
310 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
|
311 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
|
312 |
|
|
#20000
|
313 |
|
|
//expecting transaction done interrupt
|
314 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
|
315 |
|
|
testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
|
316 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h00);
|
317 |
|
|
$write("Checking receive data ");
|
318 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 0);
|
319 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 1);
|
320 |
|
|
testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 1);
|
321 |
|
|
$write("--- PASSED\n");
|
322 |
|
|
|
323 |
|
|
$write("Finished all tests\n");
|
324 |
|
|
$stop;
|
325 |
|
|
|
326 |
|
|
end
|
327 |
|
|
|
328 |
|
|
endmodule
|
329 |
|
|
|