| 1 |
37 |
sfielding |
KEY LIBERO "8.3"
|
| 2 |
|
|
KEY CAPTURE "8.3.0.22"
|
| 3 |
|
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KEY DEFAULT_IMPORT_LOC "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\RTL"
|
| 4 |
|
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KEY DEFAULT_OPEN_LOC ""
|
| 5 |
|
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KEY HDLTechnology "VERILOG"
|
| 6 |
|
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KEY VendorTechnology_Family "IGLOO"
|
| 7 |
|
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KEY VendorTechnology_Die "IS6X6M2LP"
|
| 8 |
|
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KEY VendorTechnology_Package "fg256"
|
| 9 |
|
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KEY ProjectLocation "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop"
|
| 10 |
|
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KEY SimulationType "VERILOG"
|
| 11 |
|
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KEY Vendor "Actel"
|
| 12 |
|
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KEY ActiveRoot "usbDeviceActelTop::work"
|
| 13 |
|
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LIST REVISIONS
|
| 14 |
|
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VALUE="Impl1",NUM=1
|
| 15 |
|
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CURREV=1
|
| 16 |
|
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ENDLIST
|
| 17 |
|
|
LIST FileManager
|
| 18 |
|
|
VALUE "\constraint\usbDeviceActelTop.pdc,pdc"
|
| 19 |
|
|
STATE="utd"
|
| 20 |
|
|
TIME="1207237677"
|
| 21 |
|
|
SIZE="6506"
|
| 22 |
|
|
ENDFILE
|
| 23 |
|
|
VALUE "\designer\impl1\usbDevice.adb,adb"
|
| 24 |
|
|
STATE="ood"
|
| 25 |
|
|
TIME="1219427579"
|
| 26 |
|
|
SIZE="1078784"
|
| 27 |
|
|
ENDFILE
|
| 28 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.adb,adb"
|
| 29 |
|
|
STATE="utd"
|
| 30 |
|
|
TIME="1219440016"
|
| 31 |
|
|
SIZE="1136640"
|
| 32 |
|
|
ENDFILE
|
| 33 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.pdb,pdb"
|
| 34 |
|
|
STATE="utd"
|
| 35 |
|
|
TIME="1219441261"
|
| 36 |
|
|
SIZE="16384"
|
| 37 |
|
|
ENDFILE
|
| 38 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.stp,stp"
|
| 39 |
|
|
STATE="utd"
|
| 40 |
|
|
TIME="1219441266"
|
| 41 |
|
|
SIZE="293941"
|
| 42 |
|
|
ENDFILE
|
| 43 |
|
|
VALUE "\hdl\checkLineState.v,hdl"
|
| 44 |
|
|
STATE="utd"
|
| 45 |
|
|
TIME="1219425593"
|
| 46 |
|
|
SIZE="6885"
|
| 47 |
|
|
ENDFILE
|
| 48 |
|
|
VALUE "\hdl\dpMem_dc.v,hdl"
|
| 49 |
|
|
STATE="utd"
|
| 50 |
|
|
TIME="1219427411"
|
| 51 |
|
|
SIZE="3862"
|
| 52 |
|
|
ENDFILE
|
| 53 |
|
|
VALUE "\hdl\endpMux.v,hdl"
|
| 54 |
|
|
STATE="utd"
|
| 55 |
|
|
TIME="1219427470"
|
| 56 |
|
|
SIZE="8260"
|
| 57 |
|
|
ENDFILE
|
| 58 |
|
|
VALUE "\hdl\EP0.v,hdl"
|
| 59 |
|
|
STATE="utd"
|
| 60 |
|
|
TIME="1219425593"
|
| 61 |
|
|
SIZE="25833"
|
| 62 |
|
|
ENDFILE
|
| 63 |
|
|
VALUE "\hdl\EP1Mouse.v,hdl"
|
| 64 |
|
|
STATE="utd"
|
| 65 |
|
|
TIME="1219425593"
|
| 66 |
|
|
SIZE="9454"
|
| 67 |
|
|
ENDFILE
|
| 68 |
|
|
VALUE "\hdl\fifoMux.v,hdl"
|
| 69 |
|
|
STATE="utd"
|
| 70 |
|
|
TIME="1219427470"
|
| 71 |
|
|
SIZE="6575"
|
| 72 |
|
|
ENDFILE
|
| 73 |
|
|
VALUE "\hdl\fifoRTL.v,hdl"
|
| 74 |
|
|
STATE="utd"
|
| 75 |
|
|
TIME="1219427411"
|
| 76 |
|
|
SIZE="6307"
|
| 77 |
|
|
ENDFILE
|
| 78 |
|
|
VALUE "\hdl\hostSlaveMuxBI.v,hdl"
|
| 79 |
|
|
STATE="utd"
|
| 80 |
|
|
TIME="1219427436"
|
| 81 |
|
|
SIZE="4931"
|
| 82 |
|
|
ENDFILE
|
| 83 |
|
|
VALUE "\hdl\lineControlUpdate.v,hdl"
|
| 84 |
|
|
STATE="utd"
|
| 85 |
|
|
TIME="1219427458"
|
| 86 |
|
|
SIZE="3451"
|
| 87 |
|
|
ENDFILE
|
| 88 |
|
|
VALUE "\hdl\processRxBit.v,hdl"
|
| 89 |
|
|
STATE="utd"
|
| 90 |
|
|
TIME="1219427458"
|
| 91 |
|
|
SIZE="15071"
|
| 92 |
|
|
ENDFILE
|
| 93 |
|
|
VALUE "\hdl\processRxByte.v,hdl"
|
| 94 |
|
|
STATE="utd"
|
| 95 |
|
|
TIME="1219427458"
|
| 96 |
|
|
SIZE="17214"
|
| 97 |
|
|
ENDFILE
|
| 98 |
|
|
VALUE "\hdl\processTxByte.v,hdl"
|
| 99 |
|
|
STATE="utd"
|
| 100 |
|
|
TIME="1219427458"
|
| 101 |
|
|
SIZE="15227"
|
| 102 |
|
|
ENDFILE
|
| 103 |
|
|
VALUE "\hdl\readUSBWireData.v,hdl"
|
| 104 |
|
|
STATE="utd"
|
| 105 |
|
|
TIME="1219427458"
|
| 106 |
|
|
SIZE="10944"
|
| 107 |
|
|
ENDFILE
|
| 108 |
|
|
VALUE "\hdl\RxFifo.v,hdl"
|
| 109 |
|
|
STATE="utd"
|
| 110 |
|
|
TIME="1219427411"
|
| 111 |
|
|
SIZE="5079"
|
| 112 |
|
|
ENDFILE
|
| 113 |
|
|
VALUE "\hdl\RxFifoBI.v,hdl"
|
| 114 |
|
|
STATE="utd"
|
| 115 |
|
|
TIME="1219427411"
|
| 116 |
|
|
SIZE="5600"
|
| 117 |
|
|
ENDFILE
|
| 118 |
|
|
VALUE "\hdl\sctxportarbiter.v,hdl"
|
| 119 |
|
|
STATE="utd"
|
| 120 |
|
|
TIME="1219427470"
|
| 121 |
|
|
SIZE="7476"
|
| 122 |
|
|
ENDFILE
|
| 123 |
|
|
VALUE "\hdl\siereceiver.v,hdl"
|
| 124 |
|
|
STATE="utd"
|
| 125 |
|
|
TIME="1219427458"
|
| 126 |
|
|
SIZE="9992"
|
| 127 |
|
|
ENDFILE
|
| 128 |
|
|
VALUE "\hdl\SIETransmitter.v,hdl"
|
| 129 |
|
|
STATE="utd"
|
| 130 |
|
|
TIME="1219427458"
|
| 131 |
|
|
SIZE="24223"
|
| 132 |
|
|
ENDFILE
|
| 133 |
|
|
VALUE "\hdl\slavecontroller.v,hdl"
|
| 134 |
|
|
STATE="utd"
|
| 135 |
|
|
TIME="1219427470"
|
| 136 |
|
|
SIZE="17626"
|
| 137 |
|
|
ENDFILE
|
| 138 |
|
|
VALUE "\hdl\slaveDirectcontrol.v,hdl"
|
| 139 |
|
|
STATE="utd"
|
| 140 |
|
|
TIME="1219427470"
|
| 141 |
|
|
SIZE="7433"
|
| 142 |
|
|
ENDFILE
|
| 143 |
|
|
VALUE "\hdl\slaveGetpacket.v,hdl"
|
| 144 |
|
|
STATE="utd"
|
| 145 |
|
|
TIME="1219427470"
|
| 146 |
|
|
SIZE="12832"
|
| 147 |
|
|
ENDFILE
|
| 148 |
|
|
VALUE "\hdl\slaveRxStatusMonitor.v,hdl"
|
| 149 |
|
|
STATE="utd"
|
| 150 |
|
|
TIME="1219427470"
|
| 151 |
|
|
SIZE="3985"
|
| 152 |
|
|
ENDFILE
|
| 153 |
|
|
VALUE "\hdl\slaveSendpacket.v,hdl"
|
| 154 |
|
|
STATE="utd"
|
| 155 |
|
|
TIME="1219427470"
|
| 156 |
|
|
SIZE="9072"
|
| 157 |
|
|
ENDFILE
|
| 158 |
|
|
VALUE "\hdl\timescale.v,hdl"
|
| 159 |
|
|
STATE="utd"
|
| 160 |
|
|
TIME="1219427448"
|
| 161 |
|
|
SIZE="230"
|
| 162 |
|
|
ENDFILE
|
| 163 |
|
|
VALUE "\hdl\TxFifo.v,hdl"
|
| 164 |
|
|
STATE="utd"
|
| 165 |
|
|
TIME="1219427411"
|
| 166 |
|
|
SIZE="5002"
|
| 167 |
|
|
ENDFILE
|
| 168 |
|
|
VALUE "\hdl\TxFifoBI.v,hdl"
|
| 169 |
|
|
STATE="utd"
|
| 170 |
|
|
TIME="1219427411"
|
| 171 |
|
|
SIZE="5596"
|
| 172 |
|
|
ENDFILE
|
| 173 |
|
|
VALUE "\hdl\updateCRC16.v,hdl"
|
| 174 |
|
|
STATE="utd"
|
| 175 |
|
|
TIME="1219427458"
|
| 176 |
|
|
SIZE="4076"
|
| 177 |
|
|
ENDFILE
|
| 178 |
|
|
VALUE "\hdl\updateCRC5.v,hdl"
|
| 179 |
|
|
STATE="utd"
|
| 180 |
|
|
TIME="1219427458"
|
| 181 |
|
|
SIZE="4274"
|
| 182 |
|
|
ENDFILE
|
| 183 |
|
|
VALUE "\hdl\usbConstants_h.v,hdl"
|
| 184 |
|
|
STATE="utd"
|
| 185 |
|
|
TIME="1219427448"
|
| 186 |
|
|
SIZE="706"
|
| 187 |
|
|
ENDFILE
|
| 188 |
|
|
VALUE "\hdl\usbDevice.v,hdl"
|
| 189 |
|
|
STATE="utd"
|
| 190 |
|
|
TIME="1219425593"
|
| 191 |
|
|
SIZE="6821"
|
| 192 |
|
|
ENDFILE
|
| 193 |
|
|
VALUE "\hdl\usbDeviceActelTop.v,hdl"
|
| 194 |
|
|
STATE="utd"
|
| 195 |
|
|
TIME="1219440128"
|
| 196 |
|
|
SIZE="1329"
|
| 197 |
|
|
ENDFILE
|
| 198 |
|
|
VALUE "\hdl\usbDevice_define.v,hdl"
|
| 199 |
|
|
STATE="utd"
|
| 200 |
|
|
TIME="1219425593"
|
| 201 |
|
|
SIZE="1297"
|
| 202 |
|
|
ENDFILE
|
| 203 |
|
|
VALUE "\hdl\usbHostControl_h.v,hdl"
|
| 204 |
|
|
STATE="utd"
|
| 205 |
|
|
TIME="1219427448"
|
| 206 |
|
|
SIZE="2187"
|
| 207 |
|
|
ENDFILE
|
| 208 |
|
|
VALUE "\hdl\usbHostSlaveReg_define.v,hdl"
|
| 209 |
|
|
STATE="utd"
|
| 210 |
|
|
TIME="1219425593"
|
| 211 |
|
|
SIZE="5597"
|
| 212 |
|
|
ENDFILE
|
| 213 |
|
|
VALUE "\hdl\usbHostSlave_h.v,hdl"
|
| 214 |
|
|
STATE="utd"
|
| 215 |
|
|
TIME="1219427448"
|
| 216 |
|
|
SIZE="5297"
|
| 217 |
|
|
ENDFILE
|
| 218 |
|
|
VALUE "\hdl\usbROM.v,hdl"
|
| 219 |
|
|
STATE="utd"
|
| 220 |
|
|
TIME="1219425593"
|
| 221 |
|
|
SIZE="12466"
|
| 222 |
|
|
ENDFILE
|
| 223 |
|
|
VALUE "\hdl\usbSerialInterfaceEngine.v,hdl"
|
| 224 |
|
|
STATE="utd"
|
| 225 |
|
|
TIME="1219427458"
|
| 226 |
|
|
SIZE="11255"
|
| 227 |
|
|
ENDFILE
|
| 228 |
|
|
VALUE "\hdl\usbSerialInterfaceEngine_h.v,hdl"
|
| 229 |
|
|
STATE="utd"
|
| 230 |
|
|
TIME="1219427448"
|
| 231 |
|
|
SIZE="3284"
|
| 232 |
|
|
ENDFILE
|
| 233 |
|
|
VALUE "\hdl\usbSlave.v,hdl"
|
| 234 |
|
|
STATE="utd"
|
| 235 |
|
|
TIME="1219427483"
|
| 236 |
|
|
SIZE="15345"
|
| 237 |
|
|
ENDFILE
|
| 238 |
|
|
VALUE "\hdl\usbSlaveControl.v,hdl"
|
| 239 |
|
|
STATE="utd"
|
| 240 |
|
|
TIME="1219427470"
|
| 241 |
|
|
SIZE="15326"
|
| 242 |
|
|
ENDFILE
|
| 243 |
|
|
VALUE "\hdl\USBSlaveControlBI.v,hdl"
|
| 244 |
|
|
STATE="utd"
|
| 245 |
|
|
TIME="1219427470"
|
| 246 |
|
|
SIZE="24769"
|
| 247 |
|
|
ENDFILE
|
| 248 |
|
|
VALUE "\hdl\usbSlaveControl_h.v,hdl"
|
| 249 |
|
|
STATE="utd"
|
| 250 |
|
|
TIME="1219427448"
|
| 251 |
|
|
SIZE="2718"
|
| 252 |
|
|
ENDFILE
|
| 253 |
|
|
VALUE "\hdl\usbTxWireArbiter.v,hdl"
|
| 254 |
|
|
STATE="utd"
|
| 255 |
|
|
TIME="1219427458"
|
| 256 |
|
|
SIZE="7513"
|
| 257 |
|
|
ENDFILE
|
| 258 |
|
|
VALUE "\hdl\wishboneArb.v,hdl"
|
| 259 |
|
|
STATE="utd"
|
| 260 |
|
|
TIME="1219425593"
|
| 261 |
|
|
SIZE="5708"
|
| 262 |
|
|
ENDFILE
|
| 263 |
|
|
VALUE "\hdl\wishBoneBI.v,hdl"
|
| 264 |
|
|
STATE="utd"
|
| 265 |
|
|
TIME="1219427420"
|
| 266 |
|
|
SIZE="8684"
|
| 267 |
|
|
ENDFILE
|
| 268 |
|
|
VALUE "\hdl\wishBoneBus_h.v,hdl"
|
| 269 |
|
|
STATE="utd"
|
| 270 |
|
|
TIME="1219427448"
|
| 271 |
|
|
SIZE="1041"
|
| 272 |
|
|
ENDFILE
|
| 273 |
|
|
VALUE "\hdl\writeUSBWireData.v,hdl"
|
| 274 |
|
|
STATE="utd"
|
| 275 |
|
|
TIME="1219427458"
|
| 276 |
|
|
SIZE="8542"
|
| 277 |
|
|
ENDFILE
|
| 278 |
|
|
VALUE "\synthesis\usbDevice.edn,syn_edn"
|
| 279 |
|
|
STATE="utd"
|
| 280 |
|
|
TIME="1219427525"
|
| 281 |
|
|
SIZE="3585871"
|
| 282 |
|
|
ENDFILE
|
| 283 |
|
|
VALUE "\synthesis\usbDeviceActelTop.edn,syn_edn"
|
| 284 |
|
|
STATE="utd"
|
| 285 |
|
|
TIME="1219439810"
|
| 286 |
|
|
SIZE="3661567"
|
| 287 |
|
|
ENDFILE
|
| 288 |
|
|
VALUE "\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
|
| 289 |
|
|
STATE="utd"
|
| 290 |
|
|
TIME="1219439810"
|
| 291 |
|
|
SIZE="376"
|
| 292 |
|
|
ENDFILE
|
| 293 |
|
|
VALUE "\synthesis\usbDevice_sdc.sdc,syn_sdc"
|
| 294 |
|
|
STATE="utd"
|
| 295 |
|
|
TIME="1219427525"
|
| 296 |
|
|
SIZE="376"
|
| 297 |
|
|
ENDFILE
|
| 298 |
|
|
ENDLIST
|
| 299 |
|
|
LIST UsedFile
|
| 300 |
|
|
ENDLIST
|
| 301 |
|
|
LIST NewModulesInfo
|
| 302 |
|
|
LIST "usbDevice::work"
|
| 303 |
|
|
FILE "\hdl\usbDevice.v,hdl"
|
| 304 |
|
|
LIST ProjectState5.1
|
| 305 |
|
|
LIST Impl1
|
| 306 |
|
|
LiberoState=Post_Synthesis
|
| 307 |
|
|
ideSYNTHESIS(\synthesis\usbDevice.edn,syn_edn)=StateSuccess
|
| 308 |
|
|
LIST FlowOptions
|
| 309 |
|
|
UsePhySynth=FALSE
|
| 310 |
|
|
UseSynth=TRUE
|
| 311 |
|
|
ENDLIST
|
| 312 |
|
|
Used_File_List
|
| 313 |
|
|
VALUE "\synthesis\usbDevice.edn,syn_edn"
|
| 314 |
|
|
VALUE "\synthesis\usbDevice_sdc.sdc,syn_sdc"
|
| 315 |
|
|
VALUE "\synthesis\usbDevice.v,syn_hdl"
|
| 316 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.edn,palace_edn"
|
| 317 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.gcf,palace_gcf"
|
| 318 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.pdc,palace_pdc"
|
| 319 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.sdc,palace_sdc"
|
| 320 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.v,palace_hdl"
|
| 321 |
|
|
VALUE "\designer\impl1\usbDevice.adb,adb"
|
| 322 |
|
|
VALUE "\designer\impl1\usbDevice.prb,prb"
|
| 323 |
|
|
VALUE "\designer\impl1\usbDevice.stp,stp"
|
| 324 |
|
|
VALUE "\designer\impl1\usbDevice_fp\usbDevice.pro,pro"
|
| 325 |
|
|
ENDUsed_File_List
|
| 326 |
|
|
ENDLIST
|
| 327 |
|
|
ENDLIST
|
| 328 |
|
|
ENDLIST
|
| 329 |
|
|
LIST "usbDeviceActelTop::work"
|
| 330 |
|
|
FILE "\hdl\usbDeviceActelTop.v,hdl"
|
| 331 |
|
|
LIST ProjectState5.1
|
| 332 |
|
|
LIST Impl1
|
| 333 |
|
|
LiberoState=Post_Layout
|
| 334 |
|
|
ideDESIGNER(\designer\impl1\usbDeviceActelTop.adb,adb)=StateSuccess
|
| 335 |
|
|
ideSYNTHESIS(\synthesis\usbDeviceActelTop.edn,syn_edn)=StateSuccess
|
| 336 |
|
|
LIST FlowOptions
|
| 337 |
|
|
UsePhySynth=FALSE
|
| 338 |
|
|
UseSynth=TRUE
|
| 339 |
|
|
ENDLIST
|
| 340 |
|
|
Used_File_List
|
| 341 |
|
|
VALUE "\synthesis\usbDeviceActelTop.edn,syn_edn"
|
| 342 |
|
|
VALUE "\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
|
| 343 |
|
|
VALUE "\synthesis\usbDeviceActelTop.v,syn_hdl"
|
| 344 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.edn,palace_edn"
|
| 345 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.gcf,palace_gcf"
|
| 346 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.pdc,palace_pdc"
|
| 347 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.sdc,palace_sdc"
|
| 348 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.v,palace_hdl"
|
| 349 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.adb,adb"
|
| 350 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.prb,prb"
|
| 351 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.stp,stp"
|
| 352 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop_fp\usbDeviceActelTop.pro,pro"
|
| 353 |
|
|
ENDUsed_File_List
|
| 354 |
|
|
ENDLIST
|
| 355 |
|
|
ENDLIST
|
| 356 |
|
|
ENDLIST
|
| 357 |
|
|
ENDLIST
|
| 358 |
|
|
LIST AssociatedStimulus
|
| 359 |
|
|
ENDLIST
|
| 360 |
|
|
LIST Other_Association
|
| 361 |
|
|
ENDLIST
|
| 362 |
|
|
LIST SimulationOptions
|
| 363 |
|
|
UseAutomaticDoFile=true
|
| 364 |
|
|
IncludeWaveDo=false
|
| 365 |
|
|
Type=max
|
| 366 |
|
|
RunTime=1000ns
|
| 367 |
|
|
Resolution=1ps
|
| 368 |
|
|
VsimOpt=
|
| 369 |
|
|
EntityName=testbench
|
| 370 |
|
|
TopInstanceName=_0
|
| 371 |
|
|
DoFileName=
|
| 372 |
|
|
DoFileName2=wave.do
|
| 373 |
|
|
DoFileParams=
|
| 374 |
|
|
DisplayDUTWave=false
|
| 375 |
|
|
LogAllSignals=false
|
| 376 |
|
|
DumpVCD=false
|
| 377 |
|
|
VCDFileName=power.vcd
|
| 378 |
|
|
ENDLIST
|
| 379 |
|
|
LIST ModelSimLibPath
|
| 380 |
|
|
UseCustomPath=FALSE
|
| 381 |
|
|
LibraryPath=
|
| 382 |
|
|
ENDLIST
|
| 383 |
|
|
LIST GlobalFlowOptions
|
| 384 |
|
|
GenerateHDLAfterSynthesis=FALSE
|
| 385 |
|
|
GenerateHDLAfterPhySynthesis=FALSE
|
| 386 |
|
|
RunDRCAfterSynthesis=FALSE
|
| 387 |
|
|
UpdateViewDrawIni=TRUE
|
| 388 |
|
|
UpdateModelSimIni=TRUE
|
| 389 |
|
|
NoIOMode=FALSE
|
| 390 |
|
|
GenerateHDLFromSchematic=TRUE
|
| 391 |
|
|
FlashProInputFile=pdb
|
| 392 |
|
|
SmartGenCompileReport=T
|
| 393 |
|
|
ENDLIST
|
| 394 |
|
|
LIST PhySynthesisOptions
|
| 395 |
|
|
ENDLIST
|
| 396 |
|
|
LIST Profiles
|
| 397 |
|
|
Type=CoreConfigurator
|
| 398 |
|
|
Profile=CoreConsole
|
| 399 |
|
|
Tool=CoreConsole v1.3 or later
|
| 400 |
|
|
Location=coreconsole
|
| 401 |
|
|
AdditionalParameter=
|
| 402 |
|
|
Batch=false
|
| 403 |
|
|
EndProfile
|
| 404 |
|
|
Type=Synthesis
|
| 405 |
|
|
Profile=Synplify
|
| 406 |
|
|
Tool=Synplify
|
| 407 |
|
|
Location=C:\Libero\Synplify\Synplify_902A2\bin\Synplify.exe
|
| 408 |
|
|
AdditionalParameter=
|
| 409 |
|
|
Batch=false
|
| 410 |
|
|
EndProfile
|
| 411 |
|
|
Type=Simulation
|
| 412 |
|
|
Profile=ModelSim
|
| 413 |
|
|
Tool=ModelSim
|
| 414 |
|
|
Location=C:\Libero\Model\win32acoem\modelsim.exe
|
| 415 |
|
|
AdditionalParameter=
|
| 416 |
|
|
Batch=false
|
| 417 |
|
|
EndProfile
|
| 418 |
|
|
Type=Stimulus
|
| 419 |
|
|
Profile=WFL
|
| 420 |
|
|
Tool=WFL
|
| 421 |
|
|
Location=C:\Libero\WFL\bin\syncad.exe
|
| 422 |
|
|
AdditionalParameter=-pwflite
|
| 423 |
|
|
Batch=false
|
| 424 |
|
|
EndProfile
|
| 425 |
|
|
Type=PhySynthesis
|
| 426 |
|
|
Profile=
|
| 427 |
|
|
Tool=
|
| 428 |
|
|
Location=
|
| 429 |
|
|
AdditionalParameter=
|
| 430 |
|
|
Batch=false
|
| 431 |
|
|
EndProfile
|
| 432 |
|
|
Type=Program
|
| 433 |
|
|
Profile=FlashPro
|
| 434 |
|
|
Tool=FlashPro
|
| 435 |
|
|
Location=C:\Libero\FlashPro\bin\FlashPro.exe
|
| 436 |
|
|
AdditionalParameter=
|
| 437 |
|
|
Batch=false
|
| 438 |
|
|
EndProfile
|
| 439 |
|
|
ENDLIST
|
| 440 |
|
|
LIST ProjectState5.1
|
| 441 |
|
|
LIST "usbDevice::work"
|
| 442 |
|
|
LIST Impl1
|
| 443 |
|
|
LiberoState=Post_Synthesis
|
| 444 |
|
|
ideSYNTHESIS(\synthesis\usbDevice.edn,syn_edn)=StateSuccess
|
| 445 |
|
|
LIST FlowOptions
|
| 446 |
|
|
UsePhySynth=FALSE
|
| 447 |
|
|
UseSynth=TRUE
|
| 448 |
|
|
ENDLIST
|
| 449 |
|
|
Used_File_List
|
| 450 |
|
|
VALUE "\synthesis\usbDevice.edn,syn_edn"
|
| 451 |
|
|
VALUE "\synthesis\usbDevice_sdc.sdc,syn_sdc"
|
| 452 |
|
|
VALUE "\synthesis\usbDevice.v,syn_hdl"
|
| 453 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.edn,palace_edn"
|
| 454 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.gcf,palace_gcf"
|
| 455 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.pdc,palace_pdc"
|
| 456 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.sdc,palace_sdc"
|
| 457 |
|
|
VALUE "\phy_synthesis\usbDevice_palace.v,palace_hdl"
|
| 458 |
|
|
VALUE "\designer\impl1\usbDevice.adb,adb"
|
| 459 |
|
|
VALUE "\designer\impl1\usbDevice.prb,prb"
|
| 460 |
|
|
VALUE "\designer\impl1\usbDevice.stp,stp"
|
| 461 |
|
|
VALUE "\designer\impl1\usbDevice_fp\usbDevice.pro,pro"
|
| 462 |
|
|
ENDUsed_File_List
|
| 463 |
|
|
ENDLIST
|
| 464 |
|
|
ENDLIST
|
| 465 |
|
|
LIST "usbDeviceActelTop::work"
|
| 466 |
|
|
LIST Impl1
|
| 467 |
|
|
LiberoState=Post_Layout
|
| 468 |
|
|
ideDESIGNER(\designer\impl1\usbDeviceActelTop.adb,adb)=StateSuccess
|
| 469 |
|
|
ideSYNTHESIS(\synthesis\usbDeviceActelTop.edn,syn_edn)=StateSuccess
|
| 470 |
|
|
LIST FlowOptions
|
| 471 |
|
|
UsePhySynth=FALSE
|
| 472 |
|
|
UseSynth=TRUE
|
| 473 |
|
|
ENDLIST
|
| 474 |
|
|
Used_File_List
|
| 475 |
|
|
VALUE "\synthesis\usbDeviceActelTop.edn,syn_edn"
|
| 476 |
|
|
VALUE "\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
|
| 477 |
|
|
VALUE "\synthesis\usbDeviceActelTop.v,syn_hdl"
|
| 478 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.edn,palace_edn"
|
| 479 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.gcf,palace_gcf"
|
| 480 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.pdc,palace_pdc"
|
| 481 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.sdc,palace_sdc"
|
| 482 |
|
|
VALUE "\phy_synthesis\usbDeviceActelTop_palace.v,palace_hdl"
|
| 483 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.adb,adb"
|
| 484 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.prb,prb"
|
| 485 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop.stp,stp"
|
| 486 |
|
|
VALUE "\designer\impl1\usbDeviceActelTop_fp\usbDeviceActelTop.pro,pro"
|
| 487 |
|
|
ENDUsed_File_List
|
| 488 |
|
|
ENDLIST
|
| 489 |
|
|
ENDLIST
|
| 490 |
|
|
ENDLIST
|
| 491 |
|
|
LIST ExcludePackageForSimulation
|
| 492 |
|
|
ENDLIST
|
| 493 |
|
|
LIST ExcludePackageForSynthesis
|
| 494 |
|
|
ENDLIST
|
| 495 |
|
|
LIST IncludeModuleForSimulation
|
| 496 |
|
|
ENDLIST
|
| 497 |
|
|
LIST CDBOrder
|
| 498 |
|
|
ENDLIST
|
| 499 |
|
|
LIST UserCustomizedFileList
|
| 500 |
|
|
ENDLIST
|
| 501 |
|
|
LIST OpenedFileList
|
| 502 |
|
|
DESIGNFLOW:
|
| 503 |
|
|
ACTIVE_VIEW:0
|
| 504 |
|
|
ENDLIST
|
