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# Copyright (C) 1991-2006 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# cyc_or12_mini_top_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C20Q240C8
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set_global_assignment -name TOP_LEVEL_ENTITY usbDeviceAlteraTop
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "06:48:46 JUNE 20, 2007"
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set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
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#48MHz local oscillator
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set_global_assignment -name FMAX_REQUIREMENT "20.83 ns" -section_id clk
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set_global_assignment -name DUTY_CYCLE 50 -section_id clk
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set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
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set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
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set_location_assignment PIN_30 -to clk
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set_location_assignment PIN_97 -to mc_addr[0]
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set_location_assignment PIN_96 -to mc_addr[1]
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set_location_assignment PIN_90 -to mc_addr[2]
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set_location_assignment PIN_166 -to mc_addr[3]
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set_location_assignment PIN_165 -to mc_addr[4]
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set_location_assignment PIN_164 -to mc_addr[5]
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set_location_assignment PIN_162 -to mc_addr[6]
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set_location_assignment PIN_161 -to mc_addr[7]
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set_location_assignment PIN_159 -to mc_addr[8]
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set_location_assignment PIN_157 -to mc_addr[9]
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set_location_assignment PIN_100 -to mc_addr[10]
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set_location_assignment PIN_109 -to mc_addr[11]
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set_location_assignment PIN_106 -to mc_ba[0]
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set_location_assignment PIN_105 -to mc_ba[1]
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set_location_assignment PIN_113 -to mc_cas_
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set_location_assignment PIN_156 -to mc_cke_
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set_location_assignment PIN_155 -to sdram_clk
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set_location_assignment PIN_110 -to sdram_cs
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set_location_assignment PIN_116 -to mc_dqm[0]
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set_location_assignment PIN_150 -to mc_dqm[1]
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set_location_assignment PIN_88 -to mc_dqm[2]
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set_location_assignment PIN_167 -to mc_dqm[3]
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set_location_assignment PIN_111 -to mc_ras_
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set_location_assignment PIN_114 -to mc_we_
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set_location_assignment PIN_47 -to spiClk
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set_location_assignment PIN_20 -to spiMasterDataOut
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set_location_assignment PIN_44 -to spiCS_n
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#set_location_assignment PIN_18 -to usbHostOE_n
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#set_location_assignment PIN_8 -to usbSlaveVP
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#set_location_assignment PIN_7 -to usbSlaveVM
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#set_location_assignment PIN_9 -to usbSlaveOE_n
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#set_location_assignment PIN_13 -to usbDPlusPullup
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#set_location_assignment PIN_4 -to vBusDetect
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# Santa Cruz Connector
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set_location_assignment PIN_16 -to SC_P_CLK
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set_location_assignment PIN_15 -to SC_PCS_N
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set_location_assignment PIN_188 -to SC_RST_N
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set_location_assignment PIN_191 -to SC_P0
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set_location_assignment PIN_189 -to SC_P1
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set_location_assignment PIN_194 -to SC_P2
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set_location_assignment PIN_192 -to SC_P3
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set_location_assignment PIN_199 -to SC_P4
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set_location_assignment PIN_197 -to SC_P5
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set_location_assignment PIN_208 -to SC_P6
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set_location_assignment PIN_203 -to SC_P7
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set_location_assignment PIN_218 -to SC_P8
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set_location_assignment PIN_216 -to SC_P9
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set_location_assignment PIN_226 -to SC_P10
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set_location_assignment PIN_223 -to SC_P11
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set_location_assignment PIN_231 -to SC_P12
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set_location_assignment PIN_230 -to SC_P13
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set_location_assignment PIN_234 -to SC_P14
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set_location_assignment PIN_233 -to SC_P15
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set_location_assignment PIN_236 -to SC_P16
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set_location_assignment PIN_237 -to SC_P17
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set_location_assignment PIN_238 -to SC_P18
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set_location_assignment PIN_5 -to SC_P19
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set_location_assignment PIN_4 -to SC_P20
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set_location_assignment PIN_6 -to SC_P21
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set_location_assignment PIN_7 -to SC_P22
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set_location_assignment PIN_8 -to SC_P23
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set_location_assignment PIN_9 -to SC_P24
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set_location_assignment PIN_11 -to SC_P25
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set_location_assignment PIN_13 -to SC_P26
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set_location_assignment PIN_14 -to SC_P27
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set_location_assignment PIN_18 -to SC_P28
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set_location_assignment PIN_184 -to SC_P29
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set_location_assignment PIN_185 -to SC_P30
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set_location_assignment PIN_186 -to SC_P31
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set_location_assignment PIN_187 -to SC_P32
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set_location_assignment PIN_195 -to SC_P33
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set_location_assignment PIN_200 -to SC_P34
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set_location_assignment PIN_214 -to SC_P35
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set_location_assignment PIN_222 -to SC_P36
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set_location_assignment PIN_228 -to SC_P37
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set_location_assignment PIN_232 -to SC_P38
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set_location_assignment PIN_235 -to SC_P39
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
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set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 1000
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
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set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
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set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
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set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_instance_assignment -name CLOCK_SETTINGS clk -to clk
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set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
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set_global_assignment -name USER_LIBRARIES "..\\..\\..\\rtl\\include;..\\..\\rtl"
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set_global_assignment -name VERILOG_FILE ../../../RTL/wrapper/usbSlave.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/USBSlaveControlBI.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/endpMux.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/fifoMux.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/sctxportarbiter.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slavecontroller.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveDirectcontrol.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveGetpacket.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveRxStatusMonitor.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveSendpacket.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/usbSlaveControl.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/writeUSBWireData.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/lineControlUpdate.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processRxBit.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processRxByte.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processTxByte.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/readUSBWireData.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/siereceiver.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/SIETransmitter.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/updateCRC5.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/updateCRC16.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/usbTxWireArbiter.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/hostSlaveMux/hostSlaveMuxBI.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/hostSlaveMux/hostSlaveMux.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/busInterface/wishBoneBI.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/TxFifoBI.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/dpMem_dc.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/fifoRTL.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/RxFifo.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/RxFifoBI.v
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set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/TxFifo.v
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set_global_assignment -name VERILOG_FILE ../../RTL/wishboneArb.v
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set_global_assignment -name VERILOG_FILE ../../RTL/checkLineState.v
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set_global_assignment -name VERILOG_FILE ../../RTL/EP0.v
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set_global_assignment -name VERILOG_FILE ../../RTL/EP1Mouse.v
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set_global_assignment -name VERILOG_FILE ../../RTL/pll_48MHz.v
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set_global_assignment -name VERILOG_FILE ../../RTL/usbDevice.v
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set_global_assignment -name VERILOG_FILE ../../RTL/usbDevice_define.v
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set_global_assignment -name VERILOG_FILE ../../RTL/usbDeviceAlteraTop.v
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set_global_assignment -name VERILOG_FILE ../../RTL/usbHostSlaveReg_define.v
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set_global_assignment -name VERILOG_FILE ../../RTL/usbROM.v
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set_global_assignment -name SDC_FILE usbDeviceAlteraTop.sdc
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