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# Generated by Xilinx Architecture Wizard

# --- UCF Template Only ---

# Cut and paste these attributes into the project's UCF file, if desired

INST DCM_SP_INST CLK_FEEDBACK = 1X;

INST DCM_SP_INST CLKDV_DIVIDE = 2.0;

INST DCM_SP_INST CLKFX_DIVIDE = 1;

INST DCM_SP_INST CLKFX_MULTIPLY = 4;

INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;

INST DCM_SP_INST CLKIN_PERIOD = 20.833;

INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;

INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;

INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;

INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;

INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;

INST DCM_SP_INST FACTORY_JF = C080;

INST DCM_SP_INST PHASE_SHIFT = 0;

INST DCM_SP_INST STARTUP_WAIT = FALSE;